|Publication number||US20060057852 A1|
|Application number||US 11/271,408|
|Publication date||Mar 16, 2006|
|Filing date||Nov 9, 2005|
|Priority date||Sep 25, 2003|
|Also published as||US7112534, US20050070116|
|Publication number||11271408, 271408, US 2006/0057852 A1, US 2006/057852 A1, US 20060057852 A1, US 20060057852A1, US 2006057852 A1, US 2006057852A1, US-A1-20060057852, US-A1-2006057852, US2006/0057852A1, US2006/057852A1, US20060057852 A1, US20060057852A1, US2006057852 A1, US2006057852A1|
|Inventors||Qiang Fu, James Jeong|
|Original Assignee||Qiang Fu, James Jeong|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Referenced by (10), Classifications (5), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This U.S. Patent application is a divisional of U.S. patent application Ser. No. 10/672,357 filed Sep. 25, 2003.
The present invention relates to the field of microelectronic processing, and more particularly to methods of processing a resist layer in the fabrication of integrated circuits, and structures formed thereby.
Resist layers (sometimes called photoresist layers to imply the lithographic processes typically used with them) are frequently used to generate masks during the fabrication of integrated circuits. Typically, a layer of resist material 304 is deposited on the surface of an underlying layer 302 to be patterned, and then the resist layer 304 is exposed to light 300 that is passed through an exposure pattern 301 (see
The areas of underlying layer 302 that are not directly covered by the resist material 304 are removed through an etch process, such as a plasma etch, with the mask of resist material 304 preventing removal of those portions of the underlying material that are directly under the resist material 304 (
The deterioration is typically greatest at the sidewalls 306 of the resist material 304, i.e., a post-etch sidewall angle 308′ of the sidewalls 306 is less than the pre-etch sidewall angle 308 of the sidewall 306, which results in a sloped resist sidewall 306. Circuit features, such as trenches, that may be etched in a substrate, for example, a low k dielectric material, may exhibit significant sloping because the sidewalls 306 of the resist material 304 that define those features are unintentionally etched away (
In addition, resist material that is designed for exposure to light with a wavelength of approximately 193 nanometers (which is commonly used for sub 0.13 micron circuit features) is particularly susceptible to deterioration during the plasma etch. To improve etch resistance, one common approach is to increase the carbon-to-hydrogen ratio in the resist material while maintaining its transparency to exposure light. Several available options have been utilized, such as multi-ringed aliphatic groups, poly methyl methacrylate, or cyclo olefin-maleic anhydride copolymer platforms. However, these approaches have limited success in achieving etch resistance comparable with 248 nm resist, which is commonly used for circuit features greater than about 0.13 microns.
Therefore, there is a need for improved methods of plasma etching that reduce the deterioration of deep ultraviolet (uv) resist material, such as 193 nm resist material, so that underlying features do not exhibit sloping which can lead to device failure. The present invention provides such methods and their associated structures.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that the various embodiments of the invention, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the invention. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the claims are entitled. In the drawings, like numerals refer to the same or similar functionality throughout the several views.
Methods of forming a microelectronic structure and its associated structures are described. Those methods comprise forming and patterning a deep uv resist layer on a substrate, and etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.
A dielectric layer 102 may be disposed on the etch stop layer 101 of the substrate 104. The dielectric layer 102 may including but is not limited to silicon dioxide, silicon nitride, silicon oxynitride, and the like. The dielectric layer 102 may also preferably comprise a low k dielectric material, in which the dielectric constant of the low k dielectric layer is below about 4. Examples of such a low k dielectric material may include but are not limited to carbon doped oxide, organic polymers such as a polyimide, parylene, polyarylether, organo-silicone, polynaphthalene, polyquinoline, or copolymers thereof, spin on glass materials, either doped or undoped, or porous materials such as xerogels and others that include templated pores.
A sacrificial light absorbing layer 103 may be disposed on the dielectric layer 102 of the substrate 104. The sacrificial light absorbing layer 103 may including but is not limited to a spin-on-polymer (SOP) or spin-on-glass (SOG) combined with a dye. The organic or inorganic material chosen for the dye preferably should absorb light that is used during the exposure step of the photolithographic patterning process, which improves the process control of feature definition values, such as critical dimension values (i.e., CD's) as are well known in the art. For example, the dye type and amount, and the type of base material, used to form the sacrificial light absorbing layer 103 may be selected and tuned to absorb deep ultraviolet or shorter, wavelengths (e.g., a wavelength below about 200 nm), The sacrificial light absorbing layer 103 may be formed on the dielectric layer 102 by spin coating the sacrificial light absorbing layer 103 using conventional process steps known in the art. It will be understood that the substrate 104 may comprise other materials commonly used in microelectronic manufacturing, and that the etch stop layer 101, the dielectric layer 102 and the sacrificial light absorbing layer 103 may be substituted for other layers depending on the application.
As shown in
The deep uv resist layer 106 is then patterned utilizing methods well known in the art (
An etch may be performed on the substrate 104 by exposing the substrate to a plasma utilizing a gas comprising a carbon atom to fluorine atom ratio of between about 1:1 to about 2:3. By illustration and not limitation, such a gas may comprise hexafluorobutane (C4F6). The 1:1 to about 2:3 carbon to fluorine ratio gas may have a flow rate that is from about 10 to about 50 sccm. The plasma may also comprise an argon gas that may have a flow rate from about 100 to about 1000 sccm, and the plasma may also comprise a nitrogen gas that may have a flow from about 50 to about 1000 sccm. The plasma may be generated using conventional techniques and equipment, such as reactive ion etching (RIE), inductively coupled plasma (ICP) etc. The power may be from about 1KW to about 4KW. The pressure may be from about 15 to about 100 millitorr.
Etching the substrate 104 in the aforementioned plasma produces a polymer 112 on the sidewalls 108 of the deep uv resist layer 106 as well as on the substrate sidewalls 109, shown in
Therefore, the pattern transferred by the deep uv resist layer 106 is not sloped as in the prior art (see
In another embodiment of the method of the present invention, as shown in step 210 of
Thus, after the first etch of step 220 a structure similar to the structure in
At step 230, a second etch may be performed on the dielectric layer wherein the pressure is from about 15 to about 100 millitorr, the power may be from about 1 to about 4 KW, a C4 F6 flow rate may be from about 10 to about 50 sccm, an argon flow rate may be from about 100 to about 1000 sccm, and a nitrogen flow rate may be from about 50 to about 100 sccm. Etching of the dielectric layer in the current embodiment may be stopped before substantially etching an underlying layer, such as an etch stop layer, by methods previously described herein.
Thus, after the second etch of step 230 a structure similar to the structure in
The trench 116 may comprise a first surface 118, a trench sidewall 124, a bottom width 120 and a top width 122. The ratio of the bottom width 120 to the top width 122 is preferably about 1:1, due to the sidewall 108 passivation of the deep uv resist layer 106 by the polymer 112 during the plasma etch of the current embodiment. Thus, the method of the current embodiment enables the formation of a trench 116 that comprises substantially vertical trench sidewalls 124, wherein the trench sidewalls 124 in the current embodiment comprise the dielectric layer 102.
In a preferred embodiment of the method of the present invention, as shown in step 240 of
At step 260, a second etch may be performed on the dielectric layer wherein the pressure is from about 90 to about 110 millitorr, the power may be from about 1 to about 4 KW, a C4 F6 flow rate may be from about 10 to about 14 sccm, an argon flow rate may be from about 290 to about 350 sccm, and a nitrogen flow rate may be from about 25 to about 40 sccm. Etching of the dielectric layer in the current embodiment may be stopped before substantially etching an underlying layer, such as an etch stop layer, by methods previously described herein.
Thus, after the second etch of step 260 a structure similar to the structure in
As described above, the present invention provides methods and associated structures of forming and patterning a deep uv resist layer, such as a 193 nm resist layer, on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer. The methods and structures of the present invention enable the use of deep ultraviolet resists, such as 193 nm resist, by preventing the deep uv resist degradation in a plasma etch, thus greatly reducing shorting between adjacent device features and therefore enhancing the performance and reliability of a device fabricated according to the various embodiments of the present invention.
Although the foregoing description has specified certain steps and materials that may be used in the method of the present invention, those skilled in the art will appreciate that many modifications and substitutions may be made. Accordingly, it is intended that all such modifications, alterations, substitutions and additions be considered to fall within the spirit and scope of the invention as defined by the appended claims. In addition, it is appreciated that the fabrication of a multiple layer structure atop a substrate, such as a silicon substrate, to manufacture a microelectronic device is well known in the art. Therefore, it is appreciated that the Figures provided herein illustrate only portions of an exemplary microelectronic device that pertains to the practice of the present invention. Thus the present invention is not limited to the structures described herein.
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|U.S. Classification||438/702, 257/E21.256|
|Nov 9, 2005||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FU, QIANG;JEONG, JAMES;REEL/FRAME:017252/0580;SIGNING DATES FROM 20031017 TO 20031020