US 20060060920 A1
A CMOS gate stack that increases the inversion capacitance compared to a conventional CMOS gate stack has been described. Using a poly-SiGe gate, instead of the conventional poly-Si gate near the gate dielectric layer, increases the amount of implanted dopant that can be activated. This increase overcomes the polysilicon depletion problem that limits the inversion capacitance in the conventional CMOS gate stack. To integrate the poly-SiGe layer into the gate stack, a thin α-Si layer is deposited between the gate dielectric layer and the poly-SiGe layer. To ensure proper salicide formation, a poly-Si layer is capped over the poly-SiGe layer. In order to obtain a fined-grained poly-Si over poly-SiGe, a second α-Si layer is deposited between the poly-Si layer and the poly-SiGe layer.
1. A gate stack for semiconductor MOS device comprising:
a dielectric film formed on a semiconductor substrate of said semiconductor MOS device;
a first α-Si layer formed on the dielectric film;
a poly-SiGe layer formed on the first α-Si layer;
a second α-Si layer formed on the poly-SiGe layer; and
a poly-Si layer formed on the second α-Si layer.
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10. A method of depositing an α-Si layer on a substrate, comprising:
placing the substrate in a chamber;
introducing a first Si-containing source gas into the chamber; and
introducing a second Si-containing source gas into the chamber until an α-Si layer of less than about 50 Å thickness has been deposited on said substrate.
11. The method of
12. The method of
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17. A method of forming a gate stack on a semiconductor substrate, comprising:
depositing a dielectric layer on top of the semiconductor substrate;
depositing a first α-Si layer on the dielectric film;
depositing a poly-SiGe layer on the first α-Si layer;
depositing a second α-Si layer on the poly-SiGe layer; and
depositing a poly-Si layer on the second α-Si layer.
18. The method at
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1. Field of the Invention
The embodiments of the present invention relate to a poly-silicon-germanium (poly-SiGe) gate stack for semiconductor device and a method for forming the same.
2. Description of the Related Art
Transistor drive currents and hence switching speeds for CMOS (complementary metal oxide semiconductor) devices increase with increasing inversion capacitance. One of the factors that limit inversion capacitance is charge carrier depletion in conventional poly-Si gate electrodes during inversion. Alternative gate electrode materials for CMOS devices used in high performance logic circuits are needed to circumvent polysilicon (or poly-Si) depletion.
Using metal gates, whose charge carrier concentrations exceed the carrier concentration of poly-Si by at least two orders of magnitude, virtually eliminates the poly-Si depletion effect. However, the integration of metal gates into a conventional CMOS flow is complicated due to process integration difficulties. Primarily, metal gates lack the thermal and chemical stability that is necessary to survive subsequent high temperature anneals. Deposition and patterning of metal gates are also presently immature.
An alternative approach is to use poly-SiGe (poly-silicon-germanium) gates instead of conventional poly-Si gates. Germanium (Ge) incorporation into poly-Si enhances doping to increase the amount of implanted dopants that can be activated. This is particularly true of dopants such as boron. The higher dopant activation results in a higher charge carrier concentration and a concomitant reduction in gate electrode depletion during inversion. In addition, SiGe is a mid-gap semiconductor material so that threshold voltages for NMOS and PMOS devices are almost equal in magnitude with opposite polarity. Complementary threshold voltages are necessary for proper CMOS circuit operation. A further advantage of poly-SiGe is that the material is chemically similar to poly-Si. This calls for minimal adjustment to the process integration scheme to accommodate poly-SiGe. Poly-SiGe is thermally stable and can survive the thermal cycling that devices are subjected to during the fabrication sequence.
The embodiments of the present invention provide a poly-SiGe gate for a CMOS device that reduces charge carrier depletion.
In one embodiment, a gate stack for semiconductor MOS device comprises a dielectric film formed on a semiconductor substrate of said semiconductor MOS device, a first α-Si layer formed on the dielectric film, a poly-SiGe layer formed on the first α-Si layer, a second α-Si layer formed on the poly-SiGe layer, and a poly-Si layer formed on the second α-Si layer.
In another embodiment, a method of depositing an α-Si layer on a substrate comprises placing the substrate in a chamber, introducing a first Si-containing source gas into the chamber, and introducing a second Si-containing source gas into the chamber until an α-Si layer of less than about 50 Å thickness has been deposited on said substrate.
In another embodiment, a method of forming a gate stack on a substrate comprises depositing a thin dielectric layer on top of the substrate, depositing a first α-Si layer on the dielectric film, depositing a poly-SiGe layer on the first α-Si layer, depositing a second α-Si layer on the poly-SiGe layer, and depositing a poly-Si layer on the second α-Si layer.
So that the manner in which the features of the invention described herein are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. Also note that the drawings are not to scale.
Poly-SiGe gates, where the concentration of Ge is between about 5 atomic % to about 40 atomic %, reduce gate electrode depletion during inversion, but they cannot be deposited directly on a SiO2-based gate dielectric because Ge etches the gate oxide resulting in volatile GeO formation. GeO formation inhibits the growth of a high quality poly-SiGe film. This chemical incompatibility makes it desirable to incorporate a thin α-Si (amorphous silicon) layer in between the gate dielectric and the poly-SiGe.
Insertion of an undoped α-Si layer in between the poly-SiGe and gate dielectric, however, exacerbates the dopant depletion problem. This problem can be rectified if the α-Si layer is thin enough so that it gets doped during subsequent high temperature processing by out-diffusion of Ge and other dopants from the adjoining poly-SiGe layer. Experimentally it has been found that the α-Si layer must be at least 30-50 Å. If this layer is too thin, it runs the danger of Ge attack of the gate dielectric, since the Ge can diffuse through the weak points in the poly-SiGe film during subsequent high temperature processing. If the layer is too thick, dopant depletion, one of the primary motivations for using poly-SiGe gate electrodes, is not mitigated, and may even increase. Also, the work function of the gate electrode depends on the work function of the material adjacent to the gate electrode. If the α-Si is too thick it will exhibit the work function of poly-Si after anneal. If the α-Si is sufficiently thin, Ge from the adjoining poly-SiGe will diffuse into the α-Si during subsequent thermal annealing and alter the work function to that of poly-SiGe.
A fine-grained poly-Si or poly-SiGe is also desirable. First, with a fine grain size, implanted dopants are more uniformly distributed across the grain. For large grained films, dopants may segregate at the grain boundaries diminishing the electrically active dopant concentration. Secondly, fine-grained films generally result in etched lines with smooth edges. Line edge roughness for gate electrodes can increase sub-threshold slope and threshold voltage spread, both of which are undesirable in high performance devices. Thirdly, silicide formation and transformation of the silicide from the initial as-formed high-resistivity phase to the lower resistivity phase following thermal anneal is favored by a finer grain size.
One way to improve the morphology of poly-Si deposited on poly-SiGe is to insert a thin α-Si layer in between the poly-SiGe and poly-Si layers. The α-Si layer can retain its amorphous microstructure during poly-Si deposition. The growth of poly-Si on poly-SiGe with an intervening layer of α-Si will not be hetero-epitaxial. Therefore, the poly-Si grain structure will be more akin to that obtained when the film is deposited directly on an amorphous surface, such as an SiO2 layer.
Deposition of the thin α-Si layer 207, poly-SiGe layer 208 and thin α-Si layer 209 can be achieved by employing novel sequencing of process gases and use of alternative process gases in reactors that are amenable to rapid gas flow and temperature cycling. The invention is illustratively described below with reference to a mini-batch low pressure chemical vapor deposition (LPCVD) system, FlexStar, such as those commercially available from Applied Materials, Inc. of Santa Clara, Calif. However, it should be understood that the invention has utility in other system configurations such as single-wafer LPCVD systems or other applicable LPCVD systems. All of the experiments reported here were performed on FlexStar system. The relevant details of the FlexStar system and its application to CVD processes can be found in commonly assigned U.S. Pat. No. 6,353,593, issued on Mar. 5, 2002, and U.S. patent application Ser. No. 10/216,079, filed Aug. 9, 2002, both of which are incorporated herein by reference.
This FlexStar system utilizes cross wafer gas flow, i.e., the process gases flow across the wafer surface. Cross wafer gas flow has several advantages for this application. First, reactant and dopant concentrations are uniform across the surface of the wafer. Secondly, each wafer receives the same dose of reactants resulting in good wafer-to-wafer uniformity. Thirdly, the residence time of the gases in the vicinity of the wafer can be controlled through the gas flow. Control of gas residence times is crucial for ultra-thin depositions in which film deposition must begin simultaneously across the wafer. Residence times also define the extent of gas phase reactions.
The wafer temperature can also be cycled for different process steps in a sequential process. For a poly-SiGe/poly-Si stack, the process temperature has to be increased by about 100° C. while transitioning from deposition of poly-SiGe to deposition of poly-Si. Temperature cycling is difficult to implement in a conventional vertical diffusion furnace, but the unique architecture of the FlexStar system makes this possible.
The method 300 according to the invention includes the following steps shown in
Alternatively, as shown in
Using the methods described above, nucleation delays can be reduced to nearly zero and an adequately low deposition rate can be achieved for controllable deposition of 30-50 Å α-Si films. A specific example of processing conditions for the modified process to deposit a 50 Å α-Si seed layer are described below.
Step 1: 0.2 sIm Si2H6, 2.0 sIm SiH4, 0.0 slm diluent N2, 0.4 Torr, 520° C., for 30 seconds.
Step 2: 0.0 slm Si2H6, 2.0 slm SiHJ4, 0.0 slm diluent N2, 0.4 Torr, 520° C., 150 seconds.
Step 1: 0.15 slm Si2H6, 2.3 slm diluent N2, 0.4 Torr, 520° C., 30 seconds.
Step 2: 2.0 slm SiH4, 0.0 slm diluent N2, 0.4 Torr, 520° C., 60 seconds.
Only the key process steps are described above. A complete process sequence also includes steps to stabilize the gas flows and wafer temperature prior to deposition, and chamber pump/purge steps that are performed following the deposition but prior to removing the substrates from the reactor. Also, the gas sequencing concept can be applied over a wide range of process conditions and the specific choice of process conditions for α-Si are dependent primarily on the reactor configuration. Further, although the method has been described for SiH4 and Si2H6 since these are the most commonly used silicon containing source gases for poly-Si, other silicon containing source gases may be used in the invention.
The result of the process according to the invention is that the seed layer is thin yet continuous as evidenced by the low surface roughness of the film. With a conventional process, the inventors observed the roughness (Ra) of 100 Å α-Si to be approximately 1.3 nm. The high surface roughness and the high Rmax value of 25 nm suggest that the film is semi-continuous. Surface roughness drops to less than 0.3 nm and Rmax drops to less than 4 nm with the process according to the invention indicating that the film is continuous.
Characterization of the surface roughness and crystalline structure of the poly-SiGe deposited on the α-Si seed layer can be used to assess the effect of an improved α-Si seed layer on the poly-SiGe film.
2.0 slm SiH4, 0.12 slm GeH4, 0.0 slm diluent N2, 0.4 Torr, 520° C., 600 seconds. The GeH4:SiH4 flow ratio can be modulated to adjust the Ge content in the film from pure α-Si to about 50 atomic % Ge (see
Auger analysis shows that the poly-SiGe deposition process results in uniform Ge incorporation through the film (
The poly-SiGe film is also very conformal (see
The influence of the α-Si seed layer on the roughness of the poly-SiGe is dramatic. In the absence of a seed layer, the surface roughness of a 800 Å poly-SiGe is about 39 Å (see
For poly-SiGe/poly-Si stack, the morphology of poly-Si deposited on poly-SiGe is poor. The grain size distribution is broader compared to poly-Si deposited directly on the gate dielectric. The mean grain size is also larger since poly-Si growth on poly-SiGe is quasi-heteroepitaxial, i.e. the lattice spacing of poly-Si crystallites tends to follow the larger lattice spacing of the underlying poly-SiGe.
The method according to the invention for forming a poly-SiGe/poly-Si stack includes the step of inserting of a thin α-Si layer in between the poly-SiGe and poly-Si layers. The α-Si layer retains its amorphous microstructure at the poly-Si deposition temperature. The growth of poly-Si on poly-SiGe with an intervening layer of α-Si is not hetero-epitaxial. The poly-Si grain structure is more akin to that obtained when the film is deposited directly on an amorphous surface such as thermal SiO2.
The smaller poly-Si grain size that is obtained when the poly-Si is deposited on poly-SiGe with an interposed layer of α-Si is confirmed by the reduced surface roughness of the stack. For example, when 1000 Å poly-Si is deposited directly on 500 Å poly-SiGe (without an α-Si seed layer), the surface roughness of the stack is about 58 Å (see
The α-Si deposition conditions used for this interfacial layer are described below.
2.0 slm SiH4, 0.0 slm diluent N2, 0.4 Torr, 520° C., 420 seconds to deposit 100 Å of α-Si.
In the example, the deposition temperature is chosen to be the same as that for the poly-SiGe so that the α-Si seed layer, the poly-SiGe and α-Si interfacial layer are all deposited at the same temperature before the temperature is raised for the poly-Si deposition.
The following process conditions were used for poly-Si deposition.
2.0 slm SiH4, 0.0 slm diluent N2, 0.4 Torr, 630° C., 420 seconds to deposit 1000 Å of poly-Si.
Materials other than α-Si may be used for the interfacial layer, but α-Si is best suited since it gets transformed to poly-Si during subsequent thermal annealing performed to activate and to diffuse implanted dopants. Following the anneal, a poly-SiGe/poly-Si stack results. The α-Si seed layer gets transformed to poly-SiGe during the anneal since the Ge from the poly-SiGe diffuses into the α-Si seed layer. Another advantage is that the α-Si can be deposited at the same temperature using the same reactants as poly-SiGe.
Another application for SiGe is the deposition of hemispherical grained silicon (HSG). Hemispherical grained silicon is commonly used in the bottom electrode stack for DRAM capacitors. Compared to smooth α-Si or poly-Si bottom electrode stacks, stacks incorporating HSG Si have a surface area that is 1.5-2.5× higher. The higher surface area increases the capacitance of the DRAM capacitor.
In the simplest technique, α-Si is deposited with SiH4 or SiH4 diluted in He, H2, N2, or Ar at pressures of 0.5-1.5 Torr and temperatures from 560° C.-600° C. At an intermediate temperature between 560° C. and 600° C., the morphology of the α-Si changes from smooth films to rough films with hemispherical grains. The temperature window for this mode of deposition is 10° C., which is generally too narrow to control in a production environment.
The deposition approach discussed above could be modified to make the process more manufacturable. The key concept is to dope the α-Si with Ge and adjust the deposition temperature to achieve hemispherical grain growth. Ge doping helps amorphous phase transition to the polycrystalline phase; thereby reducing the demands on temperature control. This transition temperature can drop 100° C. from 580° C. to 480° C. for high Ge content. Addition of Ge also increases the grain size that enlarges the size of the hemispherical grain. A common source for Ge is GeH4. GeH4 is an etchant for SiO2 native oxides thereby suppressing their growth. Native oxides tend to inhibit the formation of HSG-Si. The HSG-SiGe can be capped with an undoped layer of α-Si if necessary for process integration.
All of these factors contribute to larger hemispherical grains with increased surface area. Ge doping can be advantageously used in the other two HSG-Si deposition techniques as well. Some of the potential improvements are described as following. One of the techniques is to deposit a Ge doped α-Si layer and then vacuum anneal or anneal in an ambient of H2 or GeH4/H2 to form HSG-SiGe. If GeH4 is used it should be sufficiently dilute to prevent Ge deposition, but high enough to etch native oxides that may grow during anneal. Native oxides tend to reduce surface diffusion and tend to inhibit the formation of HSG film. The other technique is to seed the α-Si base layer with SiGe nuclei instead of pure Si nuclei and then vacuum anneal or anneal in an ambient of H2 or GeH4/H2 to form HSG-SiGe. If GeH4 is used it should be sufficiently dilute to prevent Ge deposition, but high enough to etch native oxides that may grow during anneal. Native oxides tend to reduce surface diffusion and tend to inhibit the formation of HSG film.
The increase in surface roughness with the addition of Ge is seen in
Yet another application for SiGe is the deposition of in-situ doped poly-Si. In-situ doped Si films are commonly used in memory devices as gate electrodes, word lines, bit lines, capacitor electrodes and capacitor plates. Generally, these films are deposited as α-Si that are in-situ doped with phosphorus, boron or arsenic. A high temperature post-deposition furnace anneal or rapid thermal anneal is performed to activate the dopant and transform the film into large grained low resistivity poly-Si.
In certain applications such as floating gates for non-volatile memories where a light as-deposited doping concentration is required, a fine-grained as-deposited poly-Si microstructure with randomly oriented grains is desired. Earlier it was shown that Ge doping lowers the α-Si to poly-Si transition temperature. In other words, Ge doping favors the α-SiGe to poly-SiGe transition. Thus one novel way to obtain an as-deposited poly-Si microstructure for in-situ doped films is to add GeH4 or other Ge containing source gases to the silicon containing source gases used for poly-Si deposition. For some dopants, especially boron, Ge doping also enhances dopant activation. In this manner, in-situ doped poly-SiGe films are obtained at process temperatures that would normally yield in-situ doped α-Si. These poly-SiGe films may be capped with α-Si or poly-Si. As described earlier, a seed layer of undoped or in-situ doped α-Si may be necessary to initiate poly-SiGe deposition.
Another application for in-situ doped films is MEMS (micromechanical systems) and TFT (thin film transistor) applications. Thermal budget is a serious constraint for MEMS processing. Typically processing temperatures must remain below 600° C. to avoid damage to the micro-machined components. For applications such as these, a low temperature (<600° C.) in-situ doped poly-Si film with activated dopant is desirable. Once again, Ge doping can be used to achieve such a film. First in-situ doped α-SiGe is deposited below the amorphous to polycrystalline transition for SiGe (typically 475-550° C.). The film is then annealed in-situ at temperatures below 600° C. to crystallize the film and activate the dopant. During anneal, the film transforms from the amorphous phase to the polycrystalline phase through a process known as solid phase recrystallization. Ge doping lowers the temperature for solid phase recrystallization of α-Si from above 600° C. to below 550° C.
In this manner, the poly-SiGe deposition techniques introduced for the primary application of advanced gate electrodes, can be advantageously applied to HSG-Si formation, in-situ doped poly-Si deposition and low temperature in-situ doped poly-Si.
Accordingly, while the present invention has been disclosed in connection with various embodiments thereof, it should be understood that other embodiments might fall within the spirit and scope of the invention, as defined by the following claims.