|Publication number||US20060063322 A1|
|Application number||US 10/946,494|
|Publication date||Mar 23, 2006|
|Filing date||Sep 21, 2004|
|Priority date||Sep 21, 2004|
|Also published as||US7179701|
|Publication number||10946494, 946494, US 2006/0063322 A1, US 2006/063322 A1, US 20060063322 A1, US 20060063322A1, US 2006063322 A1, US 2006063322A1, US-A1-20060063322, US-A1-2006063322, US2006/0063322A1, US2006/063322A1, US20060063322 A1, US20060063322A1, US2006063322 A1, US2006063322A1|
|Inventors||Ju-Wang Hsu, Jyu-Horng Shieh, Ju-Chien Chiang|
|Original Assignee||Ju-Wang Hsu, Jyu-Horng Shieh, Ju-Chien Chiang|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (9), Classifications (20), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates, most generally to a semiconductor device and methods for forming the same. More particularly, the invention relates to a high dielectric constant transistor gate and a method for forming such a structure.
Shrinking the conventional MOSFET (metal oxide semiconductor field effect transistor) beyond the 50 nanometer technology node requires innovations to circumvent barriers due to the fundamental physics that constrain conventional MOSFETs. Continued device shrinkage requires a reduction of gate dielectric thickness. This requirement arises from two different considerations: controlling the short-channel effect, and achieving a high current drive by keeping the amount of charge induced in the channel as large as possible as the power-supply voltage decreases. It is the reduction of the equivalent electrical thickness of the gate dielectric that is important in achieving each of the aforementioned considerations.
One approach for reducing the equivalent electrical thickness of the gate dielectric is to simply reduce the physical thickness of the gate dielectric material. A shortcoming associated with this approach is that the direct tunneling current through the gate dielectric grows exponentially with decreasing physical thickness of the gate dielectric. It is considered that tunneling currents arising from silicon dioxide (SiO2) gate dielectrics thinner than 0.8 nanometers cannot be tolerated, even for high-performance systems. A more favorable approach for reducing the equivalent electrical thickness of the gate dielectric is to use a gate dielectric material that has a high dielectric constant, i.e., a dielectric constant that is higher than about 3.9, the dielectric constant of SiO2. A gate dielectric with a dielectric constant (k) substantially higher than that of SiO2 (kox) will achieve a smaller equivalent electrical thickness (teq) than the SiO2, even with a physical thickness (tphys) larger than that of the SiO2 (tox):
t eq=(k ox /k)t phys.
Replacing the conventional SiO2 gate material with a high-dielectric constant (high-k) dielectric gate material, however, presents other challenges. One challenge associated with the use of high-k gate dielectric material is the inability to sufficiently remove such materials from the non-gate regions where they are not needed. Due to the absence of suitable etch chemistries to remove the high-k gate materials, an aggressive etch and an aggressive and extended over-etch must be used when etching to remove the high-k gate dielectric material, to ensure its complete removal. Such an approach can and often does result in recesses being produced throughout the semiconductor device, including in areas immediately adjacent to the gate region, due to the aggressive etch process.
It would therefore be desirable to produce a semiconductor device and provide a method for forming the device with a high-k gate dielectric material and without the above shortcomings.
To address the above needs and in view of its purposes, an aspect of the invention provides a method for forming a semiconductor device. The method comprises forming a high-k gate dielectric material over a substrate including over a gate region, using a planarization step such as chemical mechanical polishing to remove the high-k gate dielectric material from regions other than the gate region, and forming a conductive material over the high-k gate dielectric material in the gate region.
In another aspect, provided is a semiconductor device comprising a transistor gate. The semiconductor device includes a conductive gate material formed over a channel region of a substrate. A high-k dielectric layer is interposed between the conductive gate material and the substrate and the high-k dielectric layer extends along sidewalls of the conductive gate material.
The present invention is best understood from the following detailed description when read in conjunction of the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not necessarily to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Like numerals denote like features throughout the specification and drawing. Each of the following figures is a cross-sectional view.
An etching process is used to form opening 7 within organic material 1 and a subsequent ashing process may be used to remove photoresist 5 and clean up any residual organic material from gate area 9 to produce the structure shown in
Now turning to
Second conductive layer 49 may be polysilicon, one of the aforementioned metals, or a metal silicide. Second conductive material 49 is formed over first conductive material 41 and fills opening 45. A planarization process such as a chemical mechanical polishing process is then used to remove portions of second conductive material 49, first conductive layer 47, high-k gate dielectric 15 and ARC 43 from over top surface 21 of organic material 1 to form the planarized structure shown in
The various features illustrated in
The preceding merely illustrates the principles of the invention. It will thus be appreciated that those skilled in the art will be able to devise various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and conditional language recited herein are principally intended expressly to be only for pedagogical purposes and to aid the reader in understanding the principles of the invention and the concepts contributed by the inventors to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass both structural and functional equivalents thereof. Additionally, it is intended that such equivalents include both currently known equivalents and equivalents developed in the future, i.e., any elements developed that perform the same function, regardless of structure.
This description of the exemplary embodiments is intended to be read in connection with the figures of the accompanying drawing, which are to be considered part of the entire written description. In the description, relative terms such as “lower,” “upper,” “horizontal,” “vertical,”, “above,” “below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should be construed to refer to the orientation as then described or as shown in the drawing under discussion. These relative terms are for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation.
Although the invention has been described in terms of exemplary embodiments, it is not limited thereto. Rather, the appended claims should be construed broadly, to include other variants and embodiments of the invention, which may be made by those skilled in the art without departing from the scope and range of equivalents of the invention.
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|U.S. Classification||438/216, 257/E21.202, 438/756, 438/757, 257/E29.158, 257/E21.434, 257/E29.161, 257/E21.204|
|International Classification||H01L21/302, H01L21/8238|
|Cooperative Classification||H01L29/66583, H01L21/28088, H01L21/28079, H01L29/495, H01L29/517, H01L29/518, H01L29/4975, H01L29/66553|
|European Classification||H01L29/66M6T6F9, H01L29/66M6T6F11B2|
|Jan 7, 2005||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TAIW
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HSU, JU-WANG;SHIEH, JYU-HORNG;CHIANG, JU-CHIEN;REEL/FRAME:015564/0529
Effective date: 20040924
|Jul 31, 2007||CC||Certificate of correction|
|Jul 21, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Jul 23, 2014||FPAY||Fee payment|
Year of fee payment: 8