|Publication number||US20060108667 A1|
|Application number||US 11/285,525|
|Publication date||May 25, 2006|
|Filing date||Nov 21, 2005|
|Priority date||Nov 22, 2004|
|Also published as||CN1819297A, CN1819297B, CN1917248A, CN102088059A, US7608503, US20060110878|
|Publication number||11285525, 285525, US 2006/0108667 A1, US 2006/108667 A1, US 20060108667 A1, US 20060108667A1, US 2006108667 A1, US 2006108667A1, US-A1-20060108667, US-A1-2006108667, US2006/0108667A1, US2006/108667A1, US20060108667 A1, US20060108667A1, US2006108667 A1, US2006108667A1|
|Original Assignee||Macronix International Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (71), Classifications (26), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The benefit of U.S. Provisional Application No. 60/630,123; filed 22 Nov. 2004, entitled SIDE WALL ACTIVE PHASE CHANGE RAM AND MANUFACTURING METHOD, is hereby claimed.
International Business Machines Corporation, a New York corporation; Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement.
1. Field of the Invention
The present invention relates to methods for manufacturing integrated circuits and other devices, and more particularly to methods for making very small pin-shaped structures.
2. Description of Related Art
A need arises in integrated circuit manufacturing processes for making very small structures. For example, small elements comprising chalcogenide materials or other phase change materials can be caused to change phase by application of electrical current. This property has generated interest in using phase change materials to form nonvolatile memory circuits.
One direction of development has been toward using small quantities of programmable resistive material, particularly in small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.
My U.S. Patent application Publication No. US-2004-0026686-A1 describes a phase change memory cell in which the phase change element comprises a side wall on an electrode/dielectric/electrode stack. Data is stored by causing transitions in the phase change material between amorphous and crystalline states using current. Current heats the material and causes transitions between the states. The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material.
Other applications for small structures arise in integrated circuit manufacturing, and it is desirable to provide new manufacturing techniques and structures satisfying this need.
The present invention includes methods to form a narrow side wall spacer or pin. A method of forming a memory cell based on such a narrow side wall spacer or pin is described which comprises forming a stack comprising a first electrode, an insulating layer over the first electrode, and a second electrode over the insulating layer, with a side wall on at least the insulating layer of the stack. A side wall spacer comprising a programmable resistive material in electrical communication with the first and second electrodes is formed. The side wall spacer has a length extending from the first electrode to the second electrode along the side wall, a width generally orthogonal to the length, and a thickness determined by the thickness of a layer of programmable resistive material used to form the side wall spacer. The side wall spacer is formed by depositing a layer of programmable resistive material over the side wall of the stack, anisotropically etching the layer of programmable resistive material to remove it in areas away from the side wall, and selectively etching the programmable resistive material according to a pattern to define the width of the side wall spacer. In embodiments described herein, the width is less than 50 nanometers, and more preferably about 40 nanometers or less.
In order to selectively etch the programmable resistive material according to a pattern to define a side wall spacer with such a narrow width, one technique includes forming an etch mask having a lithographic pattern to define a lithographic width, and then trimming the etch mask to provide a trimmed mask to define the pattern used for defining the width of the side wall spacer. In one example, the etch mask comprises a photoresist, which is etched anisotropically to form the trimmed mask using an oxygen based plasma etch. In another example, the etch mask comprises a hard mask defined using a lithographic process, which is etched to reduce its width to form the trimmed mask.
The three dimensions that define the size of the active region in the phase change pin for the cell described herein are preferably less than 50 nanometers, and can all be less than the minimum feature size of the lithographic process applied to make the cell. The dimensions are defined in technology described herein, by the thin film thickness of phase change material, the inter-electrode dielectric thin film thickness, and the trimmed mask. As a result, the cell size (the volume of the phase change material) is very small (smaller than F3, where F is the minimum lithographic feature size for the process used to manufacture the memory cell). The resulting cell of phase change material comprises a narrow pin on the side wall of an electrode stack. The contact area between at least one of the top and bottom electrodes and the phase change material pin is also defined sub-lithographically by electrode layer thicknesses for the heights, and the photo-resist pattern trimming process for the width of the contacts. The small cell and small contact region allow implementation of a memory with very small reset current and low power consumption.
A memory device is also described that includes a stack including a first electrode, an inter-electrode insulating member over the first electrode, and a second electrode over the inter-electrode insulating member. The stack has a side wall over at least the insulating member. A spacer comprising programmable resistive material on the side wall is in electrical communication with the first and second electrodes. The spacer has a length extending from the first electrode to the second electrode along the side wall on the insulating layer, which is generally orthogonal to the length and a thickness. The width and thickness of the spacer are less than 40 nanometers in embodiments of the technology described herein. The programmable resistive material comprises a phase change material, which is reversibly programmable.
The method described herein for formation of the phase change material pin can be used to make a very small pin for other nano-technology uses on an integrated circuit or other device, using materials other than phase change materials, like metals, dielectrics, organic materials, semiconductors, and so on. The small dimension side wall pin can be formed on structures other than that used for the phase change memory cell described herein, such as structures comprising other types of stacks of thin films, such as stacks of thin film dielectrics, with and without an electrode layer for contact to the pin.
Other aspects and advantages of the technology described herein can be understood with reference to the figures and the detailed description which follow.
The following detailed description is made with reference to the figures. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows.
As illustrated, the active region of the pin 5 has a length L defined by a thin film thickness of the inter-electrode dielectric 8, which in embodiments of the invention can range between about 20 and 50 nanometers. Likewise, the active region of the pin 5 has a thickness T which is defined by the thin film thickness of the material used to form the side wall pin, which in embodiments of the invention can range between about 10 and 50 nanometers. Accordingly, all three dimensions of the pin 5 are less than 50 nanometers in embodiments of the present invention, and more preferably about 40 or less nanometers.
In embodiments of the invention, the programmable resistive material comprises a phase change material, such as Ge2Sb2Te5 or other materials described below. The volume of material within the pin 5, in which the phase change is induced in the structure illustrated in
Embodiments of the memory cell include phase change based memory materials, including chalcogenide based materials and other materials, for the side wall pin 5. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as TeaGebSb100−(a+b), where a and b represent atomic percentages that total 100% of the atoms of the constituent elements. One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb (Ovshinsky '112 patent, cols 10-11). Particular alloys evaluated by another researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7 (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v.3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.
Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These phase change materials are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.
Phase change materials can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined empirically, without undue experimentation, specifically adapted to a particular phase change alloy.
In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory cell as described herein is Ge2Sb2Te5.
Useful characteristics of the programmable resistive material, like a phase change material include the material having a resistance which is programmable, and preferably in a reversible manner, such as by having at least two solid phases that can be reversibly induced by electrical current. These at least two phases include an amorphous phase and a crystalline phase. However, in operation, the programmable resistive material may not be fully converted to either an amorphous or crystalline phase. Intermediate phases or mixtures of phases may have a detectable difference in material characteristics. The two solid phases should generally be bistable and have different electrical properties. The programmable resistive material may be a chalcogenide material. A chalcogenide material may include GST. Alternatively, it may be one of the other phase change materials identified above.
A controller implemented in this example using bias arrangement state machine 69 controls the application of bias arrangement supply voltages 68, such as read, program, erase, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.
In representative embodiments, the patterned metal layer (contacts 129-132) comprises copper metallization. Other types of metallization, including aluminum and aluminum alloys, could be utilized as well. The top and bottom electrodes (e.g. 121, 123) comprise TiN or TaN with a thickness of 10 to 30 nm. Alternatively, the electrodes may be TiAlN or TaAlN, or may comprise one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, Ru and O. The inter-electrode insulating layer may be silicon oxide, silicon oxynitride, silicon nitride, Al2O3, other low K dielectrics, or an ONO or SONO multi-layer structure. Alternatively, the inter-electrode insulating layer may comprise one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C. The inter-electrode thickness may be 10 to 200 nm, and more preferably 50 nanometers or less. The second electrode may be TiN or TaN.
After formation of the plugs 120, 141 and source line 119 for the structure 99, a multilayer, thin film structure is formed including bottom electrode thin film 150, top electrode thin film 152, inter-electrode dielectric 151, and protective top dielectric 153. The bottom electrode film 150 has a thickness less than 50 nanometers, and preferably in the range of 10 to 30 nanometers. The top electrode film 152 has a thickness less than 50 nanometers, and preferably in the range of 10 to 30 nanometers, and can be different than that of the bottom electrode film. For example, the thickness of the top electrode film 152 can be slightly greater than that of the bottom electrode, in order to improve process margin for reliable contacts using tungsten plug technology and the like. The top dielectric 153 provides process margin for use of chemical mechanical polishing for planarization, variations in side wall spacer etching, and the like. Alternative embodiments without the top dielectric 153 might be implemented.
As illustrated in
In an alternative embodiment, a hard mask layer (not shown), such as a low temperature deposited layer of SiN or SiO2, can be put between the photoresist pattern and the surface of the stacks 60, 65, to prevent etching damage of the cell, if the photoresist is not thick enough after the trimming process, or selective etching of the GST and the hard mask is improved by the hard mask.
The phase change material pin described above, and the process for making it, are representative of technologies using nano-scale structures as described herein.
While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7646631||Dec 7, 2007||Jan 12, 2010||Macronix International Co., Ltd.||Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods|
|US7663135||Sep 28, 2007||Feb 16, 2010||Macronix International Co., Ltd.||Memory cell having a side electrode contact|
|US7682868||Dec 6, 2006||Mar 23, 2010||Macronix International Co., Ltd.||Method for making a keyhole opening during the manufacture of a memory cell|
|US7687307||Dec 16, 2008||Mar 30, 2010||Macronix International Co., Ltd.||Vacuum jacketed electrode for phase change memory element|
|US7688619||Dec 18, 2006||Mar 30, 2010||Macronix International Co., Ltd.||Phase change memory cell and manufacturing method|
|US7696503||Aug 13, 2007||Apr 13, 2010||Macronix International Co., Ltd.||Multi-level memory cell having phase change element and asymmetrical thermal boundary|
|US7696506||Jun 27, 2006||Apr 13, 2010||Macronix International Co., Ltd.||Memory cell with memory material insulation and manufacturing method|
|US7701750||May 8, 2008||Apr 20, 2010||Macronix International Co., Ltd.||Phase change device having two or more substantial amorphous regions in high resistance state|
|US7701759||Jul 12, 2007||Apr 20, 2010||Macronix International Co., Ltd.||Memory cell device and programming methods|
|US7718989||Dec 28, 2006||May 18, 2010||Macronix International Co., Ltd.||Resistor random access memory cell device|
|US7719913||Sep 12, 2008||May 18, 2010||Macronix International Co., Ltd.||Sensing circuit for PCRAM applications|
|US7723180||May 27, 2008||May 25, 2010||Sandisk 3D Llc||Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same|
|US7729161||Aug 2, 2007||Jun 1, 2010||Macronix International Co., Ltd.||Phase change memory with dual word lines and source lines and method of operating same|
|US7741636||Jul 14, 2006||Jun 22, 2010||Macronix International Co., Ltd.||Programmable resistive RAM and manufacturing method|
|US7745811 *||Nov 17, 2006||Jun 29, 2010||Industrial Technology Research Institute||Phase change memory devices and methods for fabricating the same|
|US7749854||Dec 16, 2008||Jul 6, 2010||Macronix International Co., Ltd.||Method for making a self-converged memory material element for memory cell|
|US7755076||Apr 17, 2007||Jul 13, 2010||Macronix International Co., Ltd.||4F2 self align side wall active phase change memory|
|US7772581||Sep 11, 2006||Aug 10, 2010||Macronix International Co., Ltd.||Memory device having wide area phase change element and small electrode contact area|
|US7777215||Jul 18, 2008||Aug 17, 2010||Macronix International Co., Ltd.||Resistive memory structure with buffer layer|
|US7785920||Jul 12, 2006||Aug 31, 2010||Macronix International Co., Ltd.||Method for making a pillar-type phase change memory element|
|US7786460||Jan 9, 2007||Aug 31, 2010||Macronix International Co., Ltd.||Phase change memory device and manufacturing method|
|US7786461||Apr 3, 2007||Aug 31, 2010||Macronix International Co., Ltd.||Memory structure with reduced-size memory element between memory material portions|
|US7791057||Apr 22, 2008||Sep 7, 2010||Macronix International Co., Ltd.||Memory cell having a buried phase change region and method for fabricating the same|
|US7804083||Nov 14, 2007||Sep 28, 2010||Macronix International Co., Ltd.||Phase change memory cell including a thermal protect bottom electrode and manufacturing methods|
|US7812335||Jun 30, 2008||Oct 12, 2010||Sandisk 3D Llc||Sidewall structured switchable resistor cell|
|US7816661||Nov 21, 2006||Oct 19, 2010||Macronix International Co., Ltd.||Air cell thermal isolation for a memory array formed of a programmable resistive material|
|US7825398||Apr 7, 2008||Nov 2, 2010||Macronix International Co., Ltd.||Memory cell having improved mechanical stability|
|US7829876||Apr 21, 2006||Nov 9, 2010||Macronix International Co., Ltd.||Vacuum cell thermal isolation for a phase change memory device|
|US7830698||May 27, 2008||Nov 9, 2010||Sandisk 3D Llc||Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same|
|US7842536||Aug 27, 2008||Nov 30, 2010||Macronix International Co., Ltd.||Vacuum jacket for phase change memory element|
|US7859887||May 27, 2008||Dec 28, 2010||Sandisk 3D Llc||Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same|
|US7863655||Oct 24, 2006||Jan 4, 2011||Macronix International Co., Ltd.||Phase change memory cells with dual access devices|
|US7867815||Jul 16, 2008||Jan 11, 2011||Macronix International Co., Ltd.||Spacer electrode small pin phase change RAM and manufacturing method|
|US7869270||Dec 29, 2008||Jan 11, 2011||Macronix International Co., Ltd.||Set algorithm for phase change memory cell|
|US7875493||Aug 9, 2010||Jan 25, 2011||Macronix International Co., Ltd.||Memory structure with reduced-size memory element between memory material portions|
|US7879643||Jan 18, 2008||Feb 1, 2011||Macronix International Co., Ltd.||Memory cell with memory element contacting an inverted T-shaped bottom electrode|
|US7879645||Jan 28, 2008||Feb 1, 2011||Macronix International Co., Ltd.||Fill-in etching free pore device|
|US7884342||Jul 31, 2007||Feb 8, 2011||Macronix International Co., Ltd.||Phase change memory bridge cell|
|US7884343||Jan 18, 2008||Feb 8, 2011||Macronix International Co., Ltd.||Phase change memory cell with filled sidewall memory element and method for fabricating the same|
|US7893418||Nov 24, 2009||Feb 22, 2011||Macronix International Co., Ltd.||Phase change memory cell having interface structures with essentially equal thermal impedances and manufacturing methods|
|US7894254||Jul 15, 2009||Feb 22, 2011||Macronix International Co., Ltd.||Refresh circuitry for phase change memory|
|US7897954||Oct 10, 2008||Mar 1, 2011||Macronix International Co., Ltd.||Dielectric-sandwiched pillar memory device|
|US7902538||Nov 6, 2008||Mar 8, 2011||Macronix International Co., Ltd.||Phase change memory cell with first and second transition temperature portions|
|US7903447||Dec 13, 2006||Mar 8, 2011||Macronix International Co., Ltd.||Method, apparatus and computer program product for read before programming process on programmable resistive memory cell|
|US7903457||Aug 19, 2008||Mar 8, 2011||Macronix International Co., Ltd.||Multiple phase change materials in an integrated circuit for system on a chip application|
|US7910906||Feb 9, 2009||Mar 22, 2011||Macronix International Co., Ltd.||Memory cell device with circumferentially-extending memory element|
|US7919766||Oct 22, 2007||Apr 5, 2011||Macronix International Co., Ltd.||Method for making self aligning pillar memory cell device|
|US7919768||Jul 11, 2008||Apr 5, 2011||Industrial Technology Research Institute||Phase-change memory element|
|US7920415||Mar 2, 2010||Apr 5, 2011||Macronix International Co., Ltd.||Memory cell device and programming methods|
|US7923285||Jan 9, 2009||Apr 12, 2011||Macronix International, Co. Ltd.||Method for forming self-aligned thermal isolation cell for a variable resistance memory array|
|US7928421||Apr 21, 2006||Apr 19, 2011||Macronix International Co., Ltd.||Phase change memory cell with vacuum spacer|
|US7929340||Feb 10, 2010||Apr 19, 2011||Macronix International Co., Ltd.||Phase change memory cell and manufacturing method|
|US7932101||Mar 18, 2008||Apr 26, 2011||Macronix International Co., Ltd.||Thermally contained/insulated phase change memory device and method|
|US7932506||Jul 22, 2008||Apr 26, 2011||Macronix International Co., Ltd.||Fully self-aligned pore-type memory cell having diode access device|
|US7933139||May 15, 2009||Apr 26, 2011||Macronix International Co., Ltd.||One-transistor, one-resistor, one-capacitor phase change memory|
|US7943920||Jul 14, 2010||May 17, 2011||Macronix International Co., Ltd.||Resistive memory structure with buffer layer|
|US7956344||Feb 27, 2007||Jun 7, 2011||Macronix International Co., Ltd.||Memory cell with memory element contacting ring-shaped upper end of bottom electrode|
|US7956358||Feb 7, 2006||Jun 7, 2011||Macronix International Co., Ltd.||I-shaped phase change memory cell with thermal isolation|
|US8048474||Aug 7, 2008||Nov 1, 2011||Sandisk 3D Llc||Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing|
|US8293600||Dec 6, 2011||Oct 23, 2012||Macronix International Co., Ltd.||Thermally stabilized electrode structure|
|US8426838||Nov 27, 2008||Apr 23, 2013||Higgs Opl. Capital Llc||Phase-change memory|
|US8497182||Apr 19, 2011||Jul 30, 2013||Macronix International Co., Ltd.||Sidewall thin film electrode with self-aligned top electrode and programmable resistance memory|
|US8513637 *||Jul 13, 2007||Aug 20, 2013||Macronix International Co., Ltd.||4F2 self align fin bottom electrodes FET drive phase change memory|
|US8558213||Mar 30, 2009||Oct 15, 2013||Nxp B.V.||Vertical phase change memory cell|
|US8604457||Nov 12, 2008||Dec 10, 2013||Higgs Opl. Capital Llc||Phase-change memory element|
|US8716099||Mar 12, 2013||May 6, 2014||Higgs Opl. Capital Llc||Phase-change memory|
|US8884260||Oct 24, 2013||Nov 11, 2014||Higgs Opl. Capital Llc||Phase change memory element|
|US8916414||Sep 26, 2013||Dec 23, 2014||Macronix International Co., Ltd.||Method for making memory cell by melting phase change material in confined space|
|US9087985||Feb 26, 2014||Jul 21, 2015||Higgs Opl.Capital Llc||Phase-change memory|
|WO2009122349A2 *||Mar 30, 2009||Oct 8, 2009||Nxp B.V.||Vertical phase change memory cell|
|WO2009126492A1 *||Apr 1, 2009||Oct 15, 2009||Sandisk 3D Llc||Sidewall structured switchable resistor cell|
|U.S. Classification||257/624, 438/735, 257/E21.038, 257/E21.039, 257/E27.103, 438/692, 257/E45.002, 257/E27.004, 257/E21.662, 438/696|
|International Classification||H01L29/06, H01L21/461|
|Cooperative Classification||H01L45/1691, H01L45/144, H01L27/115, H01L27/112, H01L27/2436, H01L45/124, H01L45/06, H01L21/0338, H01L21/0337, H01L27/2463|
|European Classification||H01L45/04, H01L27/112, H01L27/115, H01L27/24|
|Nov 21, 2005||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LUNG, HSIANG LAN;REEL/FRAME:017249/0970
Effective date: 20051109