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Publication numberUS20060119382 A1
Publication typeApplication
Application numberUS 11/006,420
Publication dateJun 8, 2006
Filing dateDec 7, 2004
Priority dateDec 7, 2004
Also published asCN1797951A, EP1670140A2, EP1670140A3, US7986160, US20060202713, US20060202714
Publication number006420, 11006420, US 2006/0119382 A1, US 2006/119382 A1, US 20060119382 A1, US 20060119382A1, US 2006119382 A1, US 2006119382A1, US-A1-20060119382, US-A1-2006119382, US2006/0119382A1, US2006/119382A1, US20060119382 A1, US20060119382A1, US2006119382 A1, US2006119382A1
InventorsSergey Shumarayev, Rakesh Patel
Original AssigneeShumarayev Sergey Y, Rakesh Patel
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Apparatus and methods for adjusting performance characteristics of programmable logic devices
US 20060119382 A1
Abstract
A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows trading off various performance characteristics, such as speed and power consumption.
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Claims(49)
1. A programmable logic device (PLD), comprising a first circuit configured to control a supply voltage of a second circuit, the first circuit further configured to filter noise within the programmable logic device (PLD).
2. The programmable logic device (PLD) according to claim 1, wherein the first circuit comprises a variable impedance device, the variable impedance device configured to provide the supply voltage of the second circuit.
3. The programmable logic device (PLD) according to claim 1, wherein the transistor comprises a native transistor of the programmable logic device.
4. The programmable logic device (PLD) according to claim 2, wherein the variable impedance device is further configured to provide the supply voltage of the second circuit in response to a programmable logic device (PLD) configuration datum.
5. The programmable logic device (PLD) according to claim 2, wherein the variable impedance device comprises a transistor.
6. The programmable logic device (PLD) according to claim 3, wherein the first circuit further comprises a control circuit coupled to a gate terminal of the transistor.
7. The programmable logic device (PLD) according to claim 6, wherein the transistor adjusts the supply voltage of the second circuit in response to an output signal of the control circuit.
8. The programmable logic device (PLD) according to claim 4, wherein the first circuit further comprises a first capacitor coupled to a gate terminal of the transistor.
9. The programmable logic device (PLD) according to claim 4, wherein the first circuit further comprises a second capacitor coupled to a source terminal of the transistor.
10. The programmable logic device (PLD) according to claim 7, wherein the output signal of the control circuit is derived from information received from an information source external to the programmable logic device (PLD).
11. The programmable logic device (PLD) according to claim 6, wherein the output signal of the control circuit depends on a power consumption of a circuit within the programmable logic device (PLD).
12. The programmable logic device (PLD) according to claim 1, wherein the second circuit comprises a programmable logic circuit.
13. The programmable logic device (PLD) according to claim 12, wherein the programmable logic circuit comprises one of a plurality of programmable logic circuits arranged as a two-dimensional array.
14. The programmable logic device (PLD) according to claim 12, wherein the programmable logic circuit comprises a logic element.
15. The programmable logic device (PLD) according to claim 14, wherein the programmable logic circuit comprises local interconnect circuitry.
16. The programmable logic device (PLD) according to claim 1, wherein the second circuit comprises programmable interconnect circuitry.
17. The programmable logic device (PLD) according to claim 1, wherein the second circuit comprises configuration memory configured to store configuration data of the programmable logic device (PLD).
18. A programmable logic device (PLD), comprising:
a first circuit, the first circuit residing in a first deep n-well; and
a first variable impedance device coupled to the first circuit, the first variable impedance device configured to adjust a supply voltage of the first circuit.
19. The programmable logic device (PLD) according to claim 18, further comprising a first capacitor coupled to the first variable impedance device.
20. The programmable logic device (PLD) according to claim 18, comprising:
a second circuit, the second circuit residing in a second deep n-well; and
a second variable impedance device coupled to the second circuit, the second variable impedance device configured to adjust a supply voltage of the second circuit.
21. The programmable logic device (PLD) according to claim 20, further comprising a second capacitor coupled to the second variable impedance device.
22. The programmable logic device (PLD) according to claim 20, wherein the first circuit is relatively sensitive to noise.
23. The programmable logic device (PLD) according to claim 20, wherein the first circuit comprises analog circuitry.
24. The programmable logic device (PLD) according to claim 20, wherein the first circuit comprises mixed-mode circuitry.
25. The programmable logic device (PLD) according to claim 22, wherein the second circuit generates relatively high levels of noise.
26. The programmable logic device (PLD) according to claim 20, wherein the first variable impedance device derives the supply voltage of the first circuit from a first voltage supplied to the programmable logic device (PLD).
27. The programmable logic device (PLD) according to claim 20, wherein the first variable impedance device derives the supply voltage of the first circuit from a first voltage, wherein the first voltage is derived within the programmable logic device (PLD) from a second voltage supplied to the programmable logic device (PLD).
28. A method of configuring a programmable logic device (PLD) to implement an electronic circuit, the method comprising:
mapping the electronic circuit to functional resources within the programmable logic device (PLD) to generate a circuit to be implemented by the programmable logic device (PLD);
identifying at least one critical circuit path in the circuit to be implemented by the programmable logic device (PLD); and
setting a supply voltage level of at least a portion of the critical circuit path.
29. The method according to claim 28, wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises programming a configuration memory (CRAM) of the programmable logic device (PLD).
30. The method according to claim 29, wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises adjusting an impedance of a variable impedance device depending on a value programmed in the configuration memory (CRAM).
31. The method according to claim 28, further comprising adjusting the supply voltage level of at least a portion of the critical circuit path.
32. The method according to claim 31, wherein adjusting the supply voltage level of at least a portion of the critical circuit path further comprises trading off speed and power consumption of the at least a portion of the critical circuit path.
33. The method according to claim 28, wherein setting a supply voltage level of at least a portion of the critical circuit path further comprises using an output signal of a control circuit.
34. The method according to claim 33, wherein setting a supply voltage level of at least a portion of the critical path further comprises adjusting an impedance of a variable impedance device by using the output signal of the control circuit.
35. A method of operating a programmable logic device (PLD), the method comprising:
setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level;
determining whether a performance measure of the programmable logic device (PLD) meets a criterion; and
adjusting the supply voltage level of the first circuit depending on whether the performance measure of the programmable logic device (PLD) meets the criterion.
36. The method according to claim 35, wherein determining whether a performance measure of the programmable logic device (PLD) meets a criterion further comprises obtaining the performance measure.
37. The method according to claim 36, wherein obtaining the performance measure further comprises sensing a quantity within the programmable logic device (PLD).
38. The method according to claim 37, wherein sensing a quantity within the programmable logic device (PLD) further comprises sensing a temperature.
39. The method according to claim 35, wherein adjusting the supply voltage level of the first circuit further comprises:
leaving the supply voltage level of the first circuit unchanged if the performance measure of the programmable logic device (PLD) meets the criterion; and
changing the supply voltage level of the first circuit to a second level if the performance measure of the programmable logic device (PLD) fails to meet the criterion.
40. The method according to claim 35, wherein the performance measure comprises a speed of operation of the first circuit.
41. The method according to claim 35, wherein the performance measure comprises a power consumption of the first circuit.
42. The method according to claim 35, wherein setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level further comprises setting the supply voltage to a level derived from information received from a source external to the programmable logic device.
43. The method according to claim 35, wherein setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level further comprises setting the supply voltage to a level specified by configuration data of the programmable logic device (PLD).
44. The method according to claim 35, further comprising using a feedback circuit to determine if the performance measure of the programmable logic device (PLD) meets the criterion.
45. A method of operating a programmable logic device (PLD) configured to function in an operating environment, the method comprising:
setting a supply voltage level of a first circuit in the programmable logic device (PLD) to a first level; and
adjusting the supply voltage level of the first circuit depending on at least one characteristic of the operating environment of the programmable logic device (PLD).
46. The method according to claim 45, wherein adjusting the supply voltage level of the first circuit further comprises adjusting the supply voltage level of the first circuit to a second level if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be changed.
47. The method according to claim 46, wherein adjusting the supply voltage level of the first circuit further comprises increasing an operating speed of the first circuit if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be increased.
48. The method according to claim 47, wherein adjusting the supply voltage level of the first circuit further comprises trading off the operating speed of the first circuit with a power consumption of the first circuit.
49. The method according to claim 46, wherein adjusting the body-bias level of the at least one transistor further comprises decreasing an operating speed of the first circuit if the at least one characteristic of the operating environment indicates that a performance of the first circuit should be decreased.
Description
TECHNICAL FIELD

The inventive concepts relate generally to adjusting the performance of programmable logic devices (PLDs). More particularly, the invention concerns adjusting the supply voltage/power consumption of PLDs, as well as noise reduction and isolation in PLDs.

BACKGROUND

PLDs are ubiquitous electronic devices that provide flexibility to not only designers, but also end-users. During the design cycle of an electronic circuit or system, a designer may perform a relatively large number of design iterations by simply re-programming the PLD for each design. Thus, the length and expense of the design cycle decreases compared to other alternatives. Similarly, the end-user may have a desired level of control over the functionality of a design that includes PLD(s). By programming the PLD(s) in the field or even on a real-time basis, the user can change the way the circuit or system behaves.

To accommodate increasingly complex designs, modern PLDs include a relatively large number of transistors. Furthermore, users demand ever higher performance, which results in larger operating frequencies. Consequently, the power consumption, power dissipation, die temperatures and, hence, power density (power dissipation in various circuits or blocks), of PLDs has tended to increase. The upward march of the power density, however, may make PLDs design and implementation impractical or failure-prone. A need exists for PLDs that feature adjustable performance, such as adjustable power consumption in various PLD blocks and circuits.

SUMMARY

The disclosed novel concepts relate to apparatus and methods for adjusting the performance of PLDs, including adjusting the supply voltage/power consumption of PLDs, as well as noise reduction and isolation in PLDs. One aspect of the invention relates to apparatus for adjusting the performance of PLDs. In one embodiment, a PLD includes a circuit that controls a supply voltage of another circuit within the PLD. The controlling circuit further filters noise within the PLD.

In another embodiment, a PLD includes a circuit that resides in a deep n-well in the PLD. The circuit in the deep n-well couples to a variable impedance device. The variable impedance device adjusts the supply voltage of the circuit in the deep n-well, thus adjusting its performance.

Another aspect of the invention relates to methods of configuring, operating, and adjusting the performance of PLDs. In one embodiment, a method of configuring a PLD to implement an electronic circuit includes mapping the electronic circuit to functional resources within the PLD to generate a circuit to be implemented by the PLD. The method further includes identifying at least one critical circuit path in the circuit to be implemented by the PLD, and setting the supply voltage level of at least a portion of the critical circuit path.

In another embodiment, a method of operating a PLD includes setting the supply voltage level of a circuit in the PLD to a voltage level, and determining whether a performance measure of the PLD meets a particular criterion. The method further includes adjusting the supply voltage level of the circuit depending on whether the performance measure of the PLD meets the criterion.

Another embodiment relates to a method of operating a PLD that is configured to function in a desired or prescribed operating environment. More specifically, the method includes setting the supply voltage level of a circuit in the PLD to a voltage level, and adjusting the supply voltage level of the first circuit depending on at least one characteristic of the operating environment of the programmable logic device (PLD).

BRIEF DESCRIPTION OF THE DRAWINGS

The appended drawings illustrate only exemplary embodiments of the invention and therefore should not be considered as limiting its scope. Persons of ordinary skill in the art who have the benefit of the description of the invention appreciate that the disclosed inventive concepts lend themselves to other equally effective embodiments. In the drawings, the same numeral designators used in more than one drawing denote the same, similar, or equivalent functionality, components, or blocks.

FIG. 1 shows a general block diagram of a PLD according to an illustrative embodiment of the invention.

FIG. 2 illustrates a floor-plan of a PLD according to an exemplary embodiment of the invention.

FIG. 3 depicts a block diagram of an exemplary embodiment of programmable logic in a PLD according to the invention.

FIG. 4 shows a circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention.

FIG. 5 illustrates another circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention.

FIG. 6 depicts a circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.

FIG. 7 shows another circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention.

FIG. 8 illustrates an arrangement for providing a flexible mechanism for adjusting the performance of the various parts of a PLD according to an exemplary embodiment of the invention.

FIGS. 9A-9C depict circuit arrangements for distributing and generating power supply voltages in PLDs according to exemplary embodiments of the invention.

FIG. 10 shows an example of using n-wells to isolate noise-sensitive circuits in a PLD according to an illustrative embodiment of the invention.

FIG. 11 illustrates various software modules that PLD computer-aided design (CAD) software according to illustrative embodiments of the invention uses.

FIG. 12 depicts a flow diagram for a PLD CAD software according to an exemplary embodiment of the invention.

FIG. 13 shows a block diagram of circuitry within a PLD according to exemplary embodiments of the invention to adjust, program, or set the supply voltage levels of desired parts of the PLD.

FIG. 14 illustrates a circuit arrangement according to exemplary embodiments of the invention for adjusting supply voltage levels within a PLD in response to an external source.

FIG. 15 depicts a circuit arrangement for adjusting supply voltage level(s) within a PLD according to exemplary embodiments of the invention.

DETAILED DESCRIPTION

The inventive concepts contemplate apparatus and associated methods for PLDs that feature adjustable supply voltage (and, hence, power consumption and performance), reduced noise levels, and noise isolation. The inventive concepts help to overcome excessive power density levels that conventional PLDs suffer. Moreover, one may adjust the performance level of a desired portion, circuit, or block (or all circuits and blocks), of a PLD according to the invention. Put another way, one may adjust the performance by programming the supply voltage and the attendant power dissipation of the circuitry within the PLD with a desired level of granularity, ranging from individual circuit blocks, all the way to the entire PLD circuitry.

More specifically, and as described below in detail, the inventive concepts contemplate controlling the supply voltage and power consumption of one or more circuits or blocks of circuits within the PLD by using a variable impedance circuit. In addition, one may use the variable impedance circuit to form a filter that, simultaneously with the adjustment of the power consumption, tend to reduce the noise levels present within the PLD. The reduced noise levels help to protect sensitive circuitry within the PLD from adverse effects of electrical noise. Furthermore, one may protect noise-sensitive circuitry within the PLD by using deep n-well structures within the PLD that help to isolate the sensitive circuitry from sources of electrical noise.

The inventive concepts provide the following benefits over traditional implementations. First, they allow trading off performance and power consumption or optimizing the performance-power consumption tradeoff. Second, one may selectively set, program, or adjust the supply voltage and power consumption in critical circuit paths or parts of the PLD so as to increase their performance as desired. Conversely, one may selectively set, program, or adjust the supply voltage and power consumption in non-critical circuit paths or parts of the PLD to levels commensurate with their desired performance.

One may also employ the inventive concepts to prevent (or reduce the probability of) thermal runaway. More specifically, in a traditional PLD, circuits operating at relatively high speeds tend to consume more power, resulting in temperature increase of the PLD. The increased power consumption may in turn cause those circuits to consume more power. This positive feedback mechanism may increase the power densities to unsafe or destructive levels. In PLDs according to the invention, one may adjust or control the supply voltage and power consumption levels of various blocks and, hence, reduce the likelihood of thermal runaway. Furthermore, the inventive concepts help to provide better performance by reducing the noise levels within the PLD and to isolate noise-sensitive circuitry from the undesirable effects of noise.

FIG. 1 shows a general block diagram of a PLD 103 according to an illustrative embodiment of the invention. PLD 103 includes configuration circuitry 130, configuration memory 133, control circuitry 136, programmable logic 106, programmable interconnect 109, and I/O circuitry 112. In addition, PLD 103 may include test/debug circuitry 115, one or more processors 118, one or more communication circuitry 121, one or more memories 124, one or more controllers 127, as desired.

Note that FIG. 1 shows a simplified block diagram of PLD 103. Thus, PLD 103 may include other blocks and circuitry, as persons of ordinary skill in the art understand. Examples of such circuitry include clock generation and distribution circuits, redundancy circuits, and the like. Furthermore, PLD 103 may include, analog circuitry, other digital circuitry, and/or mixed-mode circuitry, as desired.

Programmable logic 106 includes blocks of configurable or programmable logic circuitry, such as look-up tables (LUTs), product-term logic, multiplexers, logic gates, registers, memory, and the like. Programmable interconnect 109 couples to programmable logic 106 and provides configurable interconnects (coupling mechanisms) between various blocks within programmable logic 106 and other circuitry within or outside PLD 103.

Control circuitry 136 controls various operations within PLD 103. Under the supervision of control circuitry 136, PLD configuration circuitry 130 uses configuration data (which it obtains from an external source, such as a storage device, a host, etc.) to program or configure the functionality of PLD 103. The configuration data typically reside in configuration memory 133. The configuration data determine the functionality of PLD 103 by programming programmable logic 106 and programmable interconnect 109, as persons skilled in the art with the benefit of the description of the invention understand.

I/O circuitry 112 may constitute a wide variety of I/O devices or circuits, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. I/O circuitry 112 may couple to various parts of PLD 103, for example, programmable logic 106 and programmable interconnect 109. I/O circuitry 112 provides a mechanism and circuitry for various blocks within PLD 103 to communicate with external circuitry or devices.

Test/debug circuitry 115 facilitates the testing and troubleshooting of various blocks and circuits within PLD 103. Test/debug circuitry 115 may include a variety of blocks or circuits known to persons of ordinary skill in the art who have the benefit of the description of the invention. For example, test/debug circuitry 115 may include circuits for performing tests after PLD 103 powers up or resets, as desired. Test/debug circuitry 115 may also include coding and parity circuits, as desired.

As noted above, PLD 103 may include one or more processors 118. Processor 118 may couple to other blocks and circuits within PLD 103. Processor 118 may receive data and information from circuits within or external to PLD 103 and process the information in a wide variety of ways, as persons skilled in the art with the benefit of the description of the invention appreciate. One or more of processor(s) 118 may constitute a digital signal processor (DSP). DSPs allow performing a wide variety of signal processing tasks, such as compression, decompression, audio processing, video processing, filtering, and the like, as desired.

PLD 103 may also include one or more communication circuitry 121. Communication circuitry 121 may facilitate data and information exchange between various circuits within PLD 103 and circuits external to PLD 103, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. As an example, communication circuitry 121 may provide various protocol functionality (e.g., Transmission Control Protocol/Internet Protocol (TCP/IP), User Datagram Protocol (UDP) etc.), as desired. As another example, communication circuitry 121 may include network (e.g., Ethernet, token ring, etc.) or bus interface circuitry, as desired.

PLD 103 may further include one or more memories 124 and one or more controller(s) 127. Memory 124 allows the storage of various data and information (such as user-data, intermediate results, calculation results, etc.) within PLD 103. Memory 124 may have a granular or block form, as desired. Controller 127 allows interfacing to, and controlling the operation and various functions of circuitry outside the PLD. For example, controller 127 may constitute a memory controller that interfaces to and controls an external synchronous dynamic random access memory (SDRAM), as desired.

In addition to the circuitry that FIG. 1 shows, PLD 103 may include analog or mixed-mode circuitry 139, sometimes known as analog or mixed-mode intellectual property (IP) blocks. For example, PLD 103 may include amplifiers, digital-to-analog converters, analog-to-digital converters, filters, and the like. By their nature, analog/mixed-mode circuits tend to exhibit sensitivity to noise. As described below in detail, the inventive concepts help to isolate noise-sensitive circuitry from noise-generating circuitry. Furthermore, the inventive concepts include techniques that tend to reduce the noise levels present in PLDs.

FIG. 2 shows a floor-plan of a PLD 103 according to an exemplary embodiment of the invention. PLD 103 includes programmable logic 106 arranged as a two-dimensional array. Programmable interconnect 109, arranged as horizontal interconnect and vertical interconnect, couples the blocks of programmable logic 106 to one another.

One may adjust the supply voltage and, hence, the power dissipation level, of each block of programmable logic 106, each segment of programmable interconnect 109, or both, as desired. Furthermore, one may adjust the supply voltage and the power dissipation level of a portion of one or more blocks of programmable logic 106, a portion of programmable interconnect 109, or both, as desired.

In illustrative embodiments, PLDs according to the invention have a hierarchical architecture. In other words, each block of programmable logic 106 in FIG. 2 may in turn include smaller or more granular programmable logic blocks or circuits. One may adjust the supply voltage and power consumption or dissipation in each level of the hierarchical architecture of the PLD, as desired.

FIG. 3 shows a block diagram of an exemplary embodiment of programmable logic 106 in a PLD according to the invention. Programmable logic 106 includes logic elements or programmable logic circuits 250, local interconnect 253, interface circuit 256, and interface circuit 259. Logic elements 250 provide configurable or programmable logic functions, for example, LUTs, registers, product-term logic, etc., as persons of ordinary skill in the art who have the benefit of the description of the invention understand. Local interconnect 253 provides a configurable or programmable mechanism for logic elements 250 to couple to one another or to programmable interconnect 109 (sometimes called “global interconnect”), as desired.

Interface circuit 256 and interface circuit 259 provide a configurable or programmable way for programmable logic 106 block of circuitry to couple to programmable interconnect 109 (and hence to other programmable logic 106, as FIG. 2 shows). Interface circuit 256 and interface circuit 259 may include multiplexers (MUXs), registers, buffers, drivers, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.

One may adjust the supply voltage and power consumption of each portion or block of circuitry within PLD 103 (see FIGS. 1-3), as desired. Furthermore, one may adjust the supply voltage and power consumption of each portion or block of circuitry independently of others, on an individual or collective basis, as desired. Within each portion or block of circuitry, one may adjust the supply voltage and power consumption of each sub-block, or groups of sub-blocks, as desired.

For example, one may adjust the supply voltage and power consumption of all or a portion of the following circuitry within a PLD according to exemplary embodiments of the invention: one or more of the blocks in FIG. 1 (e.g., programmable logic 106, programmable interconnect 109, etc.); one or more logic elements 250 within one or more programmable logic blocks 106; one or more interface circuits 256 and/or 259, within one or more programmable logic blocks 106; one or more local interconnect within one or more programmable logic 106; and one or more MUXs, drivers, buffers, etc., within one or more interface circuits 256 and/or 259.

As noted above, one may make the supply voltage and power consumption adjustments in any desired level of granularity. In other words, one may make the adjustments applicable to sub-blocks, blocks, regions, or the entire PLD, as desired, and as applicable. For example, one may make supply voltage and power consumption adjustments to one or more of such elements of the PLD independently of one or more of other elements within the PLD, as desired. As persons of ordinary skill in the art with the benefit of the description of the invention understand, one may adjust the supply voltage and power consumption of some parts of a PLD and yet provide a fixed or default supply voltage and power consumption for other parts of the PLD, as desired.

FIG. 4 shows a circuit arrangement for adjusting the supply voltage and, hence, the power consumption of a desired circuit in a PLD according to an exemplary embodiment of the invention. More specifically, the circuit arrangement in FIG. 4 shows a controlled PLD circuit 300 that includes control circuit 303, PLD circuit 306, and variable impedance device 309.

The circuit operates as follows: In response to one or more signals not shown explicitly in FIG. 4 (such as a bias signal and configuration signals, described in connection with FIG. 13) circuit 303 applies a corresponding control signal (or signals, depending on the nature of variable impedance device 309) so as to cause adjustment of the supply voltage that variable impedance device 309 provides to PLD circuit 306. Consequently, control circuit 303 can cause the adjustment of the power consumption (and other performance criteria, such as operating speed) of PLD circuit 306.

Variable impedance device 309 couples the supply voltage, VDD, to PLD circuit 306. When variable impedance device 309 has a relatively high impedance, PLD circuit 306 conducts relatively little current, and has a nearly zero supply voltage. Thus, PLD circuit 306 effectively shuts down or enters an OFF state or sleep mode. In this state, PLD circuit 306 consumes nearly zero power.

At the other extreme, when variable impedance device 309 has a relatively low impedance, PLD circuit 306 receives nearly the voltage VDD as its supply voltage (minus any drop across variable impedance device 309). In this state, PLD circuit 306 typically has higher power consumption, but also higher speed. Thus, by varying the effective supply voltage of PLD circuit 306 between the two extremes of near-zero and near-VDD supply voltages, one may trade off its various performance measures, such as power consumption and speed.

PLD circuit 306 may constitute any desired region, block, circuitry, sub-block, or collection of each of those parts, of a PLD. For example, PLD circuit 306 may constitute one or more of the elements shown in FIGS. 1-3, such as programmable interconnect 109, logic elements 250, etc., as desired.

As described below in detail, control circuit 303 may operate under the supervision of one or more other parts of the PLD, or under the control of an external source, or a combination of internal and external sources, as desired. Control circuit 303 causes the impedance of the variable impedance device to change. As a result, the effective supply voltage provided to PLD circuit 306 varies. The effective supply voltage of PLD circuit 306 affects its characteristics, such as operating speed, power consumption, and the like. By adjusting the supply voltage level for PLD circuit 306, one may trade off its various characteristics, such as speed versus power consumption.

Variable impedance device 309 may constitute a desired type of device, depending on factors such as the particular PLD implementation, circuit and process technology, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. As one example, variable impedance device 309 may constitute a transistor.

FIG. 5 illustrates another circuit arrangement for adjusting the supply voltage of a desired circuit in a PLD according to an exemplary embodiment of the invention. The circuit arrangement in FIG. 5 is similar to the circuit in FIG. 4. FIG. 5, however, uses a transistor 320 and, more particularly, a metal oxide semiconductor field effect transistor (MOSFET) transistor, as a particular type of variable impedance device.

Depending on factors such as the particular PLD implementation, circuit and process technology, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand, transistor 320 may constitute a variety of devices, such as bipolar junction transistors (BJTs), bipolar hetero-junction transistor (BHT), and the like.

In one embodiment implemented using metal oxide semiconductor (MOS) or complementary MOS (CMOS) technology, transistor 320 may constitute a native transistor, as desired. Native transistors may have a negative or small threshold voltage, VT, thus making biasing or driving transistor 320 easier in situations where a relatively small VDD results in a small headroom in the output voltage of control circuit 303.

As noted above, PLDs according to the invention may include noise-sensitive analog or mixed-mode circuitry. One may use filtering techniques to help reduce the overall noise in the PLD or the noise level that the analog or mixed-mode circuitry experiences.

FIG. 6 depicts a circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention. Controlled PLD circuit 300 in FIG. 6 is analogous to the circuit shown in FIG. 4, and provides similar benefits. Thus, the circuitry in FIG. 6 provides the capability of controlling the supply voltage and, hence, the performance, of PLD circuit 306, as described above in detail. In the circuit of FIG. 6, PLD circuit 306 constitutes a circuit with relatively high sensitivity to noise, such as an analog or mixed-mode circuit.

In addition to the elements shown in FIG. 4, the circuit arrangement in FIG. 6 includes capacitor 323 and capacitor 326. Together with various impedances present in the circuit, each of those capacitors forms a filter. For example, capacitor 326, together with the parallel impedance of variable impedance device 309 and PLD circuit 306, forms a low-pass filter. By filtering higher frequencies, the low-pass filters tend to reduce the overall noise level that PLD circuit 306 experiences. Note that one may omit one of capacitors 323 and 326, depending on factors such as the desired level of filtering, the size and value of components, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.

FIG. 7 shows another circuit arrangement for reducing the noise level in a PLD according to an exemplary embodiment of the invention. The circuit arrangement in FIG. 7 constitutes a more specific implementation of the circuit in FIG. 6. More specifically, rather than a general variable impedance device 309 in FIG. 6, the circuit arrangement in FIG. 7 uses transistor 320. Transistor 320 may generally constitute any of the devices described above with respect to FIG. 5, as desired. Note that, as described above, one may omit one of capacitors 323 and 326, depending on factors such as the desired level of filtering, the size and value of components, and the like, as persons of ordinary skill in the art who have the benefit of the description of the invention understand.

Using controlled PLD circuit 300 described above, one may adjust the supply voltage and power consumption and thus performance of various parts of PLDs. FIG. 8 shows an arrangement for providing a flexible mechanism for adjusting the performance of the various parts of a PLD 103 according to an exemplary embodiment of the invention. PLD 103 includes one or more PLD circuit regions or “islands” 400A-400C. Each PLD circuit region 400A-400C includes one or more controlled PLD circuits 300, as described above.

Each of PLD circuit regions 400A-400C may receive one or more power supply voltages, labeled as VDD1-VDDN. As examples, PLD circuit region 400A receives VDD1, whereas circuit region 400B receives VDD1-VDD3, and circuit region 400C receives VDDN. Each of controlled PLD circuits 300 can adjust the supply voltage provided to its respective PLD circuit 306 (see, for example, FIG. 4), as described above in detail.

By assigning a desired set of power supply voltages to each of PLD circuit regions 400A-400C, one may adjust the supply voltage and power consumption of circuitry within the circuit regions. Furthermore, by including a desired set of controlled PLD circuits 300 within a given circuit region 400A-400C, one may match the type of supply voltage adjustment in each circuit region 40OA-400C with one or more suitable controlled PLD circuits 300. Thus, the arrangement in FIG. 8 provides a flexible mechanism for allocating various PLD resources to implementing an appropriate part of the user's design or system so as to provide an efficient implementation with improved performance adjustment capabilities and better overall performance. (e.g., speed-power consumption tradeoff).

Note that, in addition to, or rather than, receiving external power supply voltages (e.g., VDD1-VDDN in FIG. 8), PLD 103 may generate power supply voltages internally, as desired. FIGS. 9A-9C show circuit arrangements for distributing and generating power supply voltages in PLDs according to exemplary embodiments of the invention.

In FIG. 9A, PLD 103 simply uses the external power supply voltages that it receives, e.g., VDD1-VDDN. In this scenario, PLD 103 may use a power distribution and supply voltage adjustment scheme, such as the arrangement in FIG. 8.

In FIG. 9B, PLD 103 receives power supply voltages VDD1-VDDN. PLD 103 may regulate one or more of the power supply voltages to generate one or more internal power supply voltages. PLD 103 may then use the external and the internally generated powers supply voltages in a power distribution and supply voltage adjustment scheme, e.g., as shown in FIG. 8. In the particular example shown, PLD 103 uses voltage regulator 450 to generate internal power supply voltage VDD2′ from external power supply voltage VDD2.

In FIG. 9C, PLD 103 receives power supply voltages VDD1-VDDN. PLD 103 may use one or more charge pumps 453 to generate one or more internal power supply voltages. PLD 103 may then use the external and the internally generated powers supply voltages in a power distribution and supply voltage adjustment scheme, e.g., as shown in FIG. 8. In the particular example shown, PLD 103 uses charge pump 453 to generate internal power supply voltage VDD1′ from external power supply voltage VDD1. Internal power supply voltage VDD1′ has a higher voltage level than VDD1.

As noted above, the inventive concepts include techniques for isolating noise-sensitive circuits from noise-generating circuitry with the PLD. More particularly, in PLDs fabricated using CMOS technology, various PLD circuits typically reside in a number of deep n-wells. By strategically placing noise-sensitive circuits in isolated n-wells, one may shield or isolate the noise-sensitive circuits from sources of noise. Thus, one may provide islands within the PLD, each with its own supply voltage, power consumption, noise generation, and noise isolation characteristics. The islands provide a mechanism in PLDs according to the invention for providing a flexible implementation of a user's design or system.

FIG. 10 shows an example of using n-wells to isolate noise-sensitive circuits in a PLD according to an illustrative embodiment of the invention. The PLD resides in substrate 500. Substrate 500 includes deep n-wells 503, 506, and 509. Each of deep n-wells 503, 506, and 509 may include a variety of PLD circuitry, such as the circuits shown in FIGS. 1-3.

As noted, one may place the various circuits in deep n-wells 503, 506, and 509 so as to reduce interference and noise. For example, one may place circuitry with relatively high noise sensitivity (labeled as 506A) in a PLD that includes circuits that generate moderate amounts of noise (labeled as 506B) as well as circuits that produce relatively high levels of noise (labeled as 506C). As the example in FIG. 10 illustrates, one may place circuits 506A, 506B, and 506C in deep n-wells 503, 506, and 509, respectively. Noise and interference tends to decrease by the virtue of placing noise-sensitive circuit 506A farthest from the relatively high levels of noise that circuit 506C generates, but nearer to the moderate levels of noise that circuit 506B produces.

Note that deep n-wells represent an illustrative construct in a PLD fabrication technology. Depending on a number of factors, one may use other constructs and devices in current and future fabrication technologies, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. The factors include the type and characteristics of the technology and the devices and constructs available, the desired design and performance specifications, cost, complexity, area efficiency, and the like.

As an example, one may use silicon-on-insulator (SOI) technology to provide noise isolation and control within PLDs. More specifically, and as persons of ordinary skill in the art who have the benefit of the description of the invention understand, SOI circuits tend to provide isolation between transistors because of the insulator layer (typically silicon dioxide). Thus, SOI circuits provide a mechanism for isolating noise-sensitive circuits from noise-generating circuits of the PLD.

As noted above, the user may adjust the supply voltage and power consumption and noise exposure or performance of various portions of PLDs according to the invention. The user may do so by using the software used to map a design to a PLD. FIG. 11 depicts various software modules that PLD computer-aided design (CAD) software according to illustrative embodiments of the invention uses. The modules include design-entry module 550, synthesis module 553, place-and-route module 556, and verification module 559.

Design-entry module 550 allows the integration of multiple design files. The user may generate the design files by using design-entry module 550 or by using a variety of electronic design automation (EDA) or CAD tools (such as industry-standard EDA tools), as desired. The user may enter the design in a graphic format, a waveform-based format, a schematic format, in a text or binary format, or as a combination of those formats, as desired.

Synthesis module 553 accepts the output of design-entry module 550. Based on the user-provided design, synthesis module 553 generates appropriate logic circuitry that realizes the user-provided design. One or more PLDs (not shown explicitly) implement the synthesized overall design or system.

Synthesis module 553 may also generate any glue logic that allows integration and proper operation and interfacing of various modules in the user's designs. For example, synthesis module 553 provides appropriate hardware so that an output of one block properly interfaces with an input of another block. Synthesis module 553 may provide appropriate hardware so as to meet the specifications of each of the modules in the overall design or system.

Furthermore, synthesis module 553 may include algorithms and routines for optimizing the synthesized design. Through optimization, synthesis module 553 seeks to more efficiently use the resources of the one or more PLDs that implement the overall design or system. In some embodiments, synthesis module 553 may identify critical paths within the synthesized design or system. Synthesis module 553 provides its output to place-and-route module 556.

Place-and-route module 556 uses the designer's timing specifications to perform optimal logic mapping and placement. The logic mapping and placement determine the use of routing resources within the PLD(s). In other words, by use of particular programmable interconnects with the PLD(s) for certain parts of the design, place-and-route module 556 helps optimize the performance of the overall design or system.

By proper use of PLD routing resources, place-and-route module 556 helps to meet the critical timing paths of the overall design or system. Place-and-route module 556 optimizes the critical timing paths to help provides timing closure faster in a manner known to persons of ordinary skill in the art with the benefit of the description of the invention. As a result, the overall design or system can achieve faster performance (i.e., operate at a higher clock rate or have higher throughput).

Furthermore, place-and-route module 556 adjusts the supply voltage and power consumption and the noise performance or exposure of a portion of or all of the PLD(s) that implement the design or system. Place-and-route module 556 may do so automatically, according to user-specified criteria, or a combination of the two. Place-and-route module 556 may use the user-specified criteria (for example, performance specifications, such as power dissipation, noise exposure or performance, speed, and/or current-drive capability). In addition, or instead, place-and-route module 556 may use the information about critical paths within the design or system to adjust the supply voltage(s), physical placement so as to reduce noise generation and exposure, and power consumption of parts or all of the design or system, as desired.

For example, place-and-route module 556 may adjust the supply voltage and power consumption of the critical parts of the design or system so as to achieve higher performance. Place-and-route module 556 may take into account power dissipation criteria (e.g., maximum power density) so as to trade off power and performance, as desired. Place-and-route module 556 provides the optimized design to verification module 559.

Verification module 559 performs simulation and verification of the design. The simulation and verification seek in part to verify that the design complies with the user's prescribed specifications. The simulation and verification also aim at detecting and correcting any design problems before prototyping the design. Thus, verification module 559 helps the user to reduce the overall cost and time-to-market of the overall design or system.

Verification module 559 may support and perform a variety of verification and simulation options, as desired. The options may include design-rule checking, functional verification, test-bench generation, static timing analysis, timing simulation, hardware/software simulation, in-system verification, board-level timing analysis, signal integrity analysis and electromagnetic compatibility (EMC), formal netlist verification, noise generation and exposure, and power-consumption estimation, as desired. Note that one may perform other or additional verification techniques as desired and as persons of ordinary skill in the art who have the benefit of the description of the invention understand.

FIG. 12 illustrates a flow diagram for a PLD CAD software according to an exemplary embodiment of the invention. The PLD CAD shown in FIG. 12 incorporates the choice of supply voltage and power consumption for each region of the PLD into a timing-driven place-and-route CAD system. Note that, as desired, one may include criteria for noise generation, noise exposure, and/or noise isolation into the PLD CAD in FIG. 12 by making modifications that fall within the knowledge of persons of ordinary skill in the art who have the benefit of the description of the invention.

Starting the process, at 603 the PLD CAD sets initial supply voltage levels (corresponding to estimated power consumption levels). At 606 the software generates an initial placement. Then, at 609 it analyzes the timing of the circuitry using delay estimates that reflect the various settings, such as supply voltage settings. At 612 the software determines whether it has met the user's various criteria, such as timing and power goals. If so, at 615 it records the placement and supply voltage selections. If not, the software checks at 618 to determine whether it has reached the iteration limit. If so, it proceeds to 615 to record the current placement and supply voltage selections.

If the software has not reached the iteration limit, it increments the iteration count (not shown explicitly), and at 621 changes the settings of at least some regions, circuits, blocks, or parts of the PLD. At 624 it analyzes the timing of the circuitry using delay estimates that reflect the changed settings. At 356 it improves the placement of the circuit, and jumps to 612 to determine whether it has met the user's timing and power goals. Once the PLD CAD has implemented a design (i.e., synthesized, placed and routed the design), the CAD software should automatically provide data for programming the PLD that set the supply voltages of various parts of the PLD.

FIG. 13 shows a block diagram of circuitry within a PLD according to exemplary embodiments of the invention to adjust, program, or set the supply voltage levels of desired parts of the PLD. The circuitry includes bias circuit 703, a plurality of configuration memory (configuration random-access memory, or CRAM, or other implementations of the memory) cells 709, and controlled PLD circuits 300.

Bias circuit 703 generates one or more signals 706 and provides those signal(s) to controlled PLD circuits 300 (more particularly, to control circuit 303, as shown, for example, in FIG. 4). In other word, bias circuit 703 provides one or more global bias signals to controlled PLD circuits 300. Furthermore, each of CRAM cells 709 provides to a respective one of controlled PLD circuits 300 (more particularly, to control circuit 303). The signals from CRAM cells 709 represent configuration data for the various circuits within the PLD, as provided by the PLD CAD program described above. In response to configuration data from CRAM cells 709, the control circuit (not shown explicitly) in each of controlled PLD circuits 300 generates one or more signals to control the impedance of the variable impedance device (not shown explicitly) as a function of signal(s) 706.

In other variations, each of CRAM cells 709 may provide configuration data to more than one controlled PLD circuit, as desired. Conversely, one may modify the control circuit within controlled PLD circuits 300 so as to make it responsive to configuration data from more than one CRAM cell 709, as desired.

Note that one may adjust, program, or set supply voltage levels in response to sources external to the PLD. For example, one may communicate supply voltage levels to a PLD to adjust or modify its performance. FIG. 14 shows a circuit arrangement according to exemplary embodiments of the invention for adjusting supply voltage levels within PLD 103 in response to an external source 753. The circuit arrangement includes external source 753, communication/interface circuit 762, and bias circuit 703 (see FIG. 13).

Communication/interface circuit 762 provides a mechanism for external source 753 and bias circuit 703 to communicate and exchange information. External source 753 may provide one or more control signal(s) 756 to communication/interface circuit 762 within PLD 103. Communication/interface circuit 762 provides the information received from external source 753 to bias circuit 703. In response, bias circuit 703 generates one or more signals 706, with levels corresponding to control signal(s) 756. Communication/interface circuit 762 may provide information, such as status signals, from bias circuit 703 (or PLD 103 generally) to external source 753.

External source 753 may constitute a variety of devices, structures, or arrangements, as persons of ordinary skill in the art with the benefit of the description of the invention understand. For example, external source 753 may constitute a computer network (e.g., the Internet), a telephone-line communication link, a wireless communication link, a bus, etc., as desired.

Note that one may adjust, program, or set the supply voltage levels in PLDs on a dynamic or time-varying basis, as desired, to take into account or respond to changing conditions (for example, changes in performance specifications). As one example, referring to FIG. 14, external source 753 may update or modify control signal(s) 756 that it provides to PLD 103. Bias circuit 703 responds accordingly to the updated or modified signal(s) 756.

As another example, one may change or adjust supply levels in response to changes within PLD 103 itself, for instance, a change in temperature, noise, power consumption, and the like, in one or more circuits or areas of PLD 103. FIG. 15 shows a circuit arrangement for modifying supply voltage level(s) within a PLD according to exemplary embodiments of the invention.

The circuit arrangement includes one or more sensor(s) 803, one or more reference source(s) 806, subtracter 818, and bias circuit 703. Sensor(s) 803 sense a desired parameter (e.g., temperature, noise, etc.) in one or more areas, circuits, or blocks within PLD 103 and provide signal(s) 809 to subtracter 818. Reference source(s) 806 provide reference signal(s) 812 to subtracter 818. Reference signal(s) 812 may have values that correspond to various levels of the sensed parameter.

Subtracter 818 subtracts reference signal(s) 812 from signal(s) 809 and provides difference signal(s) 815 to bias circuit 703. Difference signal(s) 815 may constitute the difference between actual sensed value(s) and the desired value(s) in one or more parts of PLD 103. In response to difference signal(s) 815, bias circuit 703 generates signal(s) 706 (see also FIG. 13).

Bias circuit 703 may use difference signal(s) 815 to generate signal(s) 706 that ultimately affect various aspects of the performance of PLD 103. For example, if difference signal(s) 815 indicate a lower sensed value (say, speed) than a threshold or maximum value, bias circuit 703 may generate signal(s) that increase supply voltage level(s) to increase operating speed of the desired parts of PLD 103. In contrast, if difference signal(s) 815 indicate a sensed level higher than a safe or maximum level, bias circuit 703 may generate signal(s) that decrease supply voltage level(s) to safe or desired levels (albeit with a decreased resulting speed).

More generally, one may implement a feedback loop that generates supply voltage level(s) so as to target specific performance criteria. Put another way, one may compare actual performance measures of a PLD to desired or specified measures or criteria and adjust, program, or set supply voltage levels accordingly.

Note that one may apply the inventive concepts effectively to various programmable logic circuitry or ICs known by other names in the art, as desired, and as persons skilled in the art with the benefit of the description of the invention understand. Such circuitry include devices known as complex programmable logic device (CPLD), programmable gate array (PGA), and field programmable gate array (FPGA).

Referring to the figures, persons of ordinary skill in the art will note that the various blocks shown may depict mainly the conceptual functions and signal flow. The actual circuit implementation may or may not contain separately identifiable hardware for the various functional blocks and may or may not use the particular circuitry shown. For example, one may combine the functionality of various blocks into one circuit block, as desired. Furthermore, one may realize the functionality of a single block in several circuit blocks, as desired. The choice of circuit implementation depends on various factors, such as particular design and performance specifications for a given implementation, as persons of ordinary skill in the art who have the benefit of the description of the invention understand. Other modifications and alternative embodiments of the invention in addition to those described here will be apparent to persons of ordinary skill in the art who have the benefit of the description of the invention. Accordingly, this description teaches those skilled in the art the manner of carrying out the invention and are to be construed as illustrative only.

The forms of the invention shown and described should be taken as the presently preferred or illustrative embodiments. Persons skilled in the art may make various changes in the shape, size and arrangement of parts without departing from the scope of the invention described in this document. For example, persons skilled in the art may substitute equivalent elements for the elements illustrated and described here. Moreover, persons skilled in the art who have the benefit of this description of the invention may use certain features of the invention independently of the use of other features, without departing from the scope of the invention.

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Classifications
U.S. Classification326/33
International ClassificationH03K19/003
Cooperative ClassificationH03K19/0016, H03K19/17732, H03K19/17748, G06F2217/84, H03K19/17792, H03K19/17784, H03K19/00369, G06F17/5054
European ClassificationG06F17/50D4, H03K19/177D4, H03K19/177J6, H03K19/177J2, H03K19/177H, H03K19/003K, H03K19/00P6
Legal Events
DateCodeEventDescription
Dec 7, 2004ASAssignment
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHUMARAYEV, SERGEY Y.;PATEL, RAKESH;REEL/FRAME:016067/0118;SIGNING DATES FROM 20041115 TO 20041130