|Publication number||US20060131633 A1|
|Application number||US 11/018,131|
|Publication date||Jun 22, 2006|
|Filing date||Dec 21, 2004|
|Priority date||Dec 21, 2004|
|Also published as||US8242554, US20100038701|
|Publication number||018131, 11018131, US 2006/0131633 A1, US 2006/131633 A1, US 20060131633 A1, US 20060131633A1, US 2006131633 A1, US 2006131633A1, US-A1-20060131633, US-A1-2006131633, US2006/0131633A1, US2006/131633A1, US20060131633 A1, US20060131633A1, US2006131633 A1, US2006131633A1|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (22), Classifications (11), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
Conventional non-volatile memory cells employ floating gate device technology. A floating gate cell can be programmed by injecting electrons to the silicon floating gate by channel hot carrier injection (CHE) to put the cell into a high threshold state. The cell can be erased by hot hole injection from the substrate plus electron back-tunneling to the substrate by Fowler-Nordheim tunneling to put the cell in a low threshold state. Both mechanisms require high fields across the gate dielectric layers with resulting adverse effects in device characteristics and reliability.
CHE can consume large amounts of power for writing, generates interface states, degrades device transconductance, and enhances back-tunneling that affects charge retention and read-disturb. Fowler-Nordheim tunneling and associated hot-hole injection generates fixed charge centers in tunneling dielectrics and shallow traps and defects in the trapping layer, thus breaking stable bonds and eventually degrading the dielectric properties of the device.
As computers become smaller and their performance increases, the computer memories have also gone through a corresponding size reduction and performance increase. However, flash memory devices present a challenge in scalability due, at least in part, to the high programming voltages typically required. Their performance can also suffer due to the above-discussed limitations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more scalable, higher performance non-volatile memory device.
The above-mentioned problems with scalable memory and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
The present invention encompasses a non-volatile memory cell that has an oxy-nitride tunnel insulator formed over a substrate, a trapping layer formed over the tunnel insulator, a charge blocking layer formed over the trapping layer, and a control gate formed over the charge blocking layer. In one embodiment, both the oxy-nitride tunnel insulator and the trapping layer are formed from SiON and the control gate is comprised of a layer of TiN or TaN between the blocking layer and the polysilicon material.
In another embodiment, a memory cell is comprised of both a fixed threshold element and a bistable element. The fixed threshold element is formed by a gate insulator and control gate having a TiN or TaN layer. The bistable element is comprised of an ONO-type insulator stack such as the SiON insulator acting as tunnel and trapping layers with the charge blocking layer.
Further embodiments of the invention include methods and apparatus of varying scope.
In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. The terms wafer or substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions.
A tunnel insulator layer 101 is formed over the substrate 100 that, in one embodiment, is comprised of p-type silicon. An alternate embodiment may use an n-type material. The substrate 100 has doped regions 110 and 112 that are used as source and drain regions.
In one embodiment, the tunnel insulator 101 is formed from silicon oxynitride (SiON). The SiON provides good back-tunneling characteristics in order to prevent a charge from leaking back to the substrate 100. Alternate embodiments may use other materials such as another oxynitride material or an oxide material. As discussed subsequently, the tunnel insulator 101 is a common element between the bistable element and the fixed threshold element of the present invention.
The tunnel insulator 101 can be formed over the substrate 100 using an atomic layer deposition (ALD) technique to produce a thickness, in one embodiment, in the range of 2-5 nm, an effective oxide thickness (EOT) of 1-2.5 nm. The actual desired thickness depends on the power supply (VDD) and the programming voltage (Vpp) requirements. The 2-5 nm range is appropriate for a VDD of 1.0-2.5V. A thickness of less than 2.5 nm typically enables the element to operate in the direct tunneling regime. Alternate embodiments that use other power supply voltages would use different insulator material and thicknesses.
In one embodiment, an SiON tunnel insulator 101 is characterized to have a very low trap density of less than 1×1011, an atomic concentration of nitrogen that is less than or equal to 20%, an atomic oxygen concentration of greater than or equal to 45%, and a refractive index of 1.55 to 1.65. These numbers are for purposes of illustration only.
A charge trapping layer 102 is formed over the tunnel insulator 101. The trapping layer 102 has a high trap density (e.g., 5×1012 to 1×1014). This layer 102 can be comprised of a high dielectric constant (high-K) material (e.g., Al2O3) with high-density metal nano-dots, silicon nano-crystals, a silicon rich insulator, or SiON/Si3N4 having a refractive indices range of 1.75-2.0. A typical thickness range for the trapping layer 102 is 4-6 nm. However, alternate embodiments may have other thickness ranges.
The high-density metal nano-dots embedded into a high dielectric constant insulator material. The embedded metal nano-dots are used as a charge retention layer for the non-volatile memory element. Each metal dot acts as an isolated, one-dimensional, small floating gate. Therefore, even if a charge leakage path exists between one small floating gate and the substrate or the control gate, the remaining nano-dots in the film layer retain the charge.
In one embodiment, the density range of the metal nano-dots in the trapping layer 102 is in the range of 5×1012 to 10×1013 with typical dot sizes in the range of 1-3 nm and spaced greater than 3 nm apart in the high-K dielectric material. Alternate embodiments can use different densities, dot sizes, and spacing.
The metal nano-dot elements can include platinum (Pt), gold (Au), Cobalt (Co), Iridium (Ir), Tungsten (W) or some other metal that provides deep energy electron and hole traps. In one embodiment, the metal nano-dot layer is deposited by sputtering or evaporation at relatively low temperatures.
A charge blocking insulator layer 103 is formed over the charge trapping layer 102. This layer 103 minimizes the programming voltage and field across the dielectric stack.
The blocking layer 103 is a high-K, high band gap dielectric medium that is characterized by a large energy barrier for electrons and holes. This provides a negligible field emission either from the trapping layer or from the metal control gate 105. This layer 103 may be comprised of alumina (Al2O3) having a K=10, hafnia (HfO2) or Zirconia (ZrO2) with a K=20, or Praeseodymium Oxide (Pr2O3) with a K=30. Alternate embodiments using high-K materials can also be used.
A typical thickness for the blocking layer 103 might be 2 times to 10 times the thickness of the tunnel insulator. The actual thickness depends on the design point of the programming voltage and the high threshold target of the bistable element. The physical thickness could vary between 5 and 25 nm.
A layer of tantalum nitride (TaN) 104 is formed over the blocking layer 103. This layer acts as a chemical passivation layer that is chemically inert. It provides protection of the lower layers from impurities imparted by subsequent processing. The layer 104 also acts as an etch stop layer for subsequent etching steps. In one embodiment, the TaN layer 104 is formed to a thickness in the range of 5-10 nm but should be formed sufficiently thin as possible to act effectively as a passivation layer. Alternate embodiments may use other materials, such as titanium nitride (TiN), and different thicknesses for this layer.
A control gate 105 is formed over the TaN layer 104. In one embodiment, the control gate 105 is a heavily doped polysilicon material. Alternate embodiments may use metal gates such as copper, tungsten, or some other metal.
A gate insulator layer 205 is formed over the substrate 200. In one embodiment, the gate insulator 205 is formed of SiON using an atomic layer deposition (ALD) technique to produce a desired thickness, in one embodiment, in the range of 2-5 nm, an effective oxide thickness (EOT) of 1-2.5 nm. The actual desired thickness depends on the power supply (VDD) requirement. The 2-5 nm range is appropriate for a VDD of 1.0-2.5V. A physical thickness of less than 3.0 nm typically enables the element to operate in the direct tunneling regime. Alternate embodiments that use other power supply voltages would use different insulator thicknesses. The fixed threshold element is designed to have a threshold typically around 0.6 V to 1.0 V to reduce stand-by leakage to a minimum.
A layer of tantalum nitride (TaN) 206 is formed over the gate insulator layer 205. This layer 206 acts as a chemical passivation layer that is chemically inert. It provides protection of the lower layers from impurities imparted by subsequent processing. The layer 206 also acts as an etch stop layer for subsequent etching steps. In one embodiment, the TaN layer 206 is formed to a thickness in the range of 5-10 nm but should be formed sufficiently thin as possible to act effectively as a passivation layer. Alternate embodiments may use other materials, such as titanium nitride (TiN), and different thicknesses for this layer.
A control gate 207 is formed over the TaN layer 206. In one embodiment, the control gate 105 is a doped polysilicon material. Alternate embodiments may use a metal gate such as copper, tungsten, or some other metal.
The bistable gate insulator stack of the above embodiments might be comprised of any oxy-nitride tunnel layer 101 (refractive index=1.6, K=5.5), an oxy-nitride trapping layer 102 (refractive index=1.80, K=7), and an alumina charge blocking layer 103 (K=10) with a doped polysilicon gate 105 (alternately, TaN/Polysilicon). As discussed previously, many combinations of trapping layer and charge blocking layer are possible. A bistable gate insulator stack as illustrated in
For two bit operation of the cell, the memory cell would be comprised of two bistable elements such as shown in FIGS. 7 or 8 each representing an appropriate high threshold state. The bistable elements may have the same Al2O3 thicknesses of 12.5 nm yielding a high Vt each of +3.0 V with a programming pulse of +7.5V.
To improve the stability of the high threshold states for the above embodiments, a modified programming scheme can be used. In such a scheme, the programming pulse is comprised of a positive programming pulse of 0.1 ms at Vprog with a −Vdd (power supply) pulse of 1 ms. This programming scheme results in minimizing electron back tunneling from shallow trap centers.
Using the above gate insulator stacks, single bit NOR memory cells can be designed to have characteristics such as (for Vdd=2.5V): Vt-low=1.0V, Vt-high=3.0-4.0V, Vprog≦7.5V with a 0.1 ms pulse and a −2.5V pulse for 1 ms, Verase=−6.0V with a pulse width of 1 ms. A retention time of 10 years is possible with an endurance of 1×1014 cycles. Equivalent characteristics can be achieved for NAND cells with slower access times.
Similarly, the above gate insulator stacks can provide the following characteristics for a two bit NOR cell at the same Vdd=2.5V: Vt-low=1.0V, Vt-high-A=3.0V, Vt-high-B=3.0V, Vprog=7.5V with a 0.1 ms pulse and a −2.5V pulse for 1 ms, Verase=−7.5V with a pulse width of 1 ms. A retention time of 10 years is possible with an endurance of 1×1014 cycles.
The high state of the cell is defined by the high threshold state of the bistable element 310. As shown later in another embodiment, the position of the fixed threshold element and the bistable element (or elements) could be reversed with reference to the source, drain, and channel location. Both elements 310 and 311 are active for cell operation.
The bistable element 310 is comprised of a polysilicon control gate 301. The polysilicon control gate 301 of the bistable element 310 overlaps the polysilicon access gate 302 of the fixed threshold element 311. In the embodiment illustrated in
The fixed threshold element 311 is comprised of an access gate 302 that, in one embodiment, also includes the passivation layer 206 of
The gate insulator stack 321 is formed over a substrate 300 that, in one embodiment, is a p-type silicon material. The substrate includes two source/drain regions 305 and 306 that are doped into the substrate. In the p-type substrate embodiment, the source/drain regions 305 and 306 are n+ regions.
Charge injected from the substrate is stored in the trapping layer (101 of
The architecture of these elements 401 and 402 are substantially similar to that illustrated in
The fixed threshold element 402 of
One of the active regions 521 acts as the drain region and is coupled to the bit line (B/L). The other active region 522 acts as the source region and is coupled to the source line (S/L). The control gates 502 and 503 of each of the bistable elements 510 and 511 are coupled to a single control gate line (CG).
The gate insulator stack for the bistable elements 510 and 511 is illustrated in
The bistable elements 601 and 602 are coupled to a control gate (CG) line. As in previous embodiments, the gate insulator stack for each of the bistable elements 601 and 602 are illustrated in
The logic fixed threshold element 603 is coupled to an access gate (AG) line. As in the previous embodiments, the gate insulator stack for the fixed threshold element is illustrated in
The control gate 920 is also shared between the adjacent cells and resides in a trench while overlapping the two adjacent access gates 910 and 911 that are formed over their respective gate insulator stacks 950 and 951 on the mesas formed by the trench. The access gates control operation of the two respective logic elements that use the gate insulator stack of
The substrate 900 further has two bit lines B/L ‘1’ and B/L ‘2’ that are connected to their respective diffusion regions 902 and 901. In one embodiment, these active regions 901 and 902 are n+ regions in a p-type substrate. However, the present invention is not limited to any one conductivity type. The configuration illustrated in
The tops of each mesa comprises diffusion regions 1015 and 1016 that act as drain regions. These regions 1015 and 1016 are connected to separate bit lines B/L ‘1’ and B/L ‘2’. Buried source lines 1001-1004 are connected together and, in one embodiment, further connected to ground potential.
In one embodiment, the substrate 1000 is a p-type substrate and the active areas 1001-1004, 1015, and 1016 are n+ regions. Alternate embodiments use other conductivity types.
The memory device includes an array of memory cells 1130 that can be comprised of the multi-level DRAM-NVRAM cells previously illustrated. The memory array 1130 is arranged in banks of rows and columns. The gates of each row of memory cells is coupled with a wordline while the drain and source connections of the memory cells are coupled to bit lines.
An address buffer circuit 1140 is provided to latch address signals provided on address input connections A0-Ax 1142. Address signals are received and decoded by a row decoder 1144 and a column decoder 1146 to access the memory array 1130. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 1130. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.
The memory device 1100 reads data in the memory array 1130 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 1150. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 1130. Data input and output buffer circuitry 1160 is included for bi-directional data communication over a plurality of data connections 1162 with the controller 1110. Write circuitry 1155 is provided to write data to the memory array.
Control circuitry 1170 decodes signals provided on control connections 1172 from the processor 1 1 10. These signals are used to control the operations on the memory array 1130, including data read, data write (program), and erase operations. The control circuitry 1170 may be a state machine, a sequencer, or some other type of controller.
The memory device illustrated in
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.
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|U.S. Classification||257/314, 257/E29.309|
|Cooperative Classification||H01L29/42328, H01L29/792, H01L29/7923, H01L29/42336|
|European Classification||H01L29/792, H01L29/423D2B2B, H01L29/423D2B2D, H01L29/792B|
|Dec 21, 2004||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BHATTACHARYYA, ARUP;REEL/FRAME:016119/0208
Effective date: 20041105