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Publication numberUS20060131633 A1
Publication typeApplication
Application numberUS 11/018,131
Publication dateJun 22, 2006
Filing dateDec 21, 2004
Priority dateDec 21, 2004
Also published asUS8242554, US20100038701
Publication number018131, 11018131, US 2006/0131633 A1, US 2006/131633 A1, US 20060131633 A1, US 20060131633A1, US 2006131633 A1, US 2006131633A1, US-A1-20060131633, US-A1-2006131633, US2006/0131633A1, US2006/131633A1, US20060131633 A1, US20060131633A1, US2006131633 A1, US2006131633A1
InventorsArup Bhattacharyya
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated two device non-volatile memory
US 20060131633 A1
Abstract
The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed threshold element by a tunnel insulator over the substrate, a charge trapping layer over the tunnel insulator, a charge blocking layer over the trapping layer, and a control gate, having a nitride layer, over the charge blocking layer. In one embodiment, the gate insulator, tunnel insulator and charge trapping layers are all SiON with thicknesses that depend on the designed programming voltage. The control gate can be formed overlapping the access gate or the access gate can be formed overlapping the control gate.
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Claims(44)
1. A memory cell comprising:
an oxy-nitride tunnel insulator formed over a substrate;
a trapping layer formed over the tunnel insulator;
a charge blocking layer formed over the trapping layer; and
a control gate formed over the charge blocking layer.
2. The cell of claim 1 wherein the control gate is comprised of a polysilicon material formed over a tantalum nitride material.
3. The cell of claim 1 wherein the control gate is comprised of a polysilicon material formed over a titanium nitride material.
4. The cell of claim 1 wherein the tunnel insulator and the trapping layer are comprised of SiON.
5. The cell of claim 4 wherein the tunnel insulator has a dielectric constant of 5.5 and the trapping layer has a dielectric constant of 7.
6. The cell of claim 1 wherein the trapping layer is an oxy-nitride trapping layer.
7. The cell of claim 1 wherein the trapping layer is a high-K dielectric material comprising embedded metal nano-dots.
8. The cell of claim 7 wherein the high-K dielectric material is one of: Al2O3, HfO2, ZrO2, or PrO3.
9. The cell of claim 1 wherein the trapping layer is one of silicon nano-crystals, a silicon rich insulator, or SiON/Si3N4.
10. The cell of claim 7 wherein the embedded metal nano-dots comprise one of:
platinum (Pt), gold (Au), Cobalt (Co), Iridium (Ir), or Tungsten (W).
11. The cell of claim 1 and further including source and drain regions doped into the substrate.
12. An integrated, non-volatile memory cell comprising:
a fixed threshold element comprising:
a gate insulator layer formed over a substrate;
an access gate formed over the gate insulator layer;
a bistable element comprising:
a tunnel insulator layer formed over the substrate;
a charge trapping layer formed over the tunnel insulator layer;
a charge blocking layer formed over the charge trapping layer; and
a control gate formed over the charge blocking layer; and
a source region and a drain region formed in the substrate.
13. The cell of claim 12 wherein the control gate overlaps the access gate.
14. The cell of claim 12 wherein the access gate overlaps the control gate.
15. The cell of claim 12 wherein the fixed threshold element and the bistable element share a drain region and a source region.
16. The cell of claim 12 wherein the access gate is comprised of a layer of tantalum nitride between the gate insulator and a polysilicon material and the control gate is comprised of a layer of tantalum nitride between the charge blocking layer and a polysilicon material.
17. The cell of claim 12 wherein the access gate is comprised of a layer of titanium nitride between the gate insulator and a polysilicon material and the control gate is comprised of a layer of titanium nitride between the charge blocking layer and a polysilicon material.
18. The cell of claim 12 wherein the source and drain regions are n+ regions and the substrate is comprised of p-type material.
19. An integrated, non-volatile memory cell comprising:
a fixed threshold element comprising:
a gate insulator layer formed over a substrate;
an access gate formed over the gate insulator layer;
a first bistable element comprising an ONO-type gate insulator stack and a first control gate;
a second bistable element comprising the ONO-type gate insulator stack and a second control gate; and
a source region and a drain region formed in the substrate.
20. The cell of claim 19 wherein the ONO-type gate insulator stack is comprised of a tunnel insulator formed over the substrate, a trapping layer formed over the tunnel insulator, and a charge blocking layer formed over the trapping layer wherein the tunnel insulator, the trapping layer, and the gate insulator are comprised of SiON.
21. The cell of claim 19 wherein the first and second bistable elements are on opposing sides of the fixed threshold element and each is formed over one of the source or the drain regions.
22. The cell of claim 19 wherein the first bistable element can hold a first charge and the second bistable element can hold a second charge.
23. The cell of claim 19 wherein the first and second control gates are coupled together.
24. The cell of claim 19 wherein the first and second control gates overlap the access gate.
25. Integrated, non-volatile memory cells comprising:
a substrate comprising a trench that is formed between two mesas, the trench comprising opposing sidewalls;
a first ONO-type gate insulator stack formed on a first sidewall;
a second ONO-type gate insulator stack formed on a second, opposing sidewall;
a source region formed in the substrate at the bottom of the trench;
a first fixed threshold element, comprising a first access gate, formed on a first mesa;
a second fixed threshold element, comprising a second access gate, formed on a second mesa;
a first drain region formed in the first mesa;
a second drain region formed in the second mesa; and
a control gate formed in the trench between the opposing sidewalls and over the first and second gate insulator stacks, the control gate overlapping the first and second access gates.
26. The cell of claim 25 wherein the first drain region is coupled to a first bit line and the second drain region is coupled to a second bit line.
27. Integrated, non-volatile memory cells comprising:
a substrate comprising a trench formed between mesas, the trench comprising opposing sidewalls;
a source region formed at each corner of the trench;
a drain region formed at the top of each mesa;
a fixed threshold element formed vertically along each opposing sidewall, each fixed threshold element formed substantially over at least a portion of a nearest drain region and each element comprising an access gate; and
a bistable element formed vertically along each opposing sidewall substantially adjacent to the fixed threshold element along that sidewall, the bistable elements in the trench sharing a common control gate that overlaps the access gates.
28. The cells of claim 27 wherein the source regions are coupled together in a series configuration.
29. The cells of claim 27 wherein the drain regions are coupled to separate bit lines.
30. The cells of claim 27 wherein the bistable elements comprise gate insulator stacks comprising a tunnel dielectric, a charge trapping layer, and a charge blocking layer.
31. An electronic system comprising:
a processor that generates memory control signals; and
a flash memory device coupled to the processor and operating in response to the memory control signals, the memory device comprising a memory array wherein each of a plurality of memory elements of the array is comprised of:
an oxy-nitride tunnel insulator formed over a substrate;
a trapping layer formed over the tunnel insulator;
a charge blocking layer formed over the trapping layer; and
a control gate formed over the charge blocking layer, the control gate comprising a nitride layer.
32. The system of claim 31 wherein the tunnel insulator and the trapping layer are comprised of SiON and the control gate is further comprised of polysilicon over the nitride layer comprising tantalum nitride.
33. The system of claim 31 wherein the tunnel insulator and the trapping layer are comprised of SiON and the control gate is further comprised of polysilicon over the nitride layer comprising titanium nitride.
34. A method for fabricating a bistable memory element, the method comprising:
forming a drain region and a source region in a substrate;
forming a tunnel insulator layer over the substrate;
forming a trapping layer over the tunnel insulator layer;
forming a charge blocking layer over the trapping layer;
forming a nitride layer over the charge blocking layer; and
forming a polysilicon control gate over the nitride layer.
35. The method of claim 34 wherein the nitride layer is one of a tantalum nitride or a titanium nitride.
36. The method of claim 34 wherein both the tunnel insulator layer and the trapping layer are SiON wherein a thickness of the tunnel insulator is in response to a designed programming voltage for the memory element.
37. A method for fabricating a non-volatile memory cell, the method comprising:
forming a fixed threshold element over a substrate, the fixed threshold element comprising:
forming a gate insulator over the substrate; and
forming an access gate over the gate insulator; and
forming a first bistable element over the substrate and substantially adjacent to the fixed threshold element, the first bistable element comprising:
forming a tunnel insulator over the substrate;
forming a trapping layer over the tunnel insulator;
forming a blocking layer over the trapping layer; and
forming a control gate over the blocking layer.
38. The method of claim 37 wherein forming the trapping layer comprises forming a layer of high-K dielectric material with embedded metal nano-dots.
39. The method of claim 37 wherein forming the control gate comprises forming the control gate such that it overlaps the access gate.
40. The method of claim 37 wherein forming the access gate comprises forming the access gate such that it overlaps the control gate.
41. The method of claim 37 and further including forming a second bistable element, having substantially the same fabrication method as the first bistable element, adjacent to and on an opposing side of the fixed threshold element.
42. The method of claim 41 wherein each control gate of the first and second bistable elements overlap the access gate.
43. A method for fabricating a plurality of non-volatile memory cells, the method comprising:
forming a trench in a substrate such that the trench forms a mesa on each side;
forming a source region in the bottom of the trench;
forming a first drain region on a first mesa and a second drain region on a second mesa;
forming a first bistable element on a first sidewall of the trench and a second bistable element on a second sidewall of the trench;
forming a first fixed threshold element on the first mesa and a second fixed threshold element on the second mesa, each fixed threshold element comprising an access gate; and
forming a control gate in the trench between the first and second bistable elements such that the control gate overlaps the access gates of the first and second fixed threshold elements.
44. A method for fabricating a plurality of non-volatile memory cells, the method comprising:
forming a trench in a substrate such that the trench forms a mesa on each side;
forming a source region in each corner of the bottom of the trench such that the resulting plurality of source regions are coupled together in series;
forming a first drain region on a first mesa and a second drain region on a second mesa;
forming a first bistable element on a first sidewall of the trench and a second bistable element on a second sidewall of the trench;
forming a first fixed threshold element on the first sidewall substantially adjacent to the first bistable element and a second fixed threshold element on the second sidewall substantially adjacent to the second bistable element, each fixed threshold element comprising an access gate; and
forming a control gate in the trench between the first and second sidewalls such that the control gate overlaps the access gates of the first and second fixed threshold elements.
Description
TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to memory devices and in particular the present invention relates to non-volatile memory devices

BACKGROUND OF THE INVENTION

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), and flash memory.

Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.

Conventional non-volatile memory cells employ floating gate device technology. A floating gate cell can be programmed by injecting electrons to the silicon floating gate by channel hot carrier injection (CHE) to put the cell into a high threshold state. The cell can be erased by hot hole injection from the substrate plus electron back-tunneling to the substrate by Fowler-Nordheim tunneling to put the cell in a low threshold state. Both mechanisms require high fields across the gate dielectric layers with resulting adverse effects in device characteristics and reliability.

CHE can consume large amounts of power for writing, generates interface states, degrades device transconductance, and enhances back-tunneling that affects charge retention and read-disturb. Fowler-Nordheim tunneling and associated hot-hole injection generates fixed charge centers in tunneling dielectrics and shallow traps and defects in the trapping layer, thus breaking stable bonds and eventually degrading the dielectric properties of the device.

As computers become smaller and their performance increases, the computer memories have also gone through a corresponding size reduction and performance increase. However, flash memory devices present a challenge in scalability due, at least in part, to the high programming voltages typically required. Their performance can also suffer due to the above-discussed limitations.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a more scalable, higher performance non-volatile memory device.

SUMMARY

The above-mentioned problems with scalable memory and other problems are addressed by the present invention and will be understood by reading and studying the following specification.

The present invention encompasses a non-volatile memory cell that has an oxy-nitride tunnel insulator formed over a substrate, a trapping layer formed over the tunnel insulator, a charge blocking layer formed over the trapping layer, and a control gate formed over the charge blocking layer. In one embodiment, both the oxy-nitride tunnel insulator and the trapping layer are formed from SiON and the control gate is comprised of a layer of TiN or TaN between the blocking layer and the polysilicon material.

In another embodiment, a memory cell is comprised of both a fixed threshold element and a bistable element. The fixed threshold element is formed by a gate insulator and control gate having a TiN or TaN layer. The bistable element is comprised of an ONO-type insulator stack such as the SiON insulator acting as tunnel and trapping layers with the charge blocking layer.

Further embodiments of the invention include methods and apparatus of varying scope.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of one embodiment of a gate insulator stack of a bi-stable element of the present invention.

FIG. 2 shows a cross-sectional view of one embodiment of a gate insulator stack of a fixed threshold logic element of the present invention.

FIG. 3 shows an embodiment of a non-volatile memory cell of the present invention.

FIG. 4 shows an alternate embodiment of a non-volatile memory cell of the present invention.

FIG. 5 shows another alternate embodiment of a non-volatile memory cell of the present invention.

FIG. 6 shows another alternate embodiment of a non-volatile memory cell of the present invention.

FIG. 7 shows another alternate embodiment of a non-volatile memory cell of the present invention.

FIG. 8 shows another alternate embodiment of a non-volatile memory cell of the present invention.

FIG. 9 shows another alternate embodiment of a non-volatile memory cell of the present invention.

FIG. 10 shows another alternate embodiment of a non-volatile memory cell of the present invention.

FIG. 11 shows a block diagram of one embodiment of an electronic system of the present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. The terms wafer or substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions.

FIG. 1 illustrates a cross-sectional view of one embodiment of a gate insulator stack of a bi-stable element of the present invention. The stack architecture provides the capability of storing multiple bits per memory element without the need to switch the biasing of the cell's drain and source regions. This is accomplished by varying the trapping density of the trapping layer.

A tunnel insulator layer 101 is formed over the substrate 100 that, in one embodiment, is comprised of p-type silicon. An alternate embodiment may use an n-type material. The substrate 100 has doped regions 110 and 112 that are used as source and drain regions.

In one embodiment, the tunnel insulator 101 is formed from silicon oxynitride (SiON). The SiON provides good back-tunneling characteristics in order to prevent a charge from leaking back to the substrate 100. Alternate embodiments may use other materials such as another oxynitride material or an oxide material. As discussed subsequently, the tunnel insulator 101 is a common element between the bistable element and the fixed threshold element of the present invention.

The tunnel insulator 101 can be formed over the substrate 100 using an atomic layer deposition (ALD) technique to produce a thickness, in one embodiment, in the range of 2-5 nm, an effective oxide thickness (EOT) of 1-2.5 nm. The actual desired thickness depends on the power supply (VDD) and the programming voltage (Vpp) requirements. The 2-5 nm range is appropriate for a VDD of 1.0-2.5V. A thickness of less than 2.5 nm typically enables the element to operate in the direct tunneling regime. Alternate embodiments that use other power supply voltages would use different insulator material and thicknesses.

In one embodiment, an SiON tunnel insulator 101 is characterized to have a very low trap density of less than 11011, an atomic concentration of nitrogen that is less than or equal to 20%, an atomic oxygen concentration of greater than or equal to 45%, and a refractive index of 1.55 to 1.65. These numbers are for purposes of illustration only.

A charge trapping layer 102 is formed over the tunnel insulator 101. The trapping layer 102 has a high trap density (e.g., 51012 to 11014). This layer 102 can be comprised of a high dielectric constant (high-K) material (e.g., Al2O3) with high-density metal nano-dots, silicon nano-crystals, a silicon rich insulator, or SiON/Si3N4 having a refractive indices range of 1.75-2.0. A typical thickness range for the trapping layer 102 is 4-6 nm. However, alternate embodiments may have other thickness ranges.

The high-density metal nano-dots embedded into a high dielectric constant insulator material. The embedded metal nano-dots are used as a charge retention layer for the non-volatile memory element. Each metal dot acts as an isolated, one-dimensional, small floating gate. Therefore, even if a charge leakage path exists between one small floating gate and the substrate or the control gate, the remaining nano-dots in the film layer retain the charge.

In one embodiment, the density range of the metal nano-dots in the trapping layer 102 is in the range of 51012 to 101013 with typical dot sizes in the range of 1-3 nm and spaced greater than 3 nm apart in the high-K dielectric material. Alternate embodiments can use different densities, dot sizes, and spacing.

The metal nano-dot elements can include platinum (Pt), gold (Au), Cobalt (Co), Iridium (Ir), Tungsten (W) or some other metal that provides deep energy electron and hole traps. In one embodiment, the metal nano-dot layer is deposited by sputtering or evaporation at relatively low temperatures.

A charge blocking insulator layer 103 is formed over the charge trapping layer 102. This layer 103 minimizes the programming voltage and field across the dielectric stack.

The blocking layer 103 is a high-K, high band gap dielectric medium that is characterized by a large energy barrier for electrons and holes. This provides a negligible field emission either from the trapping layer or from the metal control gate 105. This layer 103 may be comprised of alumina (Al2O3) having a K=10, hafnia (HfO2) or Zirconia (ZrO2) with a K=20, or Praeseodymium Oxide (Pr2O3) with a K=30. Alternate embodiments using high-K materials can also be used.

A typical thickness for the blocking layer 103 might be 2 times to 10 times the thickness of the tunnel insulator. The actual thickness depends on the design point of the programming voltage and the high threshold target of the bistable element. The physical thickness could vary between 5 and 25 nm.

A layer of tantalum nitride (TaN) 104 is formed over the blocking layer 103. This layer acts as a chemical passivation layer that is chemically inert. It provides protection of the lower layers from impurities imparted by subsequent processing. The layer 104 also acts as an etch stop layer for subsequent etching steps. In one embodiment, the TaN layer 104 is formed to a thickness in the range of 5-10 nm but should be formed sufficiently thin as possible to act effectively as a passivation layer. Alternate embodiments may use other materials, such as titanium nitride (TiN), and different thicknesses for this layer.

A control gate 105 is formed over the TaN layer 104. In one embodiment, the control gate 105 is a heavily doped polysilicon material. Alternate embodiments may use metal gates such as copper, tungsten, or some other metal.

FIG. 2 illustrates a cross-sectional view of one embodiment of a fixed threshold logic element of the present invention. The fixed threshold element is formed over a substrate 200 that, in one embodiment, is comprised of p-type silicon. An alternate embodiment may use an n-type material. The substrate has doped regions 201 and 202 that are used as source and drain regions.

A gate insulator layer 205 is formed over the substrate 200. In one embodiment, the gate insulator 205 is formed of SiON using an atomic layer deposition (ALD) technique to produce a desired thickness, in one embodiment, in the range of 2-5 nm, an effective oxide thickness (EOT) of 1-2.5 nm. The actual desired thickness depends on the power supply (VDD) requirement. The 2-5 nm range is appropriate for a VDD of 1.0-2.5V. A physical thickness of less than 3.0 nm typically enables the element to operate in the direct tunneling regime. Alternate embodiments that use other power supply voltages would use different insulator thicknesses. The fixed threshold element is designed to have a threshold typically around 0.6 V to 1.0 V to reduce stand-by leakage to a minimum.

A layer of tantalum nitride (TaN) 206 is formed over the gate insulator layer 205. This layer 206 acts as a chemical passivation layer that is chemically inert. It provides protection of the lower layers from impurities imparted by subsequent processing. The layer 206 also acts as an etch stop layer for subsequent etching steps. In one embodiment, the TaN layer 206 is formed to a thickness in the range of 5-10 nm but should be formed sufficiently thin as possible to act effectively as a passivation layer. Alternate embodiments may use other materials, such as titanium nitride (TiN), and different thicknesses for this layer.

A control gate 207 is formed over the TaN layer 206. In one embodiment, the control gate 105 is a doped polysilicon material. Alternate embodiments may use a metal gate such as copper, tungsten, or some other metal.

The following FIGS. 3-10 illustrate various embodiments using the bistable and fixed threshold gate stacks illustrated in FIGS. 1 and 2 respectively. These embodiments are for purposes of illustration. The present invention is not limited to any certain configuration.

The bistable gate insulator stack of the above embodiments might be comprised of any oxy-nitride tunnel layer 101 (refractive index=1.6, K=5.5), an oxy-nitride trapping layer 102 (refractive index=1.80, K=7), and an alumina charge blocking layer 103 (K=10) with a doped polysilicon gate 105 (alternately, TaN/Polysilicon). As discussed previously, many combinations of trapping layer and charge blocking layer are possible. A bistable gate insulator stack as illustrated in FIG. 1 with 2.2 nm tunnel layer/5 nm trapping layer SiON/12.5 nm charge blocking Al2O3 would have an EOT≦9.5 nm and a programming/erase voltage of nearly 7.5V to achieve a high state threshold of greater than 3V with <<1 ms pulse width for programming.

For two bit operation of the cell, the memory cell would be comprised of two bistable elements such as shown in FIGS. 7 or 8 each representing an appropriate high threshold state. The bistable elements may have the same Al2O3 thicknesses of 12.5 nm yielding a high Vt each of +3.0 V with a programming pulse of +7.5V.

To improve the stability of the high threshold states for the above embodiments, a modified programming scheme can be used. In such a scheme, the programming pulse is comprised of a positive programming pulse of 0.1 ms at Vprog with a −Vdd (power supply) pulse of 1 ms. This programming scheme results in minimizing electron back tunneling from shallow trap centers.

Using the above gate insulator stacks, single bit NOR memory cells can be designed to have characteristics such as (for Vdd=2.5V): Vt-low=1.0V, Vt-high=3.0-4.0V, Vprog≦7.5V with a 0.1 ms pulse and a −2.5V pulse for 1 ms, Verase=−6.0V with a pulse width of 1 ms. A retention time of 10 years is possible with an endurance of 11014 cycles. Equivalent characteristics can be achieved for NAND cells with slower access times.

Similarly, the above gate insulator stacks can provide the following characteristics for a two bit NOR cell at the same Vdd=2.5V: Vt-low=1.0V, Vt-high-A=3.0V, Vt-high-B=3.0V, Vprog=7.5V with a 0.1 ms pulse and a −2.5V pulse for 1 ms, Verase=−7.5V with a pulse width of 1 ms. A retention time of 10 years is possible with an endurance of 11014 cycles.

FIG. 3 illustrates a cross-sectional view of one embodiment of a conventional, non-volatile memory cell of the present invention. The NOR cell is comprised of a series integration of the fixed threshold element 311 and the bistable element 310 sharing a common source and drain. The threshold of the fixed threshold element 311, in one embodiment, is designed to be equal to or greater than the low threshold state of the bistable element 310 such that the low threshold state for the cell is defined by the threshold of the fixed threshold state. This provides minimum leakage of the cell during stand-by low state and yet is low enough to provide fast read-access speed during addressing of the memory cell.

The high state of the cell is defined by the high threshold state of the bistable element 310. As shown later in another embodiment, the position of the fixed threshold element and the bistable element (or elements) could be reversed with reference to the source, drain, and channel location. Both elements 310 and 311 are active for cell operation.

The bistable element 310 is comprised of a polysilicon control gate 301. The polysilicon control gate 301 of the bistable element 310 overlaps the polysilicon access gate 302 of the fixed threshold element 311. In the embodiment illustrated in FIG. 3, the passivation layer 104 of FIG. 1 is included in the control gate 301. The control gate/passivation layer 301 is formed over the gate insulator stack 320. In one embodiment, this is the bistable gate insulator stack illustrated in FIG. 1. This stack 320 provides ONO-type characteristics for the bistable element 310.

The fixed threshold element 311 is comprised of an access gate 302 that, in one embodiment, also includes the passivation layer 206 of FIG. 2. Thus, the access gate/passivation layer 302 is formed over the gate insulator stack of FIG. 2.

The gate insulator stack 321 is formed over a substrate 300 that, in one embodiment, is a p-type silicon material. The substrate includes two source/drain regions 305 and 306 that are doped into the substrate. In the p-type substrate embodiment, the source/drain regions 305 and 306 are n+ regions.

Charge injected from the substrate is stored in the trapping layer (101 of FIG. 1). During programming, electrons are injected from the substrate either by channel hot electrons (CHE) or by the Fowler-Nordheim tunneling. Erasing can be accomplished by Fowler-Nordheim tunneling by hole injection from the substrate into the trapping layer to compensate the stored negative charge in nitride aided by electron back-tunneling from the trapping sites.

FIG. 4 illustrates an embodiment of a reverse conventional non-volatile memory cell of the present invention. The cell is comprised of a fixed threshold logic element 402 and a bistable element 401.

The architecture of these elements 401 and 402 are substantially similar to that illustrated in FIG. 3. The bistable element 401 comprises the polysilicon control gate that includes the passivation layer. The gate insulator stack 403 of the bistable element is also illustrated in FIG. 1 as being comprised of the tunnel insulator, the trapping layer, and the blocking layer.

The fixed threshold element 402 of FIG. 4 is comprised of the polysilicon access gate with the passivation layer. The gate insulator stack 404 of the fixed threshold element 402 is also illustrated in FIG. 2. The difference between the embodiment of FIG. 4 and that of FIG. 3 is that the access gate overlaps the control gate of the bistable element 401.

FIG. 5 illustrates a non-volatile memory cell with an overlapping bistable element configuration with the center channel 501 defined by the fixed threshold element 512. The control gates 502 and 503 for the bistable elements 510 and 511 wrap over the fixed threshold gate 504 gating the center of the channel region 501.

One of the active regions 521 acts as the drain region and is coupled to the bit line (B/L). The other active region 522 acts as the source region and is coupled to the source line (S/L). The control gates 502 and 503 of each of the bistable elements 510 and 511 are coupled to a single control gate line (CG).

The gate insulator stack for the bistable elements 510 and 511 is illustrated in FIG. 1 where the passivation layer is considered to be part of the control gate. The gate insulator layer for the fixed threshold element is illustrated in FIG. 2.

FIG. 6 illustrates an embodiment for a non-volatile memory cell that is capable of storing two or more data bits. The cell is comprised of two bistable elements 601 and 602 on either side of a fixed threshold logic element 603. One bistable element 602 is formed above the drain region 605 that is coupled to the bit line (B/L). The second bistable element 601 is formed above the source region 606. In one embodiment, bit line and source line operations are reversed to achieve two-bit per cell storage. In another embodiment, the trapping layers of elements 601 and 602 contain a significantly different density of traps such that the elements have different high threshold values for the same programming condition. In such an embodiment, the bit line and source lie operations are not reversed.

The bistable elements 601 and 602 are coupled to a control gate (CG) line. As in previous embodiments, the gate insulator stack for each of the bistable elements 601 and 602 are illustrated in FIG. 1.

The logic fixed threshold element 603 is coupled to an access gate (AG) line. As in the previous embodiments, the gate insulator stack for the fixed threshold element is illustrated in FIG. 2.

FIG. 7 illustrates an embodiment for a non-volatile memory cell that is capable of storing two or more data bits. The cell is comprised of two bistable elements 701 and 702 for storing data. The channel region 700 is tri-gated by the access gate of the fixed threshold element 703 and the control gates of the bistable elements 701 and 702. The two separate independent bistable element control gates are coupled to CG A and CG B lines respectively. The access gate of the fixed threshold logic element is coupled to an access gate AG line. The control gates of bistable elements 701 and 702 wrap over the fixed threshold gate in the non-active region.

FIG. 8 is substantially similar to the embodiment of FIG. 7 except this embodiment does not have the overlapping control gates. Otherwise, the structure and fabrication are the same.

FIG. 9 illustrates an embodiment for a three-dimensional, non-volatile single bit NOR memory cell of the present invention. Two cells are shown in this figure. Each cell has a bistable gate insulator stack 930 and 931, as illustrated in FIG. 1, that are formed in a vertical configuration on the opposing sidewalls of a trench. A buried common source line 903 is shared between the two adjacent cells. In one embodiment, the common source line 903 is grounded.

The control gate 920 is also shared between the adjacent cells and resides in a trench while overlapping the two adjacent access gates 910 and 911 that are formed over their respective gate insulator stacks 950 and 951 on the mesas formed by the trench. The access gates control operation of the two respective logic elements that use the gate insulator stack of FIG. 2.

The substrate 900 further has two bit lines B/L 1 and B/L 2 that are connected to their respective diffusion regions 902 and 901. In one embodiment, these active regions 901 and 902 are n+ regions in a p-type substrate. However, the present invention is not limited to any one conductivity type. The configuration illustrated in FIG. 9 yields a 4 F2 cell.

FIG. 10 illustrates an embodiment for a pair of vertically configured non-volatile memory cells with a shared control gate 1012 that yields another 4 F2 cell. Each bistable element has an insulator stack 1020 and 1021 as illustrated in FIG. 1. The control gates 1030 and 1031 of each bistable element overlap the access gates 1010 and 1011 for the fixed threshold logic elements. These elements are formed vertically in a trench formed between two mesas.

The tops of each mesa comprises diffusion regions 1015 and 1016 that act as drain regions. These regions 1015 and 1016 are connected to separate bit lines B/L 1 and B/L 2. Buried source lines 1001-1004 are connected together and, in one embodiment, further connected to ground potential.

In one embodiment, the substrate 1000 is a p-type substrate and the active areas 1001-1004, 1015, and 1016 are n+ regions. Alternate embodiments use other conductivity types.

FIG. 11 illustrates a functional block diagram of a memory device 1100 that can incorporate the non-volatile memory cells of the present invention. The memory device 1100 is coupled to a processor 1110. The processor 1110 may be a microprocessor or some other type of controlling circuitry. The memory device 1100 and the processor 1110 form part of an electronic system 1120. The memory device 1100 has been simplified to focus on features of the memory that are helpful in understanding the present invention.

The memory device includes an array of memory cells 1130 that can be comprised of the multi-level DRAM-NVRAM cells previously illustrated. The memory array 1130 is arranged in banks of rows and columns. The gates of each row of memory cells is coupled with a wordline while the drain and source connections of the memory cells are coupled to bit lines.

An address buffer circuit 1140 is provided to latch address signals provided on address input connections A0-Ax 1142. Address signals are received and decoded by a row decoder 1144 and a column decoder 1146 to access the memory array 1130. It will be appreciated by those skilled in the art, with the benefit of the present description, that the number of address input connections depends on the density and architecture of the memory array 1130. That is, the number of addresses increases with both increased memory cell counts and increased bank and block counts.

The memory device 1100 reads data in the memory array 1130 by sensing voltage or current changes in the memory array columns using sense/buffer circuitry 1150. The sense/buffer circuitry, in one embodiment, is coupled to read and latch a row of data from the memory array 1130. Data input and output buffer circuitry 1160 is included for bi-directional data communication over a plurality of data connections 1162 with the controller 1110. Write circuitry 1155 is provided to write data to the memory array.

Control circuitry 1170 decodes signals provided on control connections 1172 from the processor 1 1 10. These signals are used to control the operations on the memory array 1130, including data read, data write (program), and erase operations. The control circuitry 1170 may be a state machine, a sequencer, or some other type of controller.

The memory device illustrated in FIG. 11 has been simplified to facilitate a basic understanding of the features of the memory. A more detailed understanding of internal circuitry and functions of memories are known to those skilled in the art.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7403419 *Mar 3, 2006Jul 22, 2008Micron Technology, Inc.Integrated DRAM-NVRAM multi-level memory
US7566618Mar 8, 2007Jul 28, 2009Hynix Semiconductor Inc.Non-volatile memory device having SONOS structure and manufacturing method thereof
US7635630 *May 15, 2008Dec 22, 2009Micron Technology, Inc.Scalable high density non-volatile memory cells in a contactless memory array
US7646056 *Mar 15, 2006Jan 12, 2010Samsung Electronics Co., Ltd.Gate structures of a non-volatile memory device and methods of manufacturing the same
US7700438 *Jan 30, 2006Apr 20, 2010Freescale Semiconductor, Inc.MOS device with nano-crystal gate structure
US7749838Jul 6, 2007Jul 6, 2010Macronix International Co., Ltd.Fabricating method of non-volatile memory cell
US7759715Oct 15, 2007Jul 20, 2010Micron Technology, Inc.Memory cell comprising dynamic random access memory (DRAM) nanoparticles and nonvolatile memory (NVM) nanoparticle
US7898850Oct 12, 2007Mar 1, 2011Micron Technology, Inc.Memory cells, electronic systems, methods of forming memory cells, and methods of programming memory cells
US7928502Mar 2, 2010Apr 19, 2011Freescale Semiconductor, Inc.Transistor devices with nano-crystal gate structures
US7964909Nov 24, 2009Jun 21, 2011Micron Technology, Inc.Scalable high density non-volatile memory cells in a contactless memory array
US8044454Jun 23, 2009Oct 25, 2011Hynix Semiconductor Inc.Non-volatile memory device
US8193568Jun 14, 2010Jun 5, 2012Micron Technology, Inc.Nanocrystal based universal memory cells, and memory cells
US8228743Feb 10, 2011Jul 24, 2012Micron Technology, Inc.Memory cells containing charge-trapping zones
US8330201 *Sep 12, 2007Dec 11, 2012Kabushiki Kaisha ToshibaNon-volatile semiconductor memory using charge-accumulation insulating film
US8350315Aug 18, 2009Jan 8, 2013Samsung Electronics Co., Ltd.Memory devices capable of reducing lateral movement of charges
US8686491Dec 5, 2012Apr 1, 2014Samsung Electronics Co., Ltd.Memory devices capable of reducing lateral movement of charges
US8735958 *Dec 27, 2012May 27, 2014Macronix International Co., Ltd.Multi-layer polysilicon suppression of implant species penetration
US8759896 *Oct 31, 2012Jun 24, 2014Kabushiki Kaisha ToshibaNon-volatile semiconductor memory using charge-accumulation insulating film
US20100210085 *Apr 26, 2010Aug 19, 2010Macronix International Co., Ltd.Method for fabricating non-volatile memory
US20130062686 *Oct 31, 2012Mar 14, 2013Tatsuo ShimizuNon-volatile semiconductor memory using charge-accumulation insulating film
EP1909311A2 *Oct 3, 2007Apr 9, 2008Samsung Electronics Co., Ltd.Charge trap memory device
Classifications
U.S. Classification257/314, 257/E29.309
International ClassificationH01L29/76
Cooperative ClassificationH01L29/42328, H01L29/792, H01L29/7923, H01L29/42336
European ClassificationH01L29/792, H01L29/423D2B2B, H01L29/423D2B2D, H01L29/792B
Legal Events
DateCodeEventDescription
Dec 21, 2004ASAssignment
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BHATTACHARYYA, ARUP;REEL/FRAME:016119/0208
Effective date: 20041105