Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20060152981 A1
Publication typeApplication
Application numberUS 11/311,990
Publication dateJul 13, 2006
Filing dateDec 19, 2005
Priority dateJan 11, 2005
Also published asCN1828511A, CN1828511B, DE102006002526A1, DE102006002526B4, US8159889, US8917565, US9223650, US20090265513, US20120173806, US20150067450, US20160132389
Publication number11311990, 311990, US 2006/0152981 A1, US 2006/152981 A1, US 20060152981 A1, US 20060152981A1, US 2006152981 A1, US 2006152981A1, US-A1-20060152981, US-A1-2006152981, US2006/0152981A1, US2006/152981A1, US20060152981 A1, US20060152981A1, US2006152981 A1, US2006152981A1
InventorsDong-ryul Ryu
Original AssigneeRyu Dong-Ryul
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Solid state disk controller apparatus
US 20060152981 A1
Abstract
A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.
Images(15)
Previous page
Next page
Claims(30)
1. A solid state disk controller apparatus comprising:
a first port:
a second port having a plurality of channels;
a central processing unit connected to a CPU bus;
a buffer memory configured to store data to be transferred from or to one of the first port and the second port;
a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit;
a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory in parallel to the CPU bus; and
a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory in parallel to the CPU bus.
2. The solid state disk controller apparatus of claim 1, wherein the first data transfer block comprises:
a host interface control block connected to the CPU bus and configured to interface with an external host through the first port according to a control of the central processing unit; and
a first FIFO configured to provide a data transfer path between the host interface control block and the buffer controller/arbiter block bypassing the CPU bus.
3. The solid state disk controller apparatus of claim 2, wherein the first port comprises:
a first channel connected to an external host of a serial ATA interface type;
a second channel connected to an external host of a parallel ATA interface type;
a conversion block configured to convert data to be input through the first channel into a serial ATA format and data to be output through the first channel into a parallel ATA format; and
a multiplexer configured to transfer data from the first channel or from the conversion block to the host interface control block, the multiplexer transferring data from the host interface block to either one of the second channel and the conversion block.
4. The solid state disk controller apparatus of claim 3, wherein the first port is configured such that data from the first channel is directly transferred to the host interface control block and such that data from the host interface control block is directly transferred to the external host of the serial ATA interface type through the first channel.
5. The solid state disk controller apparatus of claim 1, wherein the second data transfer block comprises:
a plurality of second FIFOs corresponding to the channels of the second port, respectively; and
a memory interface control block connected to the CPU bus and configured to interface with semiconductor memories through the second port,
wherein the plurality of second FIFOs are configured to provide data transfer paths between the memory interface control block and the buffer controller/arbiter block bypassing the CPU bus.
6. The solid state disk controller apparatus of claim 5, further comprising a plurality of ECC blocks connected to the second FIFOs respectively, the plurality of ECC blocks configured to detect errors of data transferred through the second FIFOs and to generate error correction codes of data transferred to the semiconductor memories.
7. The solid state disk controller apparatus of claim 6, wherein when an error is detected from data transferred through corresponding FIFOs, the ECC blocks are configured to correct erroneous data without interference of the central processing unit.
8. The solid state disk controller apparatus of claim 1, wherein each of the channels of the second port is connected with a plurality of non-volatile memories.
9. The solid state disk controller apparatus of claim 8, wherein the non-volatile memories connected to each channel of the second port are comprised of a non-volatile memory having the same type.
10. The solid state disk controller apparatus of claim 8, wherein the same types of non-volatile memories are connected to each channel of the second port.
11. The solid state disk controller apparatus of claim 8, wherein different types of non-volatile memories are connected to each channel of the second port.
12. The solid state disk controller apparatus of claim 8, wherein the second data transfer block is configured to detect types of non-volatile memories connected to the channels of the second port at power-up and to control read and write operations of the non-volatile memories of each channel according to the detected result.
13. The solid state disk controller apparatus of claim 5, wherein the second data transfer block is configured to control read and write operations of the semiconductor memories connected to the channels of the second port, based on either one of a hardware and software interleave protocol when read and write operations are requested to the channels of the second port.
14. The solid state disk controller apparatus of claim 5, wherein the buffer controller/arbiter block is configured to process data in a round-robin manner when the first and second FIFOs request data process operations.
15. The solid state disk controller apparatus of claim 5, wherein the memory interface control block comprises:
a control logic configured to generate a first clock signal to be transferred to a semiconductor memory through the second port, the semiconductor memory outputting data in synchronization with the first clock signal;
a delay circuit configured to delay the first clock signal and generate a second clock signal; and
a data fetch register configured to fetch the data from the semiconductor memory in synchronization with the second clock signal.
16. The solid state disk controller apparatus of claim 15, wherein a delay time of the delay circuit is determined by delay information from an exterior source.
17. The solid state disk controller apparatus of claim 15, wherein the memory interface control block further comprises a register for storing delay information that is used to determine a delay time of the delay circuit.
18. A solid state disk controller apparatus comprises:
a first port;
a second port having a plurality of channels;
a central processing unit connected to a CPU bus;
a buffer memory configured to store data to be transferred from the second port to the first port or from the first port to the second port;
a host interface control block connected to the first port and the CPU bus and configured to interface with an external host according to a control of the central processing unit;
a buffer controller/arbiter block connected to the CPU bus and configured to control the buffer memory according to a control of the central processing unit;
a first FIFO configured to provide a data transfer path between the host interface control block and the buffer controller/arbiter block;
a memory interface control block connected to the second port and the CPU bus and configured to interface with non-volatile memories according to a control of the central processing unit; and
a plurality of second FIFOs configured to provide data transfer paths between the memory interface control block and the buffer controller/arbiter block.
19. The solid state disk controller apparatus of claim 18, further comprising a plurality of ECC blocks connected to the second FIFOs respectively, the plurality of ECC blocks configured to detect errors of data transferred through corresponding second FIFOs and to generate error correction codes of data transferred to the non-volatile memories.
20. The solid state disk controller apparatus of claim 19, wherein when an error is detected from data transferred through corresponding second FIFOs, the ECC blocks are configured to correct erroneous data without interference of the central processing unit.
21. The solid state disk controller apparatus of claim 18, wherein non-volatile memories connected to each channel of the second port are comprised of non-volatile memories having the same types with each other.
22. The solid state disk controller apparatus of claim 21, wherein the same types of non-volatile memories are connected to each channel of the second port.
23. The solid state disk controller apparatus of claim 18, wherein different types of non-volatile memories are connected to each channel of the second port.
24. The solid state disk controller apparatus of claim 18, wherein the memory interface control block is configured to detect types of non-volatile memories connected to the channels of the second port at power-up and to control read and write operations of the non-volatile memories of each channel according to the detected result.
25. The solid state disk controller apparatus of claim 18, wherein the memory interface control block is configured to control read and write operations of the non-volatile memories connected to the channels of the second port, based on either one of a hardware and software interleave protocol when read and write operations are requested to the channels of the second port.
26. The solid state disk controller apparatus of claim 18, wherein the buffer controller/arbiter block is configured to process data in a round-robin manner when the first and second FIFOs request data process operations.
27. The solid state disk controller apparatus of claim 18, wherein the memory interface control block comprises:
a control logic configured to generate a first clock signal to be transferred to a semiconductor memory through the second port, the semiconductor memory outputting data in synchronization with the first clock signal;
a delay circuit configured to delay the first clock signal and generate a second clock signal; and
a data fetch register configured to fetch the data from the semiconductor memory in synchronization with the second clock signal.
28. The solid state disk controller apparatus of claim 27, wherein a delay time of the delay circuit is determined by delay information from an exterior.
29. The solid state disk controller apparatus of claim 27, wherein the memory interface control block further comprises a register for storing delay information that is used to determine a delay time of the delay circuit.
30. A method of operation of a solid disk controller having a first port, a second port having a plurality of channels, a central processing unit connected to a CPU bus, a buffer memory configured to store data, and a buffer controller/arbiter connected to the CPU bus and configured to control read and write operations of the buffer memory under control of the central processing unit, the method comprising:
transferring data to be stored/read in/from in the buffer memory between the buffer memory and the first port bypassing the CPU bus; and
transferring data to be stored/read in/from in the buffer memory between the buffer memory and the second port bypassing the CPU bus.
Description
  • [0001]
    This application claims priority from Korean Patent Application No. 2005-2611, filed on Jan. 11, 2005, the contents of which are hereby incorporated by reference in their entirety.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention is related to electronic memory devices. In particular, the present invention is related to a solid state disk controller apparatus.
  • BACKGROUND
  • [0003]
    As known in the art, computer systems generally use several types of memory systems. For example, computer systems generally use so-called main memory comprising of semiconductor devices that can be randomly written to and read from with comparable and very fast access times and thus are commonly referred to as random access memories. However, since semiconductor memories are relatively expensive, other higher density and lower cost memories are often used. For example, other memory systems include magnetic disk storage systems. In the case of magnetic disk storage systems, generally, access times are in the order of tens of milliseconds. On the other hand, in the case of main memory, the access times are in the order of hundreds of nanoseconds. Disk storage is used to store large quantities of data which can be sequentially read into main memory as needed. Another type of disk-like storage is solid state disk storage (SSD, also called solid state drive). SSD is a data storage device that uses memory chips, such as SDRAM, to store data, instead of the spinning platters found in conventional hard disk drives.
  • [0004]
    The term “SSD” is used for two different kinds of products. The first type of SSD, based on fast, volatile memory such as SDRAM, is categorized by extremely fast data access and is used primarily to accelerate applications that are contained by the latency of disk drives. Since this SSD uses volatile memory, it typically incorporates internal battery and backup disk systems to ensure data persistence. If power is lost for whatever reason, the battery keeps the unit powered long enough to copy all data from RAM to backup disk. Upon the restoration of power, data is copied back from backup disk to RAM and the SSD resumes normal operation. The first type of SSD is especially useful on a computer which is already has the maximum amount of RAM. The second type of SSD uses flash memory to store data. These products, which have usually the same size as conventional storage, are typically used as low power, rugged replacements for hard drives. To avoid confusion with the first type, these disks are generally referred to as flash disks. The present invention is directed to the second type of SSD.
  • SUMMARY OF THE INVENTION
  • [0005]
    An object of the present invention is to provide a solid state disk controller apparatus capable of transferring data without limitation of a CPU bus speed.
  • [0006]
    In accordance with one aspect of the present invention, a solid state disk controller apparatus is provided which comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; and a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port. A buffer controller/arbiter block can be connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit. A first data transfer block can be connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory in parallel to the CPU bus. A second data transfer block can be connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory in parallel to the CPU bus.
  • [0007]
    Preferably either or both of the first and second data transfer block is/are operative to by pass the CPU bus in the transfer of data between the buffer and memory and the respective first and second ports.
  • [0008]
    The term “block” as used herein refers to electronic circuiting implements the described operations. Such circuitry can be implemented wholly by hand wire circuits, or by a combination of hardware, software and/or firmware.
  • [0009]
    In this embodiment, the first data transfer block can comprise a host interface control block connected to the CPU bus and configured to interface with an external host through the first port according to a control of the central processing unit; and a first FIFO configured to provide a data transfer path between the host interface control block and the buffer controller/arbiter block.
  • [0010]
    In this embodiment, the first port can comprise a first channel connected to an external host of a serial ATA interface type; a second channel connected to an external host of a parallel ATA interface type; a conversion block configured to convert data to be input through the first channel into a serial ATA format and data to be output through the first channel into a parallel ATA format; and a multiplexer configured to transfer data from the first channel or from the conversion block to the host interface control block, the multiplexer transferring data from the host interface block to either one of the second channel and the conversion block.
  • [0011]
    In this embodiment, the first port can be configured such that data from the first channel is directly transferred to the host interface control block and such that data from the host interface control block is directly transferred to the external host of the serial ATA interface type through the first channel.
  • [0012]
    In this embodiment, the second data transfer block can comprise a plurality of second FIFOs corresponding to the channels of the second port, respectively; and a memory interface control block connected to the CPU bus and configured to interface with semiconductor memories through the second port, wherein the plurality of second FIFOs are configured to provide data transfer paths between the memory interface control block and the buffer controller/arbiter block.
  • [0013]
    In this embodiment, the memory device can further comprise a plurality of ECC blocks connected to the second FIFOs respectively, the plurality of ECC blocks configured to detect errors of data transferred through the second FIFOs and to generate error correction codes of data transferred to the semiconductor memories.
  • [0014]
    In this embodiment, when an error is detected from data transferred through corresponding FIFOs, the ECC blocks can be configured to correct erroneous data without interference of the central processing unit.
  • [0015]
    In this embodiment, each of the channels of the second port can be connected with a plurality of non-volatile memories.
  • [0016]
    In this embodiment, the non-volatile memories connected to each channel of the second port can comprise a non-volatile memory having the same type.
  • [0017]
    In this embodiment, either the same types or different types of non-volatile memories can be connected to each channel of the second port.
  • [0018]
    In this embodiment, the second data transfer block can be configured to detect types of non-volatile memories connected to the channels of the second port at power-up and to control read and write operations of the non-volatile memories of each channel according to the detected result.
  • [0019]
    In this embodiment, the second data transfer block can be configured to control read and write operations of the semiconductor memories connected to the channels of the second port, based on either one of hardware and software interleave protocols when read and write operations are requested to the channels of the second port.
  • [0020]
    In this embodiment, the buffer controller/arbiter block can be configured to process data in a round-robin manner when the first and second FIFOs request data process operations.
  • [0021]
    In this embodiment, the memory interface control block can comprise a control logic configured to generate a first clock signal to be transferred to a semiconductor memory through the second port, the semiconductor memory outputting data in synchronization with the first clock signal; a delay circuit configured to delay the first clock signal and generate a second clock signal; and a data fetch register configured to fetch the data from the semiconductor memory in synchronization with the second clock signal.
  • [0022]
    In this embodiment, a delay time of the delay circuit can be determined by delay information from an exterior source.
  • [0023]
    In this embodiment, the memory interface control block can further comprise a register for storing delay information that is used to determine a delay time of the delay circuit.
  • [0024]
    In accordance with another aspect of the present invention, a solid state disk controller apparatus is provided which a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; and a buffer memory configured to store data to be transferred from the second port to the first port or from the first port to the second port. A host interface control block can be connected to the first port and the CPU bus and configured to interface with an external host according to a control of the central processing unit. A buffer controller/arbiter block can be connected to the CPU bus and configured to control the buffer memory according to a control of the central processing unit. A first FIFO can be configured to provide a data transfer path between the host interface control block and the buffer controller/arbiter block. A memory interface control block can be connected to the second port and the CPU bus and configured to interface with non-volatile memories according to a control of the central processing unit. A plurality of second FIFOs can be configured to provide data transfer paths between the memory interface control block and the buffer controller/arbiter block.
  • [0025]
    In this embodiment, the memory device can further comprise a plurality of ECC blocks connected to the second FIFOs respectively, the plurality of ECC blocks configured to detect errors of data transferred through corresponding second FIFOs and to generate error correction codes of data transferred to the non-volatile memories.
  • [0026]
    In this embodiment, when an error is detected from data transferred through corresponding second FIFOs, the ECC blocks can be configured to correct erroneous data without interference of the central processing unit.
  • [0027]
    In this embodiment, non-volatile memories connected to each channel of the second port can comprise non-volatile memories having the same types with each other.
  • [0028]
    In this embodiment, either the same types or different types of non-volatile memories can be connected to each channel of the second port.
  • [0029]
    In this embodiment, the memory interface control block can be configured to detect types of non-volatile memories connected to the channels of the second port at power-up and to control read and write operations of the non-volatile memories of each channel according to the detected result.
  • [0030]
    In this embodiment, the memory interface control block can be configured to control read and write operations of the non-volatile memories connected to the channels of the second port, based on either one of hardware and software interleave protocols when read and write operations are requested to the channels of the second port.
  • [0031]
    In this embodiment, the buffer controller/arbiter block can be configured to process data in a round-robin manner when the first and second FIFOs request data process operations.
  • [0032]
    In this embodiment, the memory interface control block can comprise a control logic configured to generate a first clock signal to be transferred to a semiconductor memory through the second port, the semiconductor memory outputting data in synchronization with the first clock signal; a delay circuit configured to delay the first clock signal and generate a second clock signal; and a data fetch register configured to fetch the data from the semiconductor memory in synchronization with the second clock signal.
  • [0033]
    In this embodiment, a delay time of the delay circuit can be determined by delay information from an exterior source.
  • [0034]
    In this embodiment, the memory interface control block can further comprise a register for storing delay information that is used to determine a delay time of the delay circuit.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0035]
    A more complete appreciation of the present invention, and many of the attendant advantages thereof, will become readily apparent from the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
  • [0036]
    FIG. 1 is a block diagram showing an embodiment of a solid state disk controller apparatus according to the present invention;
  • [0037]
    FIG. 2 is a block diagram showing a bus architecture for connecting a buffer controller/arbiter block and FIFOs in FIG. 1;
  • [0038]
    FIGS. 3A and 3B are timing diagrams for describing operations of a buffer controller/arbiter block and FIFOs;
  • [0039]
    FIG. 4 is a block diagram showing a bus architecture of an ECC block in FIG. 1;
  • [0040]
    FIG. 5 is a timing diagram for describing error detecting and correcting operations of an ECC block in FIG. 1;
  • [0041]
    FIG. 6 is a block diagram showing one of n channels of a flash interface control block in FIG. 1;
  • [0042]
    FIG. 7 to FIG. 9 are timing diagrams for describing a write procedure according to a 4-way interleave protocols;
  • [0043]
    FIG. 10 is a block diagram showing a flash interface control block in FIG. 1;
  • [0044]
    FIG. 11 is a timing diagram showing a fetch clock signal delayed by a delay circuit of a flash interface control block in FIG. 10;
  • [0045]
    FIG. 12 is a block diagram showing memory types connected to channels of a flash interface control block; and
  • [0046]
    FIG. 13 is a block diagram showing another structure of a second channel supported by a solid state controller apparatus according to the present invention.
  • DESCRIPTION OF A PREFERRED EMBODIMENT
  • [0047]
    A preferred embodiment of the invention will be more fully described with reference to the attached drawings.
  • [0048]
    FIG. 1 is a block diagram showing a solid state disk controller apparatus according to a preferred embodiment of the present invention. A solid state disk controller apparatus 1000 comprises a first port (PORT A) and a second port (PORT B). The solid state disk controller apparatus 1000 exchanges data with an external host (not shown) through the first port PORT A. The first port comprises two channels: a parallel AT attachment (PATA) bus 1001 and a serial AT attachment (SATA) bus 1002. The second port PORT B comprises a plurality of channels, each of which is electrically connected to a plurality of non-volatile memories. Herein, the same types of memories are connected to each channel. A non-volatile memory connected to one channel comprises a single-level flash memory, a multi-level flash memory, a OneNAND flash memory (it is a single chip in which a flash memory core and memory control logic are integrated), or the like. For example, single-level flash memories are connected to one channel, multi-level flash memories are connected to another channel, and OneNAND flash memories are connected to the other channel. A SATA interface (in FIG. 1, marked by “SATA I/F”) 1100 is called a device dongle and converts serial/parallel data into parallel/serial data. For example, the SATA interface 1100 receives serial data transferred through a SATA bus 1002 and converts the received serial data into parallel data. The SATA interface 1100 converts parallel data from a multiplexer 1200 into serial data. The multiplexer 1200 transfers parallel data provided through the PATA bus 1001 to the host interface control block 1300. The multiplexer 1200 transfers data from the host interface control block 1300 to the PATA bus 1001 or the SATA interface 1100. It is previously determined whether any one of the PATA bus 1001 and the SATA bus 1002 of the first port is used.
  • [0049]
    Continuing to refer to FIG. 1, the host interface control block 1300 is connected to the PATA bus 1001 (or, called “an internal IDE bus”), the SATA bus 1002, and a CPU bus 1003. The host interface control block 1300 performs an interface operation according to a control of a central processing unit (CPU) 1400. Data to be input/output through the host interface control block 1300 is stored in a buffer memory 1700 through a buffer controller/arbiter block 1600 and a FIFO (L_FIFO) 1500, without passing through the CPU bus 1003. For example, externally input data is stored in the buffer memory 1700 through the host interface control block 1300, the L_FIFO 1500, and the buffer controller/arbiter block 1600 under the control of the CPU 1400. Likewise, stored data in the buffer memory 1700 is output to the exterior through the buffer controller/arbiter block 1600, the L_FIFO 1500, and the host interface control block 1300.
  • [0050]
    A data transfer operation of the solid state disk controller apparatus 1000 can be carried out without using the CPU bus 1003, so that a data transfer speed is not affected by a CPU bus speed.
  • [0051]
    The L_FIFO 1500 is connected between the host interface control block 1300 and the buffer controller/arbiter block 1500. In a case where bandwidths of the internal buses 1004 and 1005 are different from each other, the L_FIFO 1500 is used to temporarily store data that is not processed while data is transferred. The size of the L_FIFO 1500 is determined such that the L_FIFO 1500 is not filled up during a data transfer operation. The host interface control block 1300 comprises a register 1301, in which operating commands and addresses from the exterior are stored. The host interface control block 1300 communicates a write or read operation to the CPU 1400 through the CPU bus 1003 in response to stored information in the register 1301. The CPU 1400 controls the host interface control block 1300 and the buffer controller/arbiter block 1600 based on input information. This will be more fully described below.
  • [0052]
    A flash interface control block 1800 exchanges data with external non-volatile memories through a second port. The flash interface control block 1800 is configured to support the NAND flash memories, the One_NAND flash memories, and multi-level flash memories. The flash interface control block 1800 comprises a predetermined number of channels. A channel can be connected with any of a plurality of non-volatile memories. Channels can be connected with the same types of memories or can be connected with different types of memories. In addition, in a case in which various types of non-volatile memories are connected to the second port, the solid state disk controller apparatus 1000 supports a function for diagnosing types of non-volatile memories, connected to the second port, at booting. This function is easily accomplished by means of a well-known read operation for device ID. When read and program operations are carried out to different channels, the flash interface control block 1800 of the present solid state disk controller apparatus 1000 selectively performs software and hardware interleave operations.
  • [0053]
    Data transferred through the flash interface control block 1800 is stored in the buffer memory 1700 through a FIFO Ri_FIFO (i=0-n) and the buffer controller/arbiter block 1600. Data transferred through the flash interface control block 1800 is stored in the buffer memory 1700 through a FIFO Ri_FIFO (i=0-n) and the buffer controller/arbiter block 1600, without passing through the CPU bus 1003. For example, data input through the second port is stored in the buffer memory 1700 through the flash interface control block 1800, the Ri_FIFO, and the buffer controller/arbiter block 1600 under the control of the CPU 1400. Likewise, stored data in the buffer memory 1700 is transferred to the second port through the buffer controller/arbiter block 1600, the Ri_FIFO, and the flash interface control block 1800 under the control of the CPU 1300. A data transfer operation of the solid state disk controller apparatus 1000 can be carried out without using of the CPU bus 1003, so that its data transfer speed is not affected by the CPU bus speed. The FIFOs R0_FIFO-Rn_FIFO are connected between the flash interface control block 1800 and the buffer controller/arbiter block 1600. In a case in which bandwidths of the internal buses 1006<n:0> and 1007<n:0> are different from each other, the FIFOs R0_FIFO-Rn_FIFO are used to temporarily store data that is not processed while data is transferred. The size of each of the FIFOs R0_FIFO-Rn_FIFO is determined such that each of the FIFOs Ri FIFO is not filled up during a data transfer operation.
  • [0054]
    The buffer controller/arbiter block 1600 is configured to control read and write operations of the buffer memory 1700. For example, the buffer controller/arbiter block 1600 stores data input through the L_FIFO or the Ri_FIFO in the buffer memory 1700. The buffer controller/arbiter block 1600 reads out from the buffer memory 1700 data to be written to a non-volatile memory or to be output to the exterior. The buffer controller/arbiter block 1600 is configured to process data in a round-robin way when data processing requests coincide. In this case, it is preferable to limit the amount of data to be processed at once so that it does not take a long time to process any request. The buffer controller/arbiter block 1600 has enough data processing ability to process simultaneous requests of the FIFOs R0_FIFO-Rn_FIFO. That is, data process capacity is identical to or larger than a total bandwidth (L_FIFO+R0_FIFO+ . . . +Rn_FIFO).
  • [0055]
    Error checking and correction (ECC) blocks 1900_0-1900_n are respectively connected to the FIFOs R0_FIFO-Rn_FIFO which are connected in parallel between the buffer controller/arbiter block 1600 and the flash interface control block 1800. When data is transferred from the flash interface control block 1800 to the buffer memory 1700 through any FIFO (e.g., R0_FIFO), an ECC block 1900_0 corresponding to the R0_FIFO carries out an error detecting operation for data transferred through the R0_FIFO. If an error is detected from the transferred data, the ECC block 1900_0 is configured to request error correction to the buffer controller/arbiter block 1600 and to correct erroneous data in the buffer memory 1700. Each of the ECC blocks 1900_0-1900_n generates ECC data when main data is transferred to the flash interface control block 1800 through a corresponding FIFO. ECC data thus generated is stored in a non-volatile memory, connected to the second port, with the main data under the control of the flash interface control block 1800.
  • [0056]
    The buffer memory 1700 is used to store data to be transferred to the exterior (e.g., an external host or a non-volatile memory). In addition, the buffer memory 1700 is used to store programs operated by the CPU 1400. The buffer memory 1700 preferably consists of SRAM. The buffer memory 1700 can consist of both SRAM for storing data to be transferred to the exterior and SRAM for storing programs and data operated by the CPU 1400. But, it is obvious to one skilled in the art that the type and allocation of buffer memory are not limited to the specific example of this disclosure.
  • [0057]
    The CPU 1400 generates a command by use of values in control registers 1301 and 1801 in the control blocks 1300 and 1800. The CPU 1400 sets the control registers 1301 and 1801 with control information for read and write operations. For example, when a read/write command is received from the exterior, it is stored in the register 1301 of the host interface control block 1300. The host interface control block 1300 informs the CPU 1400 that a read/write command is received, based on the stored command in the register 1301. The CPU 1400 controls the blocks 1300 and 1600 according to a read/write command. In addition, the CPU 1400 stores a read/write command in the register 1801 of the flash interface control block 1800. The flash interface control block 1800 controls a read/write operation of non-volatile memories through the second port based on the stored command in the register 1801.
  • [0058]
    In accordance with this embodiment of the present invention, when a read/write operation for non-volatile memories connected to the second port is required, a data transfer operation is carried out not through the CPU bus 1003 in the solid state disk controller apparatus 1000, but through a FIFO path. That is, data transferring from the first port to the second port (or from the second port to the first port) can be carried out without using the CPU bus 1003, so that a data transfer speed of the present solid state disk controller apparatus 1000 is not affected by a speed of the CPU bus 1003.
  • [0059]
    FIG. 2 is a block diagram showing the bus architecture for connecting a buffer controller/arbiter block and FIFOs in FIG. 1, and FIGS. 3A and 3B are timing diagrams for describing operations of the buffer controller/arbiter block and the FIFOs.
  • [0060]
    Referring to FIG. 2, buffer controller/arbiter block 1600 is configured to acknowledge the data processing request when a data processing operation is requested from FIFOs L_FIFO and R0_FIFO-Rn_FIFO. A bus between the L_FIFO and the buffer controller/arbiter block 1600 is configured to transfer a request signal REQ0, a grant signal GRT0, a read/write distinction signal RW0, an address ADDRESS0, read data RD0, write data WD0, and a data valid interval signal D_VALID0. Likewise, each of buses 1006_0-1006_n between the FIFOs R0_FIFO-Rn_FIFO and the buffer controller/arbiter block 1600 is configured to transfer a request signal REQ1, a grant signal GRT1, a read/write distinction signal RW1, an address ADDRESS1, read data RD1, write data WD1, and a data valid interval signal D_VALID1.
  • [0061]
    In the case of transferring data from the buffer memory 1700 to the L_FIFO, as illustrated in FIG. 3A, the L_FIFO activates a request signal REQ0 for a read operation. At the same time, an address ADDRESS0 of data to be read is transferred from the L_FIFO to the buffer controller/arbiter block 1600. When the request signal REQ0 is activated, the buffer controller/arbiter block 1600 activates the grant signal GRT0 when a previous process is ended. As the data processing request is granted, the L_FIFO sequentially sends addresses to the buffer controller/arbiter block 1600. The buffer controller/arbiter block 1600 reads data from the buffer memory 1700 according to received addresses and outputs the read data to the L_FIFO during activation of a valid data interval signal D_VALID0. At this time, the L_FIFO inactivates the request signal REQ0 when a predetermined amount of data (e.g., eight N-bit data) is received. This inactivation enables the buffer controller/arbiter block 1600 to process the request of another FIFO.
  • [0062]
    In the case of transferring data from the L_FIFO to the buffer memory 1700, as illustrated in FIG. 3B, the L_FIFO activates the request signal REQ0 for a write operation. When the request signal REQ0 is activated, the buffer controller/arbiter block 1600 activates the grant signal GRT0 when a previous process is ended. As the data processing request is granted, the L_FIFO sequentially sends addresses with data to be written to the buffer controller/arbiter block 1600. The buffer controller/arbiter block 1600 writes received data in the buffer memory 1700 according to received addresses. At this time, the L_FIFO inactivates the request signal REQ0 when a predetermined amount of data (e.g., eight N-bit data) is output. This inactivation enables the buffer controller/arbiter block 1600 to process the request of another FIFO.
  • [0063]
    Data transfer from the buffer memory 1700 to a Ri_FIFO via a bus 1006_i is carried out in the same manner as illustrated in FIG. 3A, and data transfer from a Ri_FIFO via a bus 1006_i to the buffer memory 1700 is carried out in the same manner as illustrated in FIG. 3B. Thus, a description of read and write operations related to the FIFOs R0_FIFO-Rn_FIFO is omitted.
  • [0064]
    FIG. 4 is a block diagram showing the bus architecture of an ECC block in FIG. 1, and FIG. 5 is a timing diagram for describing an error detecting and correcting operation of an ECC block.
  • [0065]
    Referring to FIG. 4, an exemplary bus for connecting an ECC block 1900_0 and a R0_FIFO is configured to transfer an ECC request signal ECC_REQ, ECC read/write distinction signal ECC_RW, an ECC address ECC_ADDRESS, ECC remedy data ECC_RMWD, an ECC grant signal ECC_GRT, and ECC read data ECC_RD.
  • [0066]
    Assume that data is transferred to buffer memory 1700 through R0_FIFO. If an error is detected from transferred data, ECC block 1900_0 activates an ECC request signal ECC_REQ, which is transferred to the buffer controller/arbiter block 1600 through the R0_FIFO with an ECC address ADD1 of erroneous data. The buffer controller/arbiter block 1600 activates the grant signal ECC_GRT when the request signal ECC_REQ is received together with the address ADD1. At this time, the ECC read/write distinction signal ECC_RW is maintained high so as to indicate a read operation. When the ECC read/write distinction signal ECC_RW is at a high level, erroneous data is read from the buffer memory 1700 under the control of the buffer controller/arbiter block 1600. The erroneous data ECC_RD thus read is transferred to the ECC block 1900_0 through the R0_FIFO. The erroneous data ECC_RD is corrected by the ECC block 1900_0, and the error-corrected data ECC_RMWD is transferred to the buffer controller/arbiter block 1600 through the R0_FIFO. At this time, the ECC read/write distinction signal ECC_RW goes to a low level indicating a write operation. The buffer controller/arbiter block 1600 stores the error-corrected data ECC_RWMD in the buffer memory 1700 in response to the ECC read/write distinction signal ECC_RW. Afterwards, the buffer controller/arbiter block 1600 inactivates the grant signal ECC_GRT.
  • [0067]
    FIG. 6 is a block diagram showing one of the channels of a flash interface control block in FIG. 1.
  • [0068]
    Referring to FIG. 6, one channel is connected with a plurality of non-volatile memories. In this example, the non-volatile memories consist of NAND flash memories. As well known in the art, the NAND flash memory has a command/address/data multiplexed I/O structure. This means that commands, data, and addresses are provided through input/output pins. Assuming that one channel is connected with four non-volatile memories, it comprises input/output lines 1802 commonly connected to memories M0, M1, M2 and M3, four chip enable signal lines 1803 a-1803 d respectively connected to corresponding memories, and four ready/busy signal lines 1804 a-1804 d respectively connected to corresponding memories. In addition, although not shown in this figure, control signals such as /WE, /RE, CLE, ALE, etc. are commonly provided to the memories M0-M3.
  • [0069]
    Assume that four flash memories M0-M3 are connected to one channel. Under this assumption, write operations of hardware and software interleave protocols will be more fully described below. In order to perform a write operation, a CPU 1400 stores a write command in a register 1801 of a flash interface control block 1800 through a CPU bus 1003 (see FIG. 1). The flash interface control block 1800 performs a write operation for flash memories in response to the stored write command in the register 1801. In the case of the above-described channel structure, if the number of sectors to be written is over 2, write operations for flash memories are preferably carried out according to hardware and software interleave protocols. Firstly, a write operation of the hardware interleave protocol will be described with reference to FIG. 7. A timing diagram for describing a write procedure according to 4-way interleaving is illustrated in FIG. 7.
  • [0070]
    Referring to FIG. 7, once a write command for any channel is written in the register 1801 of the flash interface control block 1800 by the CPU 1400, the flash interface control block 1800 continuously transfers data to be programmed to flash memories M0-M3 without intervention of the CPU 1400. For example, data to be programmed is continuously transferred to the flash memory M0 through a channel (that is, input/output lines) 1802 following a command and an address, and the transferred data is programmed in a memory cell array of the flash memory M0 during a predetermined time tPROG(M0). While a write operation for the flash memory M0 is carried out, as illustrated in FIG. 7, the flash interface control block 1800 transfers data to be programmed to the flash memory M1 through the channel (that is, input/output lines) 1802. Likewise, data to be programmed in the flash memories M2 and M3 is transferred in the same manner as described above. Accordingly, the channel is occupied by each of the flash memories M0-M3 during transferring of commands, addresses and data. In addition, the channel is occupied by each flash memory during a status read period for judging whether a write operation is passed or failed. Once all data is programmed, the flash interface control block 1800 informs the CPU 1400 that a write operation is ended. Data to be programmed in flash memories commonly connected to the channel is data read out from the buffer memory 1700.
  • [0071]
    Below, a write operation of a software interleave protocol will be described with reference to FIG. 8. FIG. 8 is a timing diagram for describing a write operation according to 4-way interleaving under the assumption that a program time of a flash memory is maintained constant.
  • [0072]
    Referring to FIG. 8, once a write command for any channel is written in the register 1801 of the flash interface control block 1800 by the CPU 1400, the flash interface control block 1800 controls write operations of flash memories M0-M3 according to a control of the CPU 1400. For example, data WD0 to be programmed is sequentially transferred to the flash memory M0 through a channel (that is, input/output lines) 1802 following a command and an address. Once the data WD0 is transferred to the flash memory M0, the flash interface control block 1800 informs the CPU 1400 that transferring of data to the flash memory M0 is ended. The CPU 1400 stores in the register 1801 a write command together with information of a channel where program data is transferred. These steps (in FIG. 8, a period marked by ‘a’) are carried out within a period tPROG where data WD0 transferred to the flash memory M0 is programmed. If a write command is again written in the register 1801, the flash interface control block 1800 sequentially transfers program data WD1 to the flash memory M1 through a channel (that is, input/output lines) following a command and an address. Likewise, transferring of data to flash memories M2 and M3 is carried out in the same manner as described above, and description thereof is thus omitted.
  • [0073]
    Like the hardware interleave protocol, the channel is occupied sequentially by each flash memory during a period in which a command, an address and data are transferred. In addition, the channel is occupied by each flash memory during a status read period for judging whether a write operation is passed or failed.
  • [0074]
    Unlike the above assumption that a program time of a flash memory is maintained constant, the program time tPROG of a flash memory is not maintained constant. That is, since program times of flash memories can be different, as illustrated in FIG. 9, time loss occurs during a write operation of the software interleave protocol.
  • [0075]
    FIG. 10 is a block diagram showing a flash interface control block in FIG. 1.
  • [0076]
    As well know, data is transferred to a flash interface control block 1800 from a flash memory using a control signal such as REB. In this case, transferring of data to the flash interface control block 1800 from the flash memory is affected by line loading of input/output lines or flight time. That is, as illustrated in FIG. 10, a time for transferring data at a point A to a point A′ is varied according to system configuration. In order to overcome this variation, it is preferable to adjust a fetch time of a fetch clock signal F_CLK for determining a data fetch timing of an internal data fetch register 1810. A delay circuit 1820 generates the fetch clock signal F_CLK in response to an REB signal applied to a flash memory, and the fetch clock signal F_CLK is applied to a data fetch register 1810. In particular, a delay time of the delay circuit 1820 is adjusted by a value set in a register 1830 of the flash interface control block 1800 or by a value applied through an external pad 1840. As illustrated in FIG. 11, data, which is at a point A and output in synchronization with the REB signal, reaches point A′ after a delay time Δt. Accordingly, it is possible to stably fetch data transferred from a flash memory by delaying the REB signal by Δt and generating the fetch clock signal F_CLK.
  • [0077]
    FIG. 12 is a block diagram showing memory types that are capable of being connected to channels of a flash interface control block.
  • [0078]
    Referring to FIG. 12, one channel CH. 1 is commonly connected with NAND flash memories where 1-bit data is stored in each cell, another channel CH. 2 is commonly connected with NAND flash memories where N-bit data is stored in each cell, and the other channel CH. n is commonly connected with OneNAND flash memories. But, it is readily apparent that different types of non-volatile memories can be connected to each channel.
  • [0079]
    FIG. 13 is a block diagram showing another structure of a second channel supported by the solid state disk controller apparatus 1000.
  • [0080]
    Referring to FIG. 13, a flash memory having an input/output bit organization of 16 is configured by parallel connecting two flash memories (chip 1 and chip 2) each having an input/output bit organization of 8. In accordance with this channel structure, it is possible to double the number of flash memories and a storage capability. One of two chips uses input/output lines IO[7:0], and the other uses input/output lines IO[15:8]. In this case, all control signals are shared by the chips.
  • [0081]
    As above described, as a data transfer operation of the solid state disk controller apparatus 1000 is carried out not through a CPU bus but through a FIFO path, a data transfer speed of the solid state disk controller apparatus is not affected by a CPU bus speed.
  • [0082]
    The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5459850 *Feb 19, 1993Oct 17, 1995Conner Peripherals, Inc.Flash solid state drive that emulates a disk drive and stores variable length and fixed lenth data blocks
US5822781 *Oct 30, 1992Oct 13, 1998Intel CorporationSector-based storage device emulator having variable-sized sector
US5917538 *May 22, 1998Jun 29, 1999Sony CorporationData Transmission apparatus of video-on-demand or near video-on-demand system
US5969897 *Apr 27, 1998Oct 19, 1999Sony CorporationData recording apparatus and method
US6069827 *Mar 24, 1998May 30, 2000Memory Corporation PlcMemory system
US6360293 *Jun 24, 1999Mar 19, 2002Oki Electric Industry Co., Ltd.Solid state disk system having electrically erasable and programmable read only memory
US6401149 *Apr 12, 2000Jun 4, 2002Qlogic CorporationMethods for context switching within a disk controller
US6851069 *Mar 30, 2000Feb 1, 2005Intel CorporationMethod, apparatus, and system for high speed data transfer using programmable DLL without using strobes for reads and writes
US6874039 *Sep 7, 2001Mar 29, 2005Intel CorporationMethod and apparatus for distributed direct memory access for systems on chip
US20010017076 *Jan 30, 2001Aug 30, 2001Yoshio FujitaApparatus and method for reproducing or recording, via buffer memory, sample data supplied from storage device
US20020038393 *Sep 7, 2001Mar 28, 2002Kumar GanapathyMethod and apparatus for distributed direct memory access for systems on chip
US20030028704 *Dec 5, 2001Feb 6, 2003Naoki MukaidaMemory controller, flash memory system having memory controller and method for controlling flash memory device
US20030065899 *Sep 27, 2002Apr 3, 2003Gorobets Sergey AnatolievichMemory system sectors
US20030123287 *Sep 27, 2002Jul 3, 2003Gorobets Sergey AnatolievichNon-volatile memory control
US20040103242 *Feb 25, 2003May 27, 2004Power Quotient International Co., Ltd.Solid state disk on module with high speed data transmission
US20040153597 *Mar 20, 2002Aug 5, 2004Toshinobu KanaiCommunication control semiconductor device and interface system
US20050162990 *Dec 1, 2004Jul 28, 2005Morihiro MurataOptical disk apparatus with multiple reproduction/record units for parallel operation
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7729167Nov 10, 2008Jun 1, 2010Micron Technology, Inc.Programming a memory with varying bits per cell
US8019938Dec 6, 2007Sep 13, 2011Fusion-I0, Inc.Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage
US8041862 *Aug 24, 2010Oct 18, 2011Quantum CorporationData flow control and bridging architecture enhancing performance of removable data storage systems
US8102706Apr 29, 2010Jan 24, 2012Micron Technology, Inc.Programming a memory with varying bits per cell
US8125827Jun 24, 2009Feb 28, 2012Samsung Electronics Co., Ltd.Flash memory systems and operating methods using adaptive read voltage levels
US8154924Jul 21, 2009Apr 10, 2012Samsung Electronics Co., Ltd.Nonvolatile memory device and read method
US8189407Dec 29, 2010May 29, 2012Fusion-Io, Inc.Apparatus, system, and method for biasing data in a solid-state storage device
US8254181Oct 19, 2009Aug 28, 2012Samsung Electronics Co., Ltd.Nonvolatile memory device and programming method
US8266496Dec 6, 2007Sep 11, 2012Fusion-10, Inc.Apparatus, system, and method for managing data using a data pipeline
US8281044Aug 22, 2011Oct 2, 2012Quantum CorporationData flow control and bridging architecture enhancing performance of removable data storage systems
US8285917 *Mar 26, 2009Oct 9, 2012Scaleo ChipApparatus for enhancing flash memory access
US8285927Aug 5, 2011Oct 9, 2012Fusion-Io, Inc.Apparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage
US8316277Apr 5, 2008Nov 20, 2012Fusion-Io, Inc.Apparatus, system, and method for ensuring data validity in a data storage process
US8341338May 3, 2010Dec 25, 2012Samsung Electronics Co., Ltd.Data storage device and related method of operation
US8386650Dec 16, 2009Feb 26, 2013Intel CorporationMethod to improve a solid state disk performance by using a programmable bus arbiter
US8443134Sep 17, 2010May 14, 2013Fusion-Io, Inc.Apparatus, system, and method for graceful cache device degradation
US8482993May 1, 2012Jul 9, 2013Fusion-Io, Inc.Apparatus, system, and method for managing data in a solid-state storage device
US8489817Aug 12, 2011Jul 16, 2013Fusion-Io, Inc.Apparatus, system, and method for caching data
US8533569Aug 30, 2012Sep 10, 2013Fusion-Io, Inc.Apparatus, system, and method for managing data using a data pipeline
US8555000 *Apr 16, 2010Oct 8, 2013Samsung Electronics Co., Ltd.Data storage device and data storing method thereof
US8601200Oct 30, 2009Dec 3, 2013Ocz Technology Group Inc.Controller for solid state disk which controls access to memory bank
US8626996Oct 9, 2012Jan 7, 2014Samsung Electronics Co., Ltd.Solid state memory (SSM), computer system including an SSM, and method of operating an SSM
US8683293Dec 16, 2009Mar 25, 2014Nvidia CorporationMethod and system for fast two bit error correction
US8689079Dec 21, 2011Apr 1, 2014Kabushiki Kaisha ToshibaMemory device having multiple channels and method for accessing memory in the same
US8694750Dec 19, 2008Apr 8, 2014Nvidia CorporationMethod and system for data structure management
US8706926Oct 15, 2009Apr 22, 2014Marvell World Trade Ltd.Architecture for data storage systems
US8706968Jul 30, 2010Apr 22, 2014Fusion-Io, Inc.Apparatus, system, and method for redundant write caching
US8719501Sep 8, 2010May 6, 2014Fusion-IoApparatus, system, and method for caching data on a solid-state storage device
US8732350Dec 19, 2008May 20, 2014Nvidia CorporationMethod and system for improving direct memory access offload
US8756375Jun 29, 2013Jun 17, 2014Fusion-Io, Inc.Non-volatile cache
US8825937Feb 25, 2013Sep 2, 2014Fusion-Io, Inc.Writing cached data forward on read
US8839024 *Jul 22, 2011Sep 16, 2014Taejin Info Tech Co., Ltd.Semiconductor storage device-based data restoration
US8874823Feb 15, 2011Oct 28, 2014Intellectual Property Holdings 2 LlcSystems and methods for managing data input/output operations
US8874934Feb 24, 2010Oct 28, 2014Samsung Electronics Co., Ltd.Nonvolatile memory device and operating method
US8918595Apr 28, 2011Dec 23, 2014Seagate Technology LlcEnforcing system intentions during memory scheduling
US8954817Nov 30, 2012Feb 10, 2015Kabushiki Kaisha ToshibaStorage apparatus and controller
US8966184Jan 31, 2012Feb 24, 2015Intelligent Intellectual Property Holdings 2, LLC.Apparatus, system, and method for managing eviction of data
US9003104Nov 2, 2011Apr 7, 2015Intelligent Intellectual Property Holdings 2 LlcSystems and methods for a file-level cache
US9058123Apr 25, 2014Jun 16, 2015Intelligent Intellectual Property Holdings 2 LlcSystems, methods, and interfaces for adaptive persistence
US9064059 *Nov 3, 2009Jun 23, 2015OCZ Storage Solutions Inc.Controller for solid state disk, which controls simultaneous switching of pads
US9092337Jan 31, 2012Jul 28, 2015Intelligent Intellectual Property Holdings 2 LlcApparatus, system, and method for managing eviction of data
US9104599Apr 15, 2011Aug 11, 2015Intelligent Intellectual Property Holdings 2 LlcApparatus, system, and method for destaging cached data
US9116812Jan 25, 2013Aug 25, 2015Intelligent Intellectual Property Holdings 2 LlcSystems and methods for a de-duplication cache
US9116823Mar 14, 2013Aug 25, 2015Intelligent Intellectual Property Holdings 2 LlcSystems and methods for adaptive error-correction coding
US9141527Feb 27, 2012Sep 22, 2015Intelligent Intellectual Property Holdings 2 LlcManaging cache pools
US9170754Apr 25, 2012Oct 27, 2015Intelligent Intellectual Property Holdings 2 LlcApparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US9189383Sep 14, 2009Nov 17, 2015Samsung Electronics Co., Ltd.Nonvolatile memory system and data processing method
US9201677Jul 27, 2011Dec 1, 2015Intelligent Intellectual Property Holdings 2 LlcManaging data input/output operations
US9208079May 20, 2015Dec 8, 2015Samsung Electronics Co., Ltd.Solid state memory (SSM), computer system including an SSM, and method of operating an SSM
US9208108 *Dec 19, 2008Dec 8, 2015Nvidia CorporationMethod and system for improved flash controller commands selection
US9251052Feb 22, 2013Feb 2, 2016Intelligent Intellectual Property Holdings 2 LlcSystems and methods for profiling a non-volatile cache having a logical-to-physical translation layer
US9251086Jan 24, 2012Feb 2, 2016SanDisk Technologies, Inc.Apparatus, system, and method for managing a cache
US9304691Mar 9, 2015Apr 5, 2016Kabushiki Kaisha ToshibaMemory system and bank interleaving method
US9454492Dec 28, 2012Sep 27, 2016Longitude Enterprise Flash S.A.R.L.Systems and methods for storage parallelism
US9465728Nov 3, 2010Oct 11, 2016Nvidia CorporationMemory controller adaptable to multiple memory devices
US9495241Mar 4, 2013Nov 15, 2016Longitude Enterprise Flash S.A.R.L.Systems and methods for adaptive data storage
US9519540Jan 24, 2012Dec 13, 2016Sandisk Technologies LlcApparatus, system, and method for destaging cached data
US9519594Oct 9, 2012Dec 13, 2016Sandisk Technologies LlcApparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage
US9575902Dec 6, 2007Feb 21, 2017Longitude Enterprise Flash S.A.R.L.Apparatus, system, and method for managing commands of solid-state storage using bank interleave
US9594675Dec 31, 2009Mar 14, 2017Nvidia CorporationVirtualization of chip enables
US9600184Sep 25, 2015Mar 21, 2017Sandisk Technologies LlcApparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment
US9612966Jul 3, 2012Apr 4, 2017Sandisk Technologies LlcSystems, methods and apparatus for a virtual machine cache
US9639324Apr 21, 2014May 2, 2017Marvell World Trade Ltd.Architecture for writing and reading data in a data storage system
US20070299994 *Jun 21, 2006Dec 27, 2007Broadcom Corporation, A California CorporationDisk controller, host interface module and methods for use therewith
US20080141043 *Dec 6, 2007Jun 12, 2008David FlynnApparatus, system, and method for managing data using a data pipeline
US20090049234 *Jan 17, 2008Feb 19, 2009Samsung Electronics Co., Ltd.Solid state memory (ssm), computer system including an ssm, and method of operating an ssm
US20090067240 *Nov 10, 2008Mar 12, 2009Micron Technology, Inc.Programming a memory with varying bits per cell
US20090132760 *Dec 6, 2007May 21, 2009David FlynnApparatus, system, and method for solid-state storage as cache for high-capacity, non-volatile storage
US20100020611 *Jun 24, 2009Jan 28, 2010Park KitaeFlash memory systems and operating methods using adaptive read voltage levels
US20100039861 *Jul 21, 2009Feb 18, 2010Samsung Electronics Co., Ltd.Nonvolatile memory device and read method
US20100082995 *Sep 30, 2008Apr 1, 2010Brian DeesMethods to communicate a timestamp to a storage system
US20100088463 *Sep 14, 2009Apr 8, 2010Samsung Electronics Co., Ltd.Nonvolatile memory system and data processing method
US20100091399 *Oct 15, 2009Apr 15, 2010Tony YoonArchitecture for data storage systems
US20100115153 *Feb 19, 2009May 6, 2010Industrial Technology Research InstituteAdaptive multi-channel controller and method for storage device
US20100128532 *Oct 19, 2009May 27, 2010Samsung Electronics Co., Ltd.Nonvolatile memory device and programming method
US20100161845 *Dec 19, 2008Jun 24, 2010Nvidia CorporationMethod and system for improving direct memory access offload
US20100161876 *Dec 19, 2008Jun 24, 2010Nvidia CorporationMethod and system for data structure management
US20100161941 *Dec 19, 2008Jun 24, 2010Nvidia CorporationMethod and system for improved flash controller commands selection
US20100199025 *Sep 14, 2009Aug 5, 2010Kabushiki Kaisha ToshibaMemory system and interleaving control method of memory system
US20100220525 *Feb 9, 2010Sep 2, 2010Dong Kyu YounNon-volatile memory device and erase and read methods thereof
US20100229001 *Feb 24, 2010Sep 9, 2010Samsung Electronics Co., Ltd.Nonvolatile memory device and operating method
US20100229007 *Feb 24, 2010Sep 9, 2010Junghoon ParkNonvolatile Memory Device and Operating Method Thereof
US20100246261 *Apr 29, 2010Sep 30, 2010Micron Technology, Inc.Programming a memory with varying bits per cell
US20100250827 *Mar 26, 2009Sep 30, 2010Scaleo ChipApparatus for Enhancing Flash Memory Access
US20100287333 *May 3, 2010Nov 11, 2010Samsung Electronics Co., Ltd.Data storage device and related method of operation
US20100318698 *Aug 24, 2010Dec 16, 2010Quantum CorporationData Flow Control and Bridging Architecture Enhancing Performance of Removable Data Storage Systems
US20110093659 *Apr 16, 2010Apr 21, 2011Samsung Electronics Co., Ltd.Data storage device and data storing method thereof
US20110138115 *Feb 15, 2011Jun 9, 2011Samsung Electronics Co., Ltd.Solid state memory (ssm), computer system including an ssm, and method of operating an ssm
US20110145478 *Dec 16, 2009Jun 16, 2011Mangold Richard PMethod to improve a solid state disk performance by using a programmable bus arbiter
US20110145677 *Dec 16, 2009Jun 16, 2011Nvidia CorporationMethod and system for fast two bit error correction
US20110161553 *Dec 30, 2009Jun 30, 2011Nvidia CorporationMemory device wear-leveling techniques
US20110161561 *Dec 31, 2009Jun 30, 2011Nvidia CorporationVirtualization of chip enables
US20110289262 *Nov 3, 2009Nov 24, 2011Indilinx Co., Ltd.Controller for solid state disk, which controls simultaneous switching of pads
US20120260028 *Jan 12, 2011Oct 11, 2012Novachips Co., Ltd.Semiconductor memory system having semiconductor memory devices of various types and a control method for the same
US20130024594 *Jul 22, 2011Jan 24, 2013Byungcheol ChoSemiconductor storage device-based data restoration
US20140301384 *Apr 5, 2013Oct 9, 2014Honeywell International Inc.Integrated avionics systems and methods
DE102008036822A1Aug 6, 2008Apr 2, 2009Samsung Electronics Co., Ltd., SuwonVerfahren zum Speichern von Daten in einem Solid-State-Speicher, Solid-State-Speichersystem und Computersystem
DE102008057219A1Nov 6, 2008Jul 30, 2009Samsung Electronics Co., Ltd., SuwonVerfahren zum Betreiben eines Solid-State-Speichersystems, Solid-State-Speichersystem und Computersystem
EP2183745A2 *Aug 5, 2008May 12, 2010Intel CorporationEcc functional block placement in a multi-channel mass storage device
EP2183745A4 *Aug 5, 2008Apr 9, 2014Intel CorpEcc functional block placement in a multi-channel mass storage device
WO2008070796A2 *Dec 6, 2007Jun 12, 2008Fusion Multisystems, Inc. (Dba Fusion-Io)Apparatus, system, and method for managing data using a data pipeline
WO2008070796A3 *Dec 6, 2007Dec 10, 2009Fusion Multisystems, Inc. (Dba Fusion-Io)Apparatus, system, and method for managing data using a data pipeline
WO2008157141A1 *Jun 11, 2008Dec 24, 2008Micron Technology, Inc.Programming a memory with varying bits per cell
WO2009020969A2Aug 5, 2008Feb 12, 2009Intel CorporationEcc functional block placement in a multi-channel mass storage device
WO2010056003A3 *Oct 30, 2009Aug 5, 2010(주)인디링스Controller for solid state disk which controls access to memory bank
Classifications
U.S. Classification365/194
International ClassificationG11C7/00
Cooperative ClassificationG06F3/0688, G06F3/064, G11C29/52, G06F3/0659, G06F11/1068, G06F3/0619, G06F11/1008, G06F3/0679
European ClassificationG06F11/10R, G06F3/06A2R6, G06F3/06A6L2F, G06F3/06A4T6, G06F11/10M
Legal Events
DateCodeEventDescription
May 16, 2006ASAssignment
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RYU, DONG-RYUL;REEL/FRAME:017625/0194
Effective date: 20051206