US 20060160353 A1
Damascene stacks for use in semiconductor devices and methods for making such stacks are disclosed. An example damascene stack includes a substantially planar lower liner layer and a patterned sacrificial dielectric layer disposed on top of the lower liner layer, where the patterned sacrificial dielectric layer includes an interconnect structure of the damascene stack. The example damascene stack further includes a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, where the upper liner layer being formed of a material that is resistant to etching by a first etch compound. There is at least one plug-hole in the upper liner layer, where the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound. The example damascene stack still further includes at least one air gap formed by removing at least a portion of the sacrificial dielectric layer through the at least one plug-hole in said upper liner layer.
24. A damascene stack for use in a semiconductor device, the damascene stack comprising:
a substantially planar lower liner layer;
a patterned sacrificial dielectric layer disposed on top of the lower liner layer, the patterned sacrificial dielectric layer including an interconnect structure of the damascene stack;
a substantially planar upper liner layer disposed on top of the patterned sacrificial dielectric layer, the upper liner layer being formed of a material that is resistant to etching by a first etch compound;
at least one plug-hole in the upper liner layer, wherein the at least one plug-hole is (i) adjacent to the interconnect structure and (ii) formed by locally converting a portion of the upper liner layer to be etchable by the first etch compound and removing the locally converted portion of the upper liner layer using the first etch compound; and
at least one air gap formed by removing at least a portion of the sacrificial dielectric layer through the at least one plug-hole in the upper liner layer.
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This application claims benefit, under 35 U.S.C. § 119(e), of U.S. Provisional Patent Application 60/507,584, which was filed on Sep. 30, 2003. This application also claims priority to European Patent Application EP 03447239.9, filed on Sep. 30, 2003. The entire disclosures of U.S. Provisional Application 60/507,584 and European Application EP 03447239.9 are incorporated herein by reference.
This invention is related to the field of semiconductor processing and, more specifically, to the production of micro and nano-electromechanical systems (MEMS, NEMS) and low dielectric constant isolation for interconnects.
Airgaps are currently employed in semiconductor devices, such as integrated circuit (IC) devices as both structural or functional (e.g., circuit) element. Also, airgaps in the form of cavities may be present in MEMS and NEMS devices. The use of airgaps is considered to be very promising in the technology area of circuit interconnects, where airgaps may be used as a dielectric for isolation of such interconnects. As the geometries of IC technologies scale down, interconnects are becoming one of the major limiting factors of improved signal propagation delay times, reduced dynamic power consumption and reduction of signal errors resulting from cross-talk effects between adjacent metal lines. Some improvement has been realized by the semiconductor industry's transition from the use of aluminum to the use copper as an interconnect material. This has change has resulted in a reduction in the resistance of IC interconnects, and thus improvements in propagation delays and reductions in dynamic power consumption.
A current focus in the semiconductor industry is to achieve better isolation between the interconnect lines through the introduction of materials with lower dielectric constant than that of silicon oxide (K=4.2) in order to reduce the capacitance (C) between lines. However, the integration of low-k materials (k<3.0) into IC production processes creates a number of challenges associated with leakage, mechanical instability and joule heating, increasing the overall cost of future IC processes. Additionally, the barrier and intermediate layers that employed in such processes tend to increase the effective permittivity of the final stack, which is undesirable from a circuit performance standpoint.
The dielectric and electrical insulation properties of air makes the integration of airgaps as isolation between metal interconnect lines in IC device desirable in order to address some of the concerns discussed above. In fact, the approach of using of air as a dielectric to isolate electrical interconnects has been employed to reduce resistive-capacitive (RC) delay, as well as to reduce dynamic power consumption and signal errors (e.g. due to cross-talk between adjacent metal lines).
One approach that has been used to introduce air cavities into IC devices involves isotropic etching of a device. Such a process has been employed in the production of MEMS devices. This approach includes using hydrofluoric acid (HF) to dissolve a sacrificial SiO2 layer. In such a technique, a film that is relatively non-reactive with HF (e.g., SiC) is employed as an etch stop. The etch source is then sealed by a non-conformal CVD SiO2 layer.
Another approach for the introduction of air cavities is the use anisotropic etching. This approach includes eliminating material using an anisotropic dry etch. A mask is then used as part of the dry etch and strip operations. Subsequently, a conformal CVD SiO2 film, followed by a non-conformal CVD SiO2 film, is deposited on top of the lines to be used for the creation of airgaps.
U.S. Pat. No. 6,268,261 describes a process for manufacturing a semiconductor circuit that includes the use of airgaps. This process includes creating a plurality of adjacent conductive lines with a solid fill material between the conductive lines. One or more layers are formed above the lines and the fill material and one or more pathways to the fill material are formed through the layers formed above the lines and the fill material. The fill material is then converted to a gas that escapes through the pathways. This process leaves air voids between adjacent lines. The process results in a multi-layer semiconductor circuit with conductive lines, where the lines have airgaps (or voids) as a dielectric between them. This process has certain drawbacks, however. For example, the solid fill material needs to be deposited between the conductive lines. This fill material must be stable during deposition of the layers on top and be of a composition that is easily convertible to a gas. Further, in designing such circuits, the layers on top of a pathway need to be accounted for. Therefore, such an approach involves research and development of fill material compositions, circuit design considerations, and additional manufacturing operations, such as extra masking and etching steps.
Methods for the integration of airgaps in a semiconductor device and devices produced y such methods are disclosed. One embodiment of such a semiconductor device includes a stack of layers, where the stack of layers has at least one sub-stack of layers. The sub-stack of layers includes a liner layer formed from a liner material and a sacrificial layer formed from a sacrificial layer material. The liner material is resistant to a first etching substance, while the first etching substance is able to etch the sacrificial layer material. In certain embodiments, the sacrificial layer takes the form of a dielectric layer, which is situated under the liner layer.
The liner layer material is situated on top of and under the sacrificial layer (e.g., as multiple liner layers). The liner layer material that is formed on top of the sacrificial layer acts as a hardmask layer. The liner layer material that is situated under the sacrificial layer may act as etch stop layer.
A method for the production of airgaps includes plasma dry etching a hole in the stack of layers with a second etching substance such that a hole or trench (hereafter “hole”) is formed and also chemically and/or mechanically changes the properties of the liner layer locally, such that part of the liner layer is converted locally and becomes etchable by the first etching substance. The method further includes creating a line formed of conductive material in the hole. The line of conductive material may be separated from the sacrificial layer by a barrier layer. The line of conductive material or, if present, the barrier layer, is resistant to the first etching substance. The method also includes applying the first etching substance to the stack of layers, such that airgaps are created around the line.
In certain embodiments a liner layer situated on top of a sacrificial layer is locally converted by the second etching substance, and etching of the hole is stopped by a liner layer situated under said sacrificial layer. In such an approach, the liner layer situated under the sacrificial layer is said to act as an etch stop layer. In other embodiments, both the liner layer on top of the sacrificial layer (acting as hardmask layer) and the liner layer under the sacrificial layer are locally converted by the second etching substance.
The creation of the line of conductive material in the hole may be accomplished using any number of techniques. For example, the line may be formed by depositing a barrier layer and then depositing a layer of electrically conductive material on top of the barrier layer. Overburden of the conductive material and the barrier layer material are removed by applying a subtractive technique on top of the stack of layers such that at least one embedded line is created. Any number of subtractive techniques may be employed. These techniques include, but are not limited to Chemical Mechanical polishing (CMP), Electro Polishing, etch techniques or any combination of these or other techniques.
Various embodiments are described herein with reference to the following drawings. Certain aspects of the drawings are depicted in a simplified way for reason of clarity. Not all alternatives and options are shown in the drawings and, therefore, the invention is not limited in scope to the content of the drawings. Like numerals are employed to reference like parts in the different figures, in which:
The following description illustrates various embodiments of methods for producing semiconductor devices using airgaps for isolation and embodiments of devices produced by such methods. It will be appreciated that there are numerous variations and modifications of these embodiments that are possible. Accordingly, the description of the various embodiments should not be deemed to limit the scope of the invention, which is defined by the claims.
Methods for the integration and/or formation of airgaps in a semiconductor device are described. Such methods may be used to produce a semiconductor device including a stack of layers, where the stack of layers includes at least one sub-stack of layers.
In one embodiment of a semiconductor device produced by such a method, the sub-stack of layers includes a liner layer made of a liner material and a sacrificial layer made of a sacrificial layer material. The liner layer, which is formed of silicon-carbide (SiC), is converted locally into the sacrificial material (e.g., to SiO2). In this particular device, the chemically changed part of the liner layer has in-plane dimensions smaller than 1 μm, smaller than 500 nm, or smaller than 100 nm. It will be appreciated that in-plane dimensions of smaller than 10 nm are achievable.
For this device, the liner material is resistant to a first etching substance. The first etching substance may be hydrofluoric acid (HF) in a diluted solution. Alternatively, HF may be used in a vapor form as vapor HF (VHF). Other substances may be used for the first etching substance in place of HF or VHF. The particular substance used depends, in part, on the materials being used to produce the semiconductor device.
In cases where the first etching substance is an HF diluted solution, an anhydrous HF solution may be used instead of an aqueous HF solution (HF/H2O mixture). Use of an anhydrous solution may provide for improved control of the etch process. For example, HF/alcohol (e.g., methanol) mixtures may be used.
The first etching substance is reactive with the sacrificial layer material, such that the first etch substance etches (removes) the sacrificial layer material. In a typical embodiment, the sacrificial layer is a dielectric layer that is situated under a liner layer. The liner layer on top of the sacrificial layer functions as a hardmask layer. A second liner layer, in the sub-stack of layers, may be situated under said sacrificial layer to act as etch stop layer. The liner layers (under and on top of the sacrificial layer) may be formed from silicon carbide (SiC).
A method for the integration of airgaps (e.g., in a semiconductor device) includes etching a hole in a stack of layers (such as the sub-stack of layers described above) with a second etching substance (e.g., an anisotropic dry plasma), such as during “end of line” processing of the semiconductor device (e.g., during interconnect formation). The second etching substance may be an oxidizing substance, such as a dry etch plasma that contains oxygen.
The second etching substance is also used to chemically alter the properties of the liner layer locally, such that part of the liner layer is converted locally and becomes etchable by the first etching substance (e.g., is converted to the same material (or a highly similar material) as the sacrificial layer material). The process of locally chemically altering the liner layer may also result in the removal of the chemically altered portion of the liner layer, thus forming a plug-hole in the liner layer. Alternatively, a separate operation may be used to remove the portion of the liner layer that has been locally chemically altered.
The method further includes forming a line made from a conductive material embedded in the hole. The conductive line may be separated from the sacrificial layer by a barrier layer that is resistant to the first etching substance, which may be the line or, if present, the barrier layer. The conductive material may be selected from a group of materials including metals, carbon nanotubes and conductive polymers. For example, the conductive material may be Cu, Au or Ag. However, it will be appreciated that other conductive materials may also be used.
In this method, the filling of the holes leads to the creation of conductive lines. These conductive lines are formed as part of a (single or dual) damascene structure in a semiconductor device. The dual damascene structure is made of horizontal lines (also referred to as “trenches”) and vertical structures (referred to as “vias”). Single and dual damascene structures are formed during so-called “end of line” (EOL) semiconductor processing.
The method then includes applying the first etching substance to the stack of layers to create airgaps around the conductive line. Such airgaps may be formed preferably near the damascene trenches and/or near the vias. In situations where the conducting material of the conductive line is not resistant to the first etching substance and a barrier layer is present, an additional step of depositing a protective layer on the exposed part of the line is employed before the first etching substance is applied.
While the production of airgaps is generally described herein in the context of electrical isolation, it will be appreciated that airgaps may also be created using the methods described herein for other purposes. For instance, airgaps may be formed during the production of a micro-electromechanical systems (MEMS) device. In such an application, the airgap may be integrated in the MEMS device as a structural or functional element.
Semiconductor Devices with Integrated Airgaps
As may be seen in
In this embodiment, the hardmask liner layer 2 (e.g., SiC) is deposited on top of the upper (sacrificial) dielectric layer 3. The hardmask liner layer 2 is resistant to etching agents that are used to remove the sacrificial layer material (e.g., HF or VHF) and the hardmask liner layer 2 is non-conductive. Local conversion of the liner is performed before the creation of the interconnects 1. Such local conversion is achievable on a nanometer scale. The local conversion generates vulnerable spots (plugs) in the hardmask liner layer 2. Such localized conversion of the SiC liner layer may be accomplished using an oxygen containing plasma to locally convert the SiC into SiO2. The plugs (when removed to form plug-holes) act as channels for chemical diffusion of the interconnects 1. As previously described, a barrier layer may also be deposited.
The overburden of the deposited metal (conductive material) and the overburden of the barrier material are removed and planarized using known techniques, such as Chemical Mechanical Polishing (CMP). An etching agent is then applied to dissolve the sacrificial material between the narrowly spaced conductive lines (e.g., the interconnects 1).
A dry etch step is used to form vias and trenches, as is shown in
Materials that may be used to form a barrier layer are TaN, Ta, TiN, Ti, WN or WCN, etc. Further, any number of techniques may be used to form such a barrier layer. These techniques include Physical Vapor Deposition (PVD), Metal Organic Chemical Vapor Deposition (MO-CVD), Atomic Layer Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Chemical Vapor Deposition (CVD), and spin-on deposition. Furthermore, such a barrier layer may prevent diffusion of conductive material into the dielectric material (e.g., the low-k material).
The basis layer 9 may also be resistant to the etching substance used to form the airgaps, so as to limit the creation of airgaps under the metal (Cu) lines and/or vias 1. The basis layer 9 may thus be a metal structure. In this situation, both the dielectric layer 3 and basis layer 9 may be formed of SiCO:H material, where the basis layer 9 contains higher carbon content to make it more resistant to HF than the dielectric layer 3. In such embodiments, the basis layer 9 may alternatively be formed from a non silicon containing material, such as a low-k spin-on material.
The dry etch step takes place in an O2 containing plasma. As is illustrated in
In the situation where the basis layer 9 is not resistant to HF, the etch process to form the airgaps may be a timed etch operation. In such an approach, the HF exposure (etch) would be stopped once the lower liner layer 2 is reached to prevent the HF from attacking the basis layer 9.
The embodiments illustrated in
For the embodiments illustrated in
HF (or VHF) diffuses (as indicated by the arrows 8) through the local oxidation plugs 7 into the SiO2 dielectric material layer 3 to form airgaps 4, without contacting the Cu line 1, which is surrounded on its vertical sides with the SiC layer 22, as may be seen in FIGS. 4E/5E. The Cu line 1 may be formed in the same fashion as was described above with respect to
For the embodiments described above, one consideration is control of the size of the airgaps 4 that are formed as a result of HF exposure. One factor that affects the size of the airgaps 4 is the duration of the dry plasma etch that locally changes the properties of the liner layers, and affects the lateral depth of oxidation into the liner layers 2. However, the duration of the application of the etching substance (e.g., HF of VHF) to create the airgaps 4 has a more direct affect on the size of the airgaps 4. That is, the size of the airgaps 4 is somewhat independent of the lateral depth of the liner layers 2 that is chemically and/or mechanically changed. Thus, the size of the airgaps 4 may be well controlled by modifying the duration of time that the etching substance for forming the airgaps 4 is applied to the stack of layers.
The distance between neighboring conductor lines is determined by the limitations of available techniques for forming neighboring holes in stack of layers, such as the approaches discussed above. For example, metal lines may be spaced at about 1 μm. The embodiments described above are relatively scaling invariant and are not limited to use for any particular distance between conductor (metal) lines, as chemically and/or mechanically changing the properties of the liner layers locally may be achieved on a nanometer or smaller scale.
A 200 mm wafer that included a single-damascene (SD) stack (such as illustrated in
Organosilicon trimethylsilane gas and He at a pressure of ca. 8 Torr were employed as precursors for a-SiC:H (amorphous hydrogenated SiC). For SiO2, SiH4 and N2O at 2.6 Torr served as precursors. The main mechanical characteristic of a-SiC:H (also referred to as BLOK or barrier low-k) is a +40 to 300 MPa stress. The dry etch was performed according to the following conditions: Pressure: 175 and 70 mTorr for a double step SiO2 etch, and 90 mTorr for a SiC etch.
The temperature of a wafer chuck employed was set at 20 degrees C.; with the wafer temperature during the dry etch sequence can ramping up to 70-80 degrees C. depending on the process specifications and duration
The etch species used were as follows: SiO2 was etched in a 2-step sequence including a main etch using Ar, O2, CF4 and CHF3 (low SiO2/SiC selectivity) and an overetch using Ar, C4F8, O2. SiC was etched with a plasma composed of Ar, N2, CF4, and CHF3. The etch times were determined based on the desired feature size and depth. Typically it takes approximately 60s to etch a 250 nm wide trench to a depth of 600 nm (using the SiO2 main etch step).
The strip was done in two steps (i) dry strip which employed vapor H2O and (ii) wet strip. Additionally, the samples underwent a well controlled SiO2 etch using a clean room compatible 49% HF solution. The amount of SiO2 etched was controlled with the etch time and etch temperature.
Another process flow for integrating airgaps is illustrated in
Capacitance was measured between 1-2 cm long meanders and forks (such as illustrated in
A cross-sectional TEM image of a SD stack is shown in
Various arrangements and embodiments have been described herein. It will be appreciated, however, that those skilled in the art will understand that changes and modifications may be made to these arrangements and embodiments without departing from the true scope and spirit of the present invention, which is defined by the following claims.