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Publication numberUS20060161452 A1
Publication typeApplication
Application numberUS 11/374,710
Publication dateJul 20, 2006
Filing dateMar 14, 2006
Priority dateJan 29, 2004
Also published asCN1910516A, CN1910516B, US7646906, US20060236294, WO2005073807A1
Publication number11374710, 374710, US 2006/0161452 A1, US 2006/161452 A1, US 20060161452 A1, US 20060161452A1, US 2006161452 A1, US 2006161452A1, US-A1-20060161452, US-A1-2006161452, US2006/0161452A1, US2006/161452A1, US20060161452 A1, US20060161452A1, US2006161452 A1, US2006161452A1
InventorsCarl Hess
Original AssigneeKla-Tencor Technologies Corp.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Computer-implemented methods, processors, and systems for creating a wafer fabrication process
US 20060161452 A1
Abstract
Computer-implemented methods, processors, and systems for creating a wafer fabrication process are provided. One computer-implemented method includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. The method also includes creating the wafer fabrication process based on the overall error budget and the individual error budgets.
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Claims(21)
1. A computer-implemented method for creating a wafer fabrication process, comprising:
determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters; and
creating the wafer fabrication process based on the overall error budget and the individual error budgets.
2. The method of claim 1, wherein the wafer fabrication process comprises a lithography process.
3. The method of claim 1, wherein the wafer fabrication process comprises an etch process.
4. The method of claim 1, wherein the wafer fabrication process comprises a device design process, a reticle manufacturing process, and a lithography process.
5. The method of claim 1, wherein the wafer fabrication process comprises a device design process, a reticle manufacturing process, a lithography process, and an etch process.
6. The method of claim 1, wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget and the individual error budgets.
7. The method of claim 1, wherein said creating comprises modifying predetermined operating set points for the different parameters based on the overall error budget and the individual error budgets.
8. The method of claim 1, wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget and how variations in the individual error budgets affect how the reticle design data will be printed on the wafer.
9. The method of claim 1, wherein the individual error budget for one of the different parameters is determined as a function of the individual error budget for another of the different parameters.
10. The method of claim 1, wherein said creating comprises selecting operating set points and levels of control for at least two of the different parameters based on the overall error budget and a function describing an interrelated effect of the individual error budgets for the at least two of the different parameters on how the reticle design data will be printed on the wafer.
11. The method of claim 1, wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and controllability of the different parameters.
12. The method of claim 1, wherein said creating comprises selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and cost of implementing the levels of control.
13. The method of claim 1, wherein the different parameters comprise all parameters of the wafer fabrication process that can alter how the reticle design data will be printed on the wafer.
14. The method of claim 1, further comprising generating the simulated images by generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process and generating the simulated images using the first simulated image.
15. The method of claim 1, wherein the different values span a predetermined process window for the different parameters.
16. The method of claim 1, further comprising detecting defects in the simulated images, wherein said determining comprises determining the individual error budgets based on the overall error budget and the defects in the simulated images.
17. The method of claim 1, wherein the different parameters comprise different characteristics of the reticle design data.
18. The method of claim 17, further comprising creating a design process for the reticle design data based on the overall error budget and the individual error budgets for the different parameters.
19. The method of claim 17, further comprising altering the reticle design data based on the overall error budget and the individual error budgets for the different parameters.
20. A processor configured to perform a method for creating a wafer fabrication process, wherein the method comprises:
determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters; and
creating the wafer fabrication process based on the overall error budget and the individual error budgets.
21. A system configured to create a wafer fabrication process, comprising:
a simulation engine configured to generate simulated images illustrating how reticle design data will be printed on a wafer at different values of different parameters of the wafer fabrication process; and
a processor configured to determine individual error budgets for the different parameters based on an overall error budget for the wafer fabrication process and the simulated images and to create the wafer fabrication process based on the overall error budget and the individual error budgets.
Description
PRIORITY CLAIM

This application is a continuation-in-part of U.S. patent application Ser. No. 11/048,630 entitled “Computer-Implemented Methods for Detecting Defects in Reticle Design Data,” filed Jan. 31, 2005, which claims priority to U.S. Provisional Application No. 60/540,031 entitled “Method and System of Qualifying Integrated Circuit Design for Manufacturability and Application to Improving Critical Dimension Control in Integrated Circuit Manufacturing,” filed Jan. 29, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to computer-implemented methods for detecting defects in reticle design data. Certain embodiments relate to a computer-implemented method that includes detecting defects in reticle design data using simulated images that illustrate how a reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process.

2. Description of the Related Art

The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.

Fabricating semiconductor devices such as logic and memory devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes to form various features and multiple levels of the semiconductor devices. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated in an arrangement on a semiconductor wafer and then separated into individual semiconductor devices.

Lithography is typically one of the most important processes in integrated circuit manufacturing since this is the process in which features are patterned on the wafer. The pattern printed in a resist by lithography is then utilized as a masking layer to transfer the pattern to additional layers on the wafer in subsequent processing steps. Therefore, the pattern that is formed on the wafer during lithography directly affects the features of the integrated circuits that are formed on the wafer. Consequently, defects that are formed on a wafer during lithography may be particularly problematic for the integrated circuit manufacturing process. One of the many ways in which defects may be formed on the patterned wafer during lithography is by transfer of defects that are present on the reticle to the wafer. Therefore, detection and correction of defects on the reticle such as unwanted particulate or other matter is performed rather stringently to prevent as many defects on the reticle from being transferred to the wafer during lithography.

However, as the dimensions of integrated circuits decrease and the patterns being transferred from the reticle to the wafer become more complex, defects or marginalities in the features formed on the reticle become increasingly important. In particular, if the pattern is not formed accurately on the reticle, such discrepancies increasingly produce defects on the wafer as the dimensions of the pattern decrease and the complexity of the pattern increases. In addition, marginalities in the reticle design may cause the design to print incorrectly on the wafer. Therefore, significant efforts have been devoted to methods and systems that can be used to detect problems in the pattern on the reticle or in the design that will cause problems on the wafer. These efforts are relatively complex and difficult due, at least in part, to the fact that not all discrepancies or marginalities in the pattern formed on the reticle (as compared to the ideal pattern) will cause errors on the wafer that will adversely affect the integrated circuit. In other words, some error in the pattern formed on the reticle may not produce defects on the wafer at all or may produce defects on the wafer that will not reduce the performance characteristics of the integrated circuit. Therefore, one challenge of many in developing adequate methods and systems for qualifying a reticle pattern is to discriminate between pattern defects or marginalities that “matter” and those that do not.

One way to check a reticle pattern before the reticle is fabricated is design rule checking (DRC). However, conventional DRC operates only at the nominal process conditions, or at most, at a limited number of process conditions and/or at a limited number of points within the device. Other software based methods for detecting design pattern defects prior to fabrication of the reticle have been proposed, and one such method is described in U.S. Patent Application Publication No. 2003/0119216A1 by Weed, which is incorporated by reference as if fully set forth herein. However, this method is designed to determine only the best focus and exposure settings and not to explore the full range of the process window conditions available for each design. Another method described in U.S. Pat. No. 6,373,975 to Bula et al., which is incorporated by reference as if fully set forth herein, runs simulations only to test for specific design rule violations and does not compare full chip simulated images to a reference to detect arbitrary defects.

Therefore, such software methods have several disadvantages. In particular, these software methods do not examine the full range of process window conditions thereby failing to detect process window marginalities and missing potential defects. In addition, these methods do not determine the exact focus and exposure conditions under which defects will occur thereby preventing the complete optimization of the design. The lack of complete process window information also limits the ability to implement advanced process control techniques for critical dimension control across all critical features on the device.

Accordingly, it would be desirable to develop methods and systems that can detect reticle design defects or marginalities within an entire chip and across a range of process conditions such as focus and exposure before the reticle is manufactured to reduce the cost of fabricating a reticle that is qualified for use in integrated circuit manufacturing and to reduce the time involved in fabricating a reticle that passes qualification for integrated circuit manufacturing.

SUMMARY OF THE INVENTION

The following description of various embodiments of computer-implemented methods for detecting defects in reticle design data is not to be construed in any way as limiting the subject matter of the appended claims. The methods described herein are generally referred to as virtual process window qualification (vPWQ) methods.

An embodiment of the invention relates to a computer-implemented method for detecting defects in reticle design data. The method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. Therefore, the method includes performing a simulation in a two step approach: first, simulating from design to reticle (i.e., simulation of the mask making process); then, simulating the reticle to wafer pattern transfer (i.e., simulation of the wafer manufacturing process). In addition, the method includes detecting defects in the reticle design data using the second simulated images.

In one embodiment, the first and second simulated images include simulated images of a complete chip defined by the reticle design data. In some embodiments, the different values span a predetermined process window for the one or more parameters of the wafer printing process. Therefore, the method may include simulation of the full chip across the full process window to determine regions of the device that will fail first as the process conditions (such as focus and exposure) vary. In another embodiment, the reticle design data includes reticle design data modified by resolution enhancement technology (RET) feature data.

In additional embodiments, the method includes determining a process window for the wafer printing process based on results of the detecting step. In another embodiment, the method includes determining which of the different values at which at least one of the defects appears in the second simulated images. In a further embodiment, the method includes determining a region in the reticle design data in which the defects appear at the different values that are closer to nominal values for the one or more parameters of the wafer printing process than the different values at which the defects appear in other regions in the reticle design data.

In one embodiment, the detecting step includes comparing the second simulated images to a reference image. In this manner, the method may involve identification of “defective” regions in the reticle design data by comparison to a reference image. The reference image may include an additional simulated image illustrating how the reticle will be printed on the wafer at nominal values of the one or more parameters of the wafer printing process. In another such embodiment, the reference image illustrates how the reticle design data would ideally be printed on the wafer. In other embodiments, the detecting step includes comparing one of the second simulated images to additional simulated images that illustrate how the reticle will be printed on the wafer at the different values that are closer to nominal values of the one or more parameters of the wafer printing process than the different values corresponding to the one second simulated image.

In some embodiments, the method may include generating additional simulated images illustrating how the reticle design data will be printed on the reticle at different values of one or more parameters of the reticle manufacturing process. One such embodiment includes selecting the different values of the one or more parameters of the reticle manufacturing process that produce a minimum number of design pattern defects on the reticle. As such, the method may include selecting the most appropriate mask making process for the reticle design data. In another embodiment, the method includes altering the reticle design data based on results of the detecting step. The altering step may include altering RET feature data of the reticle design data. In this manner, the method allows for optimal selection of resolution enhancements, optical proximity correction (OPC) rules, design layout, etc.

In one embodiment, the method may include generating an inspection process for the reticle based on results of the detecting step. In one such embodiment, the method may include linking vPWQ data to reticle inspection to drive selective sensitivity of the inspector. In an additional embodiment, the method may include generating an inspection process for the wafer based on results of the detecting step. In one such embodiment, the method may include linking vPWQ data to wafer inspection to drive selective sensitivity of the inspector. In a different embodiment, the method may include fabricating the reticle subsequent to the detecting step, inspecting the reticle, and generating an inspection process for the wafer based on results of the detecting step and the inspecting step. In this manner, the method may include linking the combination of vPWQ and reticle inspection data to wafer inspection to drive selective sensitivity of the wafer inspector. In another embodiment, the method may include fabricating the reticle subsequent to the detecting step, inspecting the reticle, and generating an inspection process for the wafer based on results of the detecting step, results of the inspecting step, critical feature data generated by a designer of the reticle design data, or some combination thereof. As such, the methods may include linking the combination of vPWQ, reticle inspection, and/or critical features identified by the designer to drive wafer inspection sensitivity, metrology sample plans and critical dimension (CD) control systems for optimal yield.

In a further embodiment, the method may include identifying first regions in the reticle design data that have a greater probability of being printed defectively than second regions in the reticle design data and generating a process control method for wafers that will be printed with the reticle based on results of the identifying step. In one such embodiment, the method may include linking vPWQ to wafer CD metrology tools to drive the optimum sampling plan and to detect the earliest possible signs of process failure in critical regions identified by vPWQ. In yet another embodiment, the method may include identifying first regions in the reticle design data that have a greater probability of being printed defectively than second regions in the reticle design data and altering the reticle design data based on the identifying step. In this manner, the method may include feedback of vPWQ data to the designer and/or design process to enable optimization of device electrical parameters in the regions identified by vPWQ as most limited in terms of process window tolerance. Each of the embodiments of the method described above may include any other step(s) described herein.

Another embodiment relates to a simulation engine configured to generate a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The simulation engine is also configured to generate second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. The second simulated images can be used to detect defects in the reticle design data. The simulation engine may be further configured as described herein.

An additional embodiment relates to a system configured to detect defects in reticle design data. The system includes a simulation engine configured to generate a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The simulation engine is also configured to generate second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. The system also includes a processor configured to detect defects in the reticle design data using the second simulated images. The system may be further configured as described herein.

Another embodiment relates to a different method for detecting defects in reticle design data. This method includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. The method also includes generating second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. In addition, the method includes determining a rate of change in a characteristic of the second simulated images as a function of the different values. This method further includes detecting defects in the reticle design data based on the rate of change. In one embodiment, the detecting step may include using the rate of change in combination with the second simulated images to detect the defects in the reticle design data. Each of the embodiments of this method may also include any other step(s) described herein.

An additional embodiment relates to a method for detecting defects in reticle design data printed on a reticle. This method includes printing images of the reticle on a wafer at different values of one or more parameters of a wafer printing process. The method also includes determining a rate of change in a characteristic of the images as a function of the different values. In addition, the method includes detecting defects in the reticle design data based on the rate of change. This method may also include any other step(s) described herein.

A further embodiment relates to a computer-implemented method for creating a wafer fabrication process. The method includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. The method also includes creating the wafer fabrication process based on the overall error budget and the individual error budgets.

In one embodiment, the wafer fabrication process includes a lithography process. In another embodiment, the wafer fabrication process includes an etch process. In an additional embodiment, the wafer fabrication process includes a device design process, a reticle manufacturing process, and a lithography process. In some embodiments, the wafer fabrication process includes a device design process, a reticle manufacturing process, a lithography process, and an etch process.

In one embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget and the individual error budgets. In some embodiments, creating the wafer fabrication process includes modifying predetermined operating set points for the different parameters based on the overall error budget and the individual error budgets. In another embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget and how variations in the individual error budgets affect how the reticle design data will be printed on the wafer.

In an additional embodiment, the individual error budget for one of the different parameters is determined as a function of the individual error budget for another of the different parameters. In some embodiments, creating the wafer fabrication process includes selecting operating set points and levels of control for at least two of the different parameters based on the overall error budget and a function describing an interrelated effect of the individual error budgets for the at least two of the different parameters on how the reticle design data will be printed on the wafer.

In a further embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and controllability of the different parameters. In another embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and cost of implementing the levels of control.

In one embodiment, the different parameters include all parameters of the wafer fabrication process that can alter how the reticle design data will be printed on the wafer. In another embodiment, the method includes generating the simulated images by generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process and generating the simulated images using the first simulated image. In an additional embodiment, the different values span a predetermined process window for the different parameters. In a further embodiment, the method includes detecting defects in the simulated images. In one such embodiment, determining the individual error budgets includes determining the individual error budgets based on the overall error budget and the defects in the simulated images.

In some embodiments, the different parameters include different characteristics of the reticle design data. In one such embodiment, the method includes creating a design process for the reticle design data based on the overall error budget and the individual error budgets for the different parameters. In another such embodiment, the method includes altering the reticle design data based on the overall error budget and the individual error budgets for the different parameters. Each of the embodiments of the method described above may include any other step(s) of any other method(s) described herein.

Another embodiment relates to a processor configured to perform a method for creating a wafer fabrication process. The method includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. The method also includes creating the wafer fabrication process based on the overall error budget and the individual error budgets. The processor may be further configured as described herein.

An additional embodiment relates to a system configured to create a wafer fabrication process. The system includes a simulation engine configured to generate simulated images illustrating how reticle design data will be printed on a wafer at different values of different parameters of the wafer fabrication process. The system also includes a processor configured to determine individual error budgets for the different parameters based on an overall error budget for the wafer fabrication process and the simulated images. The processor is also configured to create the wafer fabrication process based on the overall error budget and the individual error budgets. The system may be further configured as described herein.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the present invention may become apparent to those skilled in the art with the benefit of the following detailed description of the preferred embodiments and upon reference to the accompanying drawings in which:

FIG. 1 is a flow chart illustrating a method for qualifying a reticle for production in integrated circuit manufacturing;

FIG. 2 is a flow chart illustrating one embodiment of a computer-implemented method for detecting defects in reticle design data;

FIG. 3 is a flow chart illustrating one embodiment of a method for data flow between a computer-implemented method for detecting defects in reticle design data and other process steps;

FIG. 4 is a schematic diagram illustrating one example of different areas in reticle design data having different levels and types of criticality;

FIG. 5 is a schematic diagram illustrating one example of different values of parameters of a wafer printing process for which simulated images can be generated, which can be used to detect defects in reticle design data;

FIG. 6 is a schematic diagram illustrating one embodiment of different values of parameters of a wafer printing process for which simulated images can be generated, which can be used to detect defects in reticle design data;

FIG. 7 is a schematic diagram illustrating one arrangement of dies printed on a wafer at different values of parameters of a wafer printing process that can be used to detect defects in reticle design data;

FIG. 8 is a schematic diagram illustrating one embodiment of an arrangement of dies simulated or printed on a wafer at different values of parameters of a wafer printing process that can be used to detect defects in reticle design data;

FIGS. 9-12 are flow charts illustrating various embodiments of a computer-implemented method for detecting defects in reticle design data; and

FIG. 13 is a block diagram illustrating one embodiment of a processor configured to perform a method for creating a wafer fabrication process and one embodiment of a system configured to create a wafer fabrication process.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and may herein be described in detail. The drawings may not be to scale. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As used herein, the term “wafer” generally refers to a substrate formed of a semiconductor or non-semiconductor material. Examples of such a semiconductor or non-semiconductor material include, but are not limited to, monocrystalline silicon, gallium arsenide, and indium phosphide. Such substrates may be commonly found and/or processed in semiconductor fabrication facilities.

A wafer may include only the substrate. Such a wafer is commonly referred to as a “virgin wafer.” Alternatively, a wafer may include one or more layers formed upon a substrate. For example, such layers may include, but are not limited to, a resist, a dielectric material, and a conductive material. A resist may include any material that may be patterned by an optical lithography technique, an e-beam lithography technique, or an X-ray lithography technique. Examples of a dielectric material include, but are not limited to, silicon dioxide, silicon nitride, silicon oxynitride, and titanium nitride. Additional examples of a dielectric material include “low-k” dielectric materials such as Black Diamond™ which is commercially available from Applied Materials, Inc., Santa Clara, Calif., and CORAL™ commercially available from Novellus Systems, Inc., San Jose, Calif., “ultra-low k” dielectric materials such as “xerogels,” and “high-k” dielectric materials such as tantalum pentoxide. In addition, examples of a conductive material include, but are not limited to, aluminum, polysilicon, and copper.

One or more layers formed on a wafer may be patterned or unpatterned. For example, a wafer may include a plurality of dies having repeatable pattern features. Formation and processing of such layers of material may ultimately result in completed semiconductor devices. As such, a wafer may include a substrate on which not all layers of a complete semiconductor device have been formed or a substrate on which all layers of a complete semiconductor device have been formed. The term “semiconductor device” is used interchangeably herein with the term “integrated circuit.” In addition, other devices such as microelectromechanical system (MEMS) devices and the like may also be formed on a wafer.

A “reticle” or a “mask” is generally defined as a substantially transparent substrate having substantially opaque regions formed thereon and configured in a pattern. The substrate may include, for example, a glass material such as quartz. The substantially opaque regions may be formed of a material such as chromium. A reticle may be disposed above a resist-covered wafer during an exposure step of a lithography process such that the pattern on the reticle may be transferred to the resist. For example, substantially opaque regions of the reticle may protect underlying regions of the resist from exposure to an energy source. Many different types of reticles are known in the art, and the term reticle as used herein is intended to encompass all types of reticles.

As used herein, the term “defects” refers to marginalities in a reticle design that will cause the reticle design to print incorrectly on a wafer. In addition, the defects may print on the wafer at only certain values of one or more parameters of a wafer printing process. The term “wafer printing process” is used interchangeably herein with the term “lithography process.”

The terms “first” and “second” are used herein only to distinguish between different simulated images, different regions on a reticle, etc. and are not to be construed in any other manner.

One particularly successful method for qualifying a reticle for integrated circuit manufacturing is the process window qualification (PWQ) method that is described in U.S. patent application Ser. No. 09/211,156 by Peterson et al., filed Aug. 2, 2002, issued as U.S. Pat. No. 6,902,855 on Jun. 7, 2005, which is incorporated by reference as if fully set forth herein. This method generally involves printing a fabricated photomask on a wafer and inspecting the wafer in a specified manner to detect design marginalities, which will cause failures and low yield on production wafers. While effective for design defect detection, PWQ cannot detect the design defects until after the mask or reticle has been fabricated, often at very high cost. In addition, correcting the reticle design and fabricating a new mask with the corrected design for additional design defect detection are also both expensive and time consuming.

To detect marginalities in reticle design data before a reticle is even made, computer-implemented methods have been developed and are described herein, which are generally referred to herein as “virtual process window qualification” (vPWQ). Instead of fabricating an actual mask and printing actual wafers with the mask, vPWQ uses the reticle design data to simulate what the mask and wafer would look like if the reticle design data was printed on the mask and wafer, respectively. The simulated images of what the reticle design data would look like on the wafer may be generated across the full range of focus and exposure conditions expected to be used in the production environment.

In vPWQ, defects are detected by comparing a reference image to different simulated images illustrating how the reticle design data would be printed on a wafer, which are generated for different values of focus and exposure and/or other parameters of the wafer printing process. The reference image may represent how the reticle design data would be printed on the wafer at the best focus/best exposure conditions or nominal focus and exposure conditions. Alternatively, the reference image may be the ideal image of the reticle design data, which can be generated from the design data prior to optical proximity correction (OPC) “decoration” (i.e., prior to modification of the reticle design data by the OPC data). Therefore, in essence, vPWQ is a virtual wafer to database inspection method, where the virtual wafer is generated for different focus and exposure conditions, preferably across the entire process window that will be used for the reticle in a lithography process. In this manner, the complete design layout (including OPC and other reticle enhancement techniques (RETs)) can be optimized for the best possible range of valid focus and exposure conditions (i.e., the largest process window) before the design is committed to the mask.

In general, therefore, one embodiment of a computer-implemented method for detecting defects in reticle design data includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. In one embodiment, vPWQ uses the design database, including all optical enhancements (OPC, phase shifting features, and other RET), and simulates how the mask will be manufactured. In this manner, the reticle design data used in the methods described herein may include reticle design data modified by RET feature data.

The method also includes generating second simulated images using the first simulated image. The second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. For instance, generating the second simulated images can be performed using one or more models such as a resist model (e.g., a model of the resist that will be printed with the reticle design data on the wafer) and a lithography model (e.g., a model of the optical parameters of an exposure tool that will be used to print the reticle on the wafer and a model of other process steps involved in the lithography process such as develop and post exposure bake). Such models and/or parameters for such models may be acquired from one or more sources such as the PROLITH software, which is commercially available from KLA-Tencor.

The different values at which the second images are simulated may span a predetermined process window for the one or more parameters of the wafer printing process. For example, the predetermined process window may be a process window that is desired or available for the wafer printing process to be used with the reticle. However, as described further herein, the actual process window that is determined for use with the reticle design data may be smaller than this predetermined process window. The one or more parameters may include, but are not limited to, dose and focus. For example, the one or more parameters may also include different types of illumination that are available for use with the reticle (e.g., annular and quadrapole). In one embodiment, the second simulated images, which are also referred to herein as “test images,” may illustrate how the actual mask will be printed at the wafer level across the full range of focus and exposure conditions. The first and second simulated images may include simulated images of a complete chip defined by the reticle design data.

vPWQ, therefore, involves breaking the simulation into 2 steps: 1) using a database description of the reticle design to render a simulated image of how the reticle will be written (simulating the reticle manufacturing process); and 2) using the simulated reticle pattern to render simulated wafer patterns. This 2 step approach has many advantages. For example, this approach allows the user to simulate not just the reticle design, but the combination of reticle design data plus mask manufacturing process, thus enabling selection of the best mask making process for a given design and/or optimization of the design rules for the selected process. This approach also produces more accurate simulations by removing the design to mask offset.

In addition, the method includes detecting defects in the reticle design data using the second simulated images. For example, the test images may be compared to a reference image on a point by point basis, and defects are identified in the test images using, for example, algorithms. The algorithms that are used for the methods described herein may be the same as, or substantially similar to, those used in typical reticle inspection. In one embodiment, the reference image that is compared to the second simulated images for defect detection includes a simulated image illustrating how the reticle will be printed on the wafer at nominal values of the one or more parameters of the wafer printing process. In a different embodiment, the reference image that is compared to the second simulated images for defect detection illustrates how the reticle design data would ideally be printed on the wafer. In this manner, the reference image can either be the circuit layout as ideally conceived by the designer prior to RET decoration or the simulated wafer image under the best focus and exposure conditions.

The reference images used for defect detection may also be variations of the reference images described above. For example, as described above, the reference image can be the reticle pattern layout intended by the designer or the pattern simulated at best focus and exposure conditions. This “designer intended” layout can be modified by simulating the expected mask to design bias so that the reference image illustrates the undecorated pattern that will be printed on a reticle under nominal mask making conditions.

The reference image can also be a simulated image illustrating how the reticle design data will be printed on a wafer under best focus and exposure conditions. The usefulness of this simulated reference image could be improved by calibrating the simulation model using wafer print images and/or data of standard test cells that are also included in the design under test. Alternatively, the reference simulated image may be modified by using wafer print images and/or data for sections of the new design that had been included in previous or test reticles, which is thereby available at the wafer level.

The reference image simulation can also be calibrated using aerial image data collected from prior designs or test reticles. The reference aerial image data may be generated by inserting an existing reticle in a scanner and monitoring the aerial image at the wafer plane. Alternatively, the reference aerial image may be generated by inserting one or more existing reticles in an aerial image defect detection and/or review tool with optical conditions set up to emulate the performance of a physical exposure system (scanner). Examples of aerial image defect detection and/or review tools are illustrated in U.S. patent application Ser. No. 09/679,617 by Stokowski et al. filed on Oct. 6, 2003, which is incorporated by reference as if fully set forth herein.

The second simulated images may also be compared to different types of reference images. For example, a reference simulated image illustrating how the reticle will be printed on the wafer at nominal values of the one or more parameters of a wafer printing process is particularly useful for detecting defects in the reticle design data that will vary depending on the one or more parameters. In other words, such a reference image will be particularly useful for detecting defects in the reticle design data that may reduce the process window that can be used with the reticle. In particular, certain defects may not appear at the nominal parameters, but may appear in the second simulated images, particularly as the parameters move farther away from nominal. vPWQ may include determining which of the different values at which at least one of the defects appears in the second image. Depending on the characteristics of these defects (e.g., whether the defects are “killer” defects or not) and the values of the parameters at which these defects appear, the process window that can be used for the reticle in a wafer printing process may be less than the predetermined process window. In one embodiment, therefore, the method may include determining a process window for the wafer printing process based on results of the detecting step. The examination of the expected performance of the wafer printing process within the process window of the reticle is a particular strength of PWQ and vPWQ methods.

However, since such a reference image illustrates how the reticle design data would be printed on a wafer at nominal parameters, this comparison may not detect defects in the reticle design data such as features that will not print on a wafer at all. In particular, if there are features in the reticle design data that simply will not print, these features will be missing from both the reference image simulated for nominal parameters and the second simulated images. Therefore, the missing features will not be detected by such comparisons. A reference image that represents the ideal image of the reticle design data, however, will include both printable and non-printable features. In this manner, comparison between such an “ideal” reference image and the second simulated images may be used to detect missing feature type defects. As such, multiple comparisons can be made between the second simulated images and different reference images to detect different kinds of defects thereby increasing the defect detection capability of the vPWQ methods.

As described above, defect detection may be performed by comparing test and reference images. Any region in the test image that varies from the corresponding region in the reference image by more than a threshold value is flagged as a defect. All of the algorithmic tools used in physical reticle inspection systems can be used in this defect detection step including varying the defect threshold based on local geometry, applying multiple algorithmic detectors based on different smoothing filters applied to varying numbers of nearest neighbor pixels, and detecting single edge misplacements (CD errors) and/or dual edge misplacements (registration errors).

The defect detection algorithms may have the same tuning capability as those used for physical reticle inspection tools. In particular, the algorithms that are used for the methods described herein may be configured such that the sensitivity of the algorithms can be optimized to detect defects which will impact device performance and yield, but not be overwhelmed by small differences between ideal and actual imaging performance. In one such embodiment, the sensitivity of the algorithms may be altered from region to region in the reticle design data based on one or more characteristics of the reticle design data (e.g., dimensions, criticality, etc.). In another such embodiment, the sensitivity of the algorithms may be altered dynamically or in real time based on the results of the detecting step. The sensitivity of the algorithm(s) may be altered in any manner known in the art (e.g., by altering the threshold used in the algorithm).

In one such embodiment, the methods described herein may be configured to perform defect detection with selective sensitivity, which is referred to herein as “SmartInspection.” For example, defects may be identified by vPWQ by comparing simulated wafer images at different process conditions to a nominal or reference image. The sensitivity of this comparison directly affects the defect detection results of the vPWQ process. If the sensitivity is too high, every reticle design will fail since vPWQ will detect excessive numbers of defects. On the other hand, if the sensitivity is too low, potentially critical defects could escape detection. Examples of methods that can be used to implement SmartInspection are described in U.S. patent application Ser. No. 10/883,372 to Marella et al. filed on Jul. 1, 2004, which is incorporated by reference as if fully set forth herein. As described in this patent application, not all areas of a design are equally critical to device performance. In addition, if the designer tags individual portions of the reticle design data to indicate the most critical areas and/or the areas that do not matter to the device performance (dummy fill regions, redundant contacts, unconnected lines, etc.), the sensitivity of vPWQ can be varied on a localized basis to apply the maximum sensitivity to the most critical regions and reduced sensitivity to non-critical areas. Examples of such defect detection methods are also illustrated in U.S. patent application Ser. No. 11/003,291 by Hess et al., filed on Dec. 3, 2004, which is incorporated by reference as if fully set forth herein.

As described herein, the method may include determining a process window for the reticle design data. The process window may include those values of the one or more parameters for which the second simulated images illustrate an acceptable level of defectivity. In addition, the methods described herein may include determining the sensitivity of different regions of the reticle design data to changes in the values of the one or more parameters. For example, in one embodiment, the method may include determining a region in the reticle design data in which the defects appear at the different values of the one or more parameters of the wafer printing process that are closer to nominal values for the one or more parameters of the wafer printing process than the different values at which the defects appear in other regions in the reticle design data. In other words, different regions may be identified in the reticle design data based on how quickly the regions exhibit defects as the parameter(s) move away from the nominal values. Such information may be used in a number of embodiments described herein. For example, this information may be used to tailor reticle inspection, wafer inspection, process control methods, etc. for a particular reticle design.

The methods described herein may also include generating an inspection process for the reticle based on results of the detecting step. In one such embodiment, another extension of the SmartInspection concept is to use the output of the vPWQ inspection to vary the sensitivity of the inspection of the fabricated reticle. In particular, the sensitivity of the reticle inspection can be higher in regions of the reticle design data where vPWQ results indicate the tightest process window, while the sensitivity can be lower in regions where vPWQ results indicate a more comfortable process window. Such reticle inspection methods are also described in the patent application by Hess et al., which is incorporated by reference above.

In another embodiment, the methods described herein may include generating an inspection process for the wafer based on results of the detecting step. In one such embodiment, the methods described herein may use the SmartInspection concept by using the output of the vPWQ methods to vary the sensitivity of the inspection of the printed wafer as a function of position on the wafer. In particular, the sensitivity of the wafer inspection can be higher in regions where vPWQ results indicate the tightest process window, while the sensitivity can be lower in regions where vPWQ results identify a more comfortable process window.

In an additional embodiment, the method may include fabricating the reticle subsequent to the detecting step (e.g., if the results of the detecting step indicate no significant or catastrophic defects in the reticle design data). This embodiment of the method may also include inspecting the reticle and generating an inspection process for the wafer based on results of the detecting step and the inspection of the reticle. In one such embodiment, the methods described herein may use the SmartInspection concept with the combined results of vPWQ and inspection of the fabricated reticle to determine the sensitivity of the inspection of the printed wafer as a function of position on the wafer. Thus, in regions of the reticle design data where the physical reticle inspection shows no problems and the vPWQ simulation predicts a relatively comfortable process window, the wafer inspection sensitivity can be relaxed. Sensitivity could be increased in regions where either vPWQ detected a restricted process window or reticle inspection found a less than optimal pattern where the departure from nominal is not large enough to be considered a defect, but may limit the process window (“subspec region”). The highest sensitivity could be reserved for locations where both vPWQ and reticle inspection identified potential constraints on the process window. In some embodiments, the method may include generating an inspection process for the wafer based on results of the detecting step of the vPWQ method, results of the reticle inspection, critical feature data generated by a designer of the reticle design data, or some combination thereof.

In additional embodiments, the method may include identifying first regions in the reticle design data that have a greater probability of being printed defectively than second or other regions in the reticle design data. One such embodiment may also include generating a process control method for wafers that will be printed with the reticle based on results of the identifying step. In this manner, the method may include determining the best wafer metrology sample plans for a particular reticle design. For example, extra care could be taken to measure locations on a wafer corresponding to the regions where vPWQ and/or reticle inspection identified limited process windows, and critical dimension (CD) measurements could be performed at those locations to insure that the device meets specifications. Extra care may also be taken in any other manner such as increasing the number and/or the sensitivity of the measurements performed in these locations.

In another example, identification of regions in the reticle design data with the most limited process windows as determined by vPWQ, reticle inspection, and/or physical wafer PWQ can also be used to improve the CD control method or other metrology or process control method used in the fab. For example, instead of tracking and adjusting dose and focus to obtain the most stable CDs on test structures or other features, identification of the regions having the most limited process windows allows the control loops (statistical process control (SPC) and/or automatic process control (APC)) to be optimized to keep these locations from drifting outside of the allowed specification limits. The optimization of the control loops may include either a) shifting the metrology sample plan to measure specific features with the most limited process windows or b) measuring other features, determining the focus and exposure conditions, which led to the printing of these test structure dimensions, and applying simulation to predict the expected results of the process window limited features at the determined values of focus and exposure. This optimization technique is an extension of the CD control technique described in U.S. patent application Ser. No. 10/778,752 by Preil et al. filed on Feb. 13, 2004, which is incorporated by reference as if fully set forth herein.

In additional embodiments, the methods described herein may include altering the reticle design data based on the identifying step described above. For example, vPWQ output can be fed back up to the designer or the design process. The results can be used to determine the circuit timing, parasitics and electrical performance of a circuit that will be formed on a wafer that is printed with the reticle design data. The results can also be used to determine if the defects detected by vPWQ have characteristics such as size that will impact circuit performance. Currently, this physical (or electrical) verification is performed assuming that the ideal design as drawn by the layout tools is what will appear on the wafer. However, the vPWQ methods described herein can be used to identify the departures to be expected from this nominal case and to locate the regions of the circuit which will have the largest departure from nominal.

Obviously, using currently available hardware, it would not be practical to attempt to model the electrical performance of a circuit with millions of transistors while varying every single feature of the transistors across the full range of possible sizes. The vPWQ methods described herein, however, can reduce the number of points in the reticle design data that are varied and tested to a manageable number. The designer or the design process or tool can use this data and knowledge of which portions of the circuit are most critical to device performance to run a limited number of additional verifications prior to committing the design to a mask set.

Another aspect of vPWQ that differs from physical PWQ is the ability to flexibly change the simulation conditions during the virtual inspection. In particular, PWQ relies on physical wafers printed under preset conditions of focus and exposure. Since the number of such conditions for which images can be printed on a wafer is relatively limited, the data is highly granular (e.g., increments of focus of 0.1 μm) thereby possibly producing large changes in the number of defects from one setting to the next. However, vPWQ can change settings as it inspects (e.g., in real time as vPWQ is being performed). For example, if too many defects occur in one preset focus or exposure increment, additional simulations can be run automatically to fill in the gap and determine the precise focus and/or exposure settings at which the defect began to print. vPWQ can, therefore, create far more precise maps of the allowed process window for each critical feature.

The vPWQ methods described herein can be used to detect defects in reticle design data for binary masks (chrome on glass (COG) masks) or masks with any of a number of RETs such as OPC, phase shifting masks (alternate aperture or embedded PSM (EPSM)), sub-resolution assist features (SRAFs) such as scattering bars, serifs, and hammerheads, chromeless phase shift masks (CPL), and gray scaled images. The vPWQ methods described herein can also be applied to complementary masks where the desired pattern is decomposed into multiple patterns, which are each imaged under different illumination conditions. For a complementary mask, the vPWQ methods include generating simulated images, each illustrating how the different, multiple patterns will be printed separately on a wafer by the different reticles. The vPWQ method may then use each of the simulated images in combination to generated additional simulated images (the test images) that illustrate how the final reticle design pattern will be printed on a wafer using a multiple exposure wafer printing process on the scanner.

The vPWQ methods described herein are equally applicable to optical lithography processes using visible, ultraviolet, and deep ultraviolet illumination (e.g., 248 nm, 193 nm, and 157 nm light sources), electron beam lithography, or extreme ultraviolet lithography using reflective masks and an exposure wavelength near 13 nm. The vPWQ methods may also be applied to maskless lithography systems where reticle inspection is not possible. In this case, the vPWQ inspection has the added advantage of minimizing the need for difficult die-to-database inspection at the wafer level.

The methods described herein have, therefore, a number of advantages over other reticle design data inspection methods. For instance, the methods described herein can be used for detecting and correcting process window marginalities in the reticle design data prior to manufacturing the masks and printing wafers. As such, the reticle design data inspection methods described herein are substantially less expensive than currently available methods. In addition, the mask making process and the wafer pattern transfer process are simulated. Therefore, the methods described herein account for how the reticle design data will be altered by the reticle manufacturing process and the wafer printing process. For the designer, vPWQ offers the ability to test multiple variations of a design without buying multiple variations of expensive masks. The designer may, therefore, select the reticle design implementation with the broadest process window to maximize device yield in production. vPWQ also provides the ability to generate reticle inspection, wafer inspection, and CD metrology and process control methods having selective sensitivity (sample plans, process window centering, and maximizing the available process window for production). Furthermore, the vPWQ method results may be used for optimization of the circuit design (e.g., optimization of one or more characteristics of the circuit design such as timing, parasitics, other electrical parameters, or some combination thereof).

One preferred embodiment of the wafer level simulation includes simulation of the aerial image (reticle manufacturing process), resist process (wafer printing process), and etch process to determine the final physical pattern that would be formed on the wafer. Alternative methods include aerial image simulation only; aerial image simulation with an adjustable threshold model calibrated to emulate the real photoresist performance as a function of CD, pitch and local environment; and aerial image simulation with an adjustable threshold calibrated to emulate the pattern transfer after resist processing and etch as a function of CD, pitch, and local environment.

The simulation at the wafer level can include, therefore, not just the lithography (wafer printing) process, but the full pattern transfer process, including any, some combination, or all of the following: etch, polishing, film deposition or growth, and any other steps that affect the final structure and topography of the device. Lithography parameters for which simulated images may be generated at different values can also include degree of partial coherence, illumination mode, numerical aperture, lens aberrations (e.g., Zernike coefficients), resist parameters (e.g., thickness, development rate model, lumped parameter model, Dill coefficients, and thermal diffusion coefficients) and/or film parameters (e.g., substrate reflectivity, thickness, anti-reflection coating properties, etc.).

The simulation at the wafer level can also include electrical simulation of device performance in addition to physical simulation of the patterned structures. The electrical performance of the device—either parametric properties of selected regions of the circuit (e.g., resistance, capacitance, transistor performance, etc.), performance of localized regions of the circuit (e.g., phase lock loop frequencies, timing, etc.), or the simulated performance of the full circuit as intended in the end use application—can be used as the pass/fail criteria for the design and/or to select critical regions for further inspection, metrology, and/or process control. In one embodiment, the method may include altering the reticle design data based on results of the vPWQ method. In one such embodiment, the reticle design data may be altered by altering RET feature data of the reticle design data.

The simulation of the reticle design data printed on a wafer can be performed using parameters of multiple, different reticle manufacturing processes, and the simulation of the wafer printing can be performed using parameters for multiple, different exposure tools, etch tools, or other processes. Examination of the reticle design data for different processes and tools may be valuable since each tool or process will have different aberrations that impact the pattern transfer in different ways. The vPWQ simulations can then be used to determine the optimum combination of design, optical enhancements (e.g., OPC, RET, etc.), mask making process, and wafer manufacturing process. In one such embodiment, the method may include generating additional simulated images illustrating how the reticle design data will be printed on the reticle at different values of one or more parameters of the reticle manufacturing process. Such embodiments may also include selecting the different values of the one or more parameters of the reticle manufacturing process that produce a minimum number of design pattern defects on the reticle.

The vPWQ concept and data linkages to reticle and wafer inspection, CD control, and design optimization can also be performed using printed wafers based on die-to-database inspection. Although performing such printed wafer inspection involves making a reticle and printing wafers, such an embodiment of the vPWQ methods would still add value to the integrated circuit manufacturing process.

A system configured to perform the vPWQ methods described herein may appear to be similar to a state of the art KLA-Tencor reticle inspection system, but optionally without the reticle handling and optical systems. Such a system may include a user interface that can be used to define the inspection parameters and a computer system to handle the incoming reticle design data and render the simulated mask level from the data (i.e., to generate the first simulated image as described above). The system may also include a massively parallel computer system to simulate the mask to wafer pattern transfer under a range of focus and/or exposure conditions (i.e., to generate the second simulated images as described above).

If the second simulated images are generated for different values of focus and exposure of a wafer printing process, one or more of the computer systems described above may be configured to compare reference and test images for the full chip for each focus-exposure (F-E) combination and to identify locations that are defects under the conditions set in the inspection recipe. These defect locations may be compared between F-E settings, and defects that occur at the same location under multiple F-E conditions can be concatenated to a single defect. Each defect may be tagged with the range of focus and exposure conditions under which it prints as a defect in the simulated images. The defects may then be automatically prioritized for review and analysis. The highest priority would be assigned to those defects which occur closest to the nominal F-E conditions and/or those with the most limited range of non-defectiveness. A defect map may be presented to the user for review and classification, and an inspection report may be generated and stored for later review and/or additional analysis, either on-line (linked to the simulation engine) or off-line.

With the trend towards fabless design companies feeding their products to multiple foundries, the number of designs which can be verified using the vPWQ methods described herein is growing rapidly. Foundries may use multiple vPWQ tools to qualify all of their designs in a timely manner, as will IDMs with a wide range of products (telecommunications, wireless, consumer applications). In addition, the methods described herein may be performed using hardware that is similar to that used in currently available reticle inspection systems such as the TeraScan system, which is commercially available from KLA-Tencor, San Jose, Calif. In this manner, the methods described herein can be implemented without substantial development costs and may be made commercially available on currently available reticle inspection systems. Furthermore, the methods described herein may be performed on hardware that is linked to reticle inspection, wafer inspection, metrology and analysis tools such that data may be easily shared between systems.

FIG. 1 is a flow chart illustrating one example of a method for detecting defects in reticle design data. This method includes designing the circuit, as shown in step 10 of FIG. 1. The circuit may be designed using any method or system known in the art. The method also includes verifying the design, as shown in step 12. Verifying the design may include verifying the physical characteristics of the design. The physical verification can be performed using any method or system known in the art. As shown in step 14, the method includes determining if the circuit design passes or fails the physical verification. If the design fails the physical verification, the method includes re-designing the circuit and repeating the physical verification, which may include repeating steps 10, 12, and 14.

If the design passes the physical verification, the method includes generating a layout for the circuit, as shown in step 16. The layout of the circuit may be generated using any method or system known in the art. The method also includes verifying the layout of the circuit, as shown in step 18. The verification of the layout may include logical verification and/or design rule checking (DRC). The layout verification can be performed using any method or system known in the art. As shown in step 20, the method includes determining if the layout passes or fails verification. If the layout fails verification, the method includes changing the layout of the circuit and re-verifying the revised layout of the circuit, which may include repeating steps 16, 18, and 20.

If the layout passes verification, the method includes adding RETs to the circuit layout, as shown in step 22. This step is commonly referred to as “decorating” the circuit layout. Adding the RETs to the circuit layout may be performed in any manner known in the art. The RETs may include any RET known in the art. As shown in step 24, the method includes verifying the decoration. Verifying the decoration may include optical rule checking (ORC). As shown in step 26, the method includes determining if the decorated layout passes or fails verification. If the decorated design fails verification, the method includes changing the RETs in the decorated design and re-verifying the decorated design, which may include repeating steps 22, 24, and 26.

If the decorated design passes verification, the method includes making the mask, as shown in step 28. As shown in step 30, the method includes verifying the mask using mask inspection. The mask may be inspected using any system and method known in the art. As shown in step 32, the method includes determining if the mask passes or fails verification. If the mask fails inspection, the method includes determining if the mask is repairable, as shown in step 34. If the mask is determined to be repairable, the method includes repairing the mask, as shown in step 36, and then re-verifying the repaired mask, which may include repeating steps 30 and 32. If the mask is determined to not be repairable, the method includes scrapping the mask and optionally re-spinning the process, as shown in step 38.

If the mask passes verification, the method includes printing wafers, as shown in step 40. As shown in step 42, the method includes verifying the printed wafers. In one example, verifying the printed wafers may include PWQ wafer inspection, which may be performed as described above. As shown in step 44, the method includes determining if the printed wafers pass or fail verification. If the wafers fail inspection, the method includes determining if the defects in the reticle that caused the wafers to fail inspection can be repaired, as shown in step 46. If the defects of the reticle are repairable, the method includes repairing the mask, as shown in step 36, and the method may be continued after step 36 as shown in FIG. 1. If the defects on the reticle are determined to not be repairable, the method includes scrapping the mask and optionally re-spinning the process, as shown in step 38. If the wafers are determined to pass verification, the method includes releasing the reticle to production, as shown in step 48.

In the method shown in FIG. 1, any RET process window marginalities or any other reticle design defects are not detected until a wafer is printed. As such, if defects or marginalities are present in the reticle pattern, it is relatively expensive to scrap the printed wafer and to revise the parameters involved in one or more processes of the wafer print process (e.g., reticle design, reticle manufacturing process, wafer printing process, etc.). FIG. 2 is a flow chart illustrating one embodiment of a computer-implemented method for detecting defects in reticle design data. This method may, or may not, include many of the steps described and shown in FIG. 1. Those steps that may be included in both FIGS. 1 and 2 have been indicated using the same reference numerals and will not be described further herein. However, the method shown in FIG. 2 includes one important step that is not included in FIG. 1, which imparts significant advantages to the method shown in FIG. 2.

In particular, the method shown in FIG. 2 includes verifying the decoration of the reticle design, as shown in step 50, which unlike step 24 of the method shown in FIG. 1 includes vPWQ defect detection. vPWQ in step 50 may be performed as described herein. In addition, the vPWQ method performed in step 50 may be performed to detect defects in the reticle design data across a full predetermined process window for the wafer printing process that is to be used with the reticle. As such, in this method, any marginalities that are present in the reticle design can be advantageously detected before the mask is fabricated. The method shown in FIG. 2 may include any other steps described herein. For example, the method shown in FIG. 2 may include generating an inspection process for the reticle and/or generating an inspection process for the wafers. These inspection processes may be generated as described above and may be used in steps 30 and 42 to verify the reticle and wafers, respectively.

FIG. 3 is a flow chart illustrating examples of data flow between vPWQ and one or more of wafer inspection, reticle inspection, wafer metrology, and APC control in the fab. As shown in FIG. 3, history 52, which includes prior designs and models may be provided to synthesis step 54 in which the design may be created in an appropriate format such as RTL code or netlist format. Characteristics 56 of the integrated circuit such as timing, power, and signal integrity may be provided to the synthesis step to verify the design. Critical paths 58 in the design determined by verification can be provided to data “bus” 60.

Creation of the reticle design data may be performed in step 62. Creation of the reticle design data may include, for example, converting the netlist to GDS format. History 64 including, for example, prior designs and/or models may be provided to the creation step. In addition, logical verification step (LVS) 66 may be used to verify the reticle design data. Critical features 68 in the reticle design determined by LVS may be provided to data “bus” 60. OPC decoration of the reticle design may be performed in step 70 using calibration data 72 such as calibrated lithography models, critical dimensions, and/or other data. Decoration may include adding any RETs to the reticle design data. Physical verification step 74 may include verifying the decorated reticle design using a technique such as ORC. Critical OPC 76 or other critical RET determined by the physical verification step may be provided to data “bus” 60. In addition, physical verification step 74 may be performed using edge placement error (EPE) tolerance data 78 provided by data “bus” 60.

As shown in FIG. 3, after OPC decoration of the reticle design data, vPWQ defect detection may be performed in step 80. vPWQ may be performed in step 80 according to any of the embodiments described herein. One or more parameters for “Smart vPWQ” 82 may be provided to the vPWQ method by data “bus” 60. vPWQ may generate critical OPC information 84, which is provided to data “bus” 60. Depending on the results of the vPWQ method, mask making step 86 may be performed using calibration data 88 such as PSC, BKMs, aerial imaging measurement system (AIMS) calibration data, etc. After the mask is fabricated, mask verification step 90 may be performed on the mask fabricated in step 86. Mask verification step 90 may use SmartInspection data 92, which may be provided by data “bus” 60. This SmartInspection data may be generated by the vPWQ method performed in step 80. In addition, critical mask data 94 generated by the mask verification step may be provided to data “bus” 60.

In some embodiments, a second vPWQ method (vPWQ2) may be performed, as shown in step 96. vPWQ2 shown in FIG. 3 is an alternate embodiment of vPWQ that can be performed after mask inspection on real mask images (i.e., images of the fabricated reticle). In other words, vPWQ2 may be performed as described herein except with real mask images instead of simulated images of the reticle. vPWQ2 may be performed using one or more parameters for “Smart vPWQ” 98 from data “bus” 60. “Smart vPWQ” parameters 98 may or may not be the same as “Smart vPWQ” parameters 82. Critical OPC 100 or other critical RET generated by vPWQ2 may be provided to data “bus” 60.

Wafer fabrication step 102 may be performed after vPWQ2. Verification of the wafer fabrication step 104 may be performed using calibrated metrology tools 106, which may include any metrology tools known in the art. Verification of the wafer fabrication step 102 may be performed using “Smart Sampling” parameters 108 for the wafer inspection provided by data “bus” 60, which may be determined from, for example, critical paths 58, critical features 68, mask location data, critical OPC 76 and 100, etc. In addition, verification of the wafer fabrication step may be performed using automatic process control (APC) 110 information provided by data “bus” 60. APC information may be generated from the results of vPWQ and/or vPWQ2 as described herein.

FIG. 4 illustrates how multiple types of criticality (design, RET, mask making) may overlap in reticle design data such that patterns may suffer most at margins of the process window, which may limit the available process margin. In particular, design critical areas 112 are shown mapped in space 114, which represents the area of the reticle design data. Design critical areas 112 may be created or “tagged,” for example, by a designer based on electronic design automation (EDA) electrical simulation. In contrast, mask making critical areas 116 are shown separately in space 114. The mask making critical areas include regions with limited process window for the reticle manufacturing process. These critical areas may be created or “tagged” by the reticle inspection system used to inspect a fabricated reticle. More preferably, these critical areas may be determined by the vPWQ methods described herein.

Lithographic critical areas 118 are also shown separately mapped in space 114. The lithographic critical areas may include regions with limited process window for the wafer printing process. The lithographic critical areas may be identified and “tagged” by vPWQ simulation of the patterning process, which may be performed as described herein. It is to be understood that critical areas 112, 116, and 118 shown in FIG. 4 are merely presented as examples of the different critical areas. Obviously, the critical areas will vary depending on the reticle design data, the reticle manufacturing process, the wafer printing process, or some combination thereof.

Each of the critical areas described above may be combined in a single map as shown by space 120 to illustrate which areas in the reticle design data have multiple types of criticality. Areas that are critical for multiple reasons may be selected for intensive metrology and/or wafer level inspection to ensure yield. In particular, an inspection process for a reticle or wafer may be generated as described above, and the sensitivity of the inspection processes may vary from region to region in the reticle design data depending on the one or more reasons that each region qualifies as critical. For example, areas that exhibit two different types of criticality may be inspected with greater sensitivity than areas that exhibit only one type of criticality. In this manner, regions in the reticle design data with multiple types of criticality can be prioritized for wafer inspection, metrology, and CD control.

Additional methods described further herein may be used in the vPWQ methods described above and possibly in other reticle design defect detection methods. In particular, the methods described further herein provide improved methods for performing defect detection and other calculations described herein to reduce the number of detected defects which are not critical or important to the user to prevent the detection of these “nuisance” defects from obscuring the important defects. Additionally, the methods described further herein can be used to prioritize the order in which defects are reviewed and/or corrections are made to the design to improve the process window.

vPWQ was conceived to work just like PWQ, which is a wafer based inspection method disclosed in the patent application by Peterson et al., which is incorporated by reference above. On the wafers in PWQ, full fields are exposed at different focus and/or exposure conditions, and these test fields are compared to reference fields, which are exposed at best focus and exposure conditions. In general, the farther removed the test fields are from the reference fields, the more defects will be detected as printed features begin to fail to image properly. The focus and exposure conditions at which printed features image incorrectly thus define the limits of the usable process window for the device. vPWQ does essentially the same test to reference comparison, but on simulated images without making a mask and printing wafers. Therefore, the vPWQ method allows weak points in the reticle design to be identified and corrected before expensive masks are made and wafers are printed with the masks.

In performing a highly sensitive test-to-reference comparison, even small changes in the dimensions of the features may be interpreted as defects. As the focus and/or exposure conditions move away from the nominal best settings, the number of defects detected may become excessive. This problem can be mitigated by reducing the sensitivity of the inspection (test-to-reference comparison), but in that case some important defects may be missed.

It would be desirable to maintain the highest degree of sensitivity, but prioritize the defects based on the likelihood that they will lead to catastrophic imaging failures, not just small critical dimension (CD) errors. In other words, the important information may not be which features have changed by a few nanometers (nm) in CD. Instead, the important information is which features will change by an unacceptably large number of nm if there is a small change in focus and/or exposure and/or other process conditions. Thus, two features may have exactly the same absolute CD error, but one feature may be far more important than the other if it is susceptible to large additional changes with additional process variation. Therefore, wafer based PWQ and vPWQ described above may be modified as described further herein to discriminate between potential defects based on rate of change.

In particular, one embodiment of a computer-implemented method for detecting defects in reticle design data includes generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process. This generating step may be performed as in the vPWQ methods described above. This embodiment also includes generating second simulated images using the first simulated image, which may also be performed as in the vPWQ methods described above. In particular, the second simulated images illustrate how the reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. However, unlike the vPWQ methods described above, this embodiment includes determining a rate of change in a characteristic of the second simulated images as a function of the different values. In addition, the method includes detecting defects in the reticle design data based on the rate of change. In some embodiments, the detecting step may include using the rate of change in combination with the second simulated images to detect the defects in the reticle design data. For example, defect detection may be performed using rate of change in combination with the vPWQ results described above. These embodiments of this computer-implemented method may include any other step(s) described herein.

Another embodiment of a method for detecting defects in reticle design data printed on a reticle is a modified version of PWQ that includes printing images of the reticle on a wafer at different values of one or more parameters of a wafer printing process. The method also includes determining a rate of change in a characteristic of the images as a function of the different values. In addition, the method includes detecting defects in the reticle design data based on the rate of change. This embodiment of the method may include any other step(s) described herein.

The methods described herein, therefore, may include using not just the difference between the test CD and the reference CD to detect defects in the reticle design data as in vPWQ and PWQ, but also the rate of change of the test CD. Such defect detection can be accomplished in several ways, and the results can be used in several different ways, which are outlined below. The different methods of computing and using rate of change information can be used separately or in combination with each other as outlined below. In addition, although methods are described herein with respect to the rate of change in CD, it is to be understood that the rate of change information may be the rate of change in any measurable parameter of the test images (e.g., feature profile). Furthermore, although methods are described further herein with respect to different values of focus and exposure of a wafer printing process, it is to be understood that the methods described herein can be used for different values of these and/or any other parameters of the wafer printing process that may affect the reticle design data printed on the wafer.

One method of increasing vPWQ and PWQ sensitivity to rate of CD change is to change the reference used in defect detection. For example, instead of using the reference image simulated for nominal best focus and exposure conditions (E0, F0) as the reference for all comparisons with test images, each test image (En, Fn) can be compared to its nearest neighbors (e.g., other test and/or reference images that are closer to the nominal values at (E0, F0) than the test image). In other words, the detecting step of vPWQ may be performed by comparing one of the second or test simulated images to additional simulated images that illustrate how the reticle will be printed on the wafer at the different values that are closer to nominal values for the one or more parameters of the wafer printing process than the different values corresponding to the one second simulated image.

FIG. 5 shows one example of a layout that is currently used for defect detection in which each test image (En, Fn) is compared to the same nominal reference image (E0, F0). In particular, test images 120 are each compared to reference image 122. Such comparisons may be used for PWQ with images actually printed on a wafer. Alternatively, such comparisons may be used for vPWQ with simulated test and reference images. It is to be understood that although four test images are shown in FIG. 5, the defect detection method may use any number of test images.

FIG. 6 shows a new arrangement that can be used for reticle design defect detection in which each test image (En, Fn) 124 is compared to its 3 nearest neighbors (NN) 126, 128, and 130, all of which are simulated or printed for at least one parameter that is closer to the nominal values (E0, F0) than the test image. Such comparison of test and reference images is referred to herein as “cascading” test to reference defect detection. Such comparisons can be easily performed for vPWQ using images simulated for the different values of exposure dose and focus. This method can also be applied to wafer based PWQ by printing the wafer in an appropriate manner (e.g., by adding columns with offset focus and exposure conditions to be used as reference sites instead of the current configuration where all reference columns are exposed at nominal conditions).

In the example of FIG. 6, the 3 nearest neighbors are each used for comparison with the test image. Alternatively, the number of neighbors used for comparison with the test image could vary from 1 to 8. For one comparison, the user may select the nearest neighbor in terms of focus or exposure with the other parameter fixed or may select the diagonal nearest neighbor for which both focus and exposure changed. For more than 3 nearest neighbors, the test images that are farther removed from the nominal best focus and exposure conditions may be compared to the test image being examined thereby sampling the rate of change moving away from the preferred operating conditions. Although one or more of the comparisons are redundant (since a comparison would be repeated for the inspection of the outward neighbor), different weighting factors could be applied in the defect detection and/or prioritization algorithms. In addition, although 4 test images are shown in FIG. 6, it is to be understood that the methods described herein may use any number of test images for defect detection.

FIG. 7 illustrates one layout for dies printed on a wafer that can be used for PWQ defect detection. In this example, each test location is compared to a nominal reference image corresponding to best focus and exposure values for the wafer printing process, which are indicated in FIG. 7 by a 0. Each set of test conditions is checked 4 times in this arrangement. A test condition can vary in focus, exposure, or both.

FIG. 8 illustrates one layout of die images that can be printed on a wafer for different values of focus and exposure for PWQ defect detection or that can be simulated for the different values of focus and exposure for vPWQ defect detection. In this example, each test image is compared to another test image that is printed or simulated for value(s) of the wafer printing process parameter(s) that are closer to the nominal values than those of the test image being examined. Each test image may still be compared 4 times, as in FIG. 7, but far more values of the parameters can be tested with more sensitivity to the rate of change between settings. Some replication of the nominal conditions (0) may be printed on the wafer for calibration and background noise checks.

By performing such cascading test to reference defect detection, the defect detection algorithms will detect areas that are the most different from the neighboring exposure conditions (focus and/or exposure) thereby increasing the sensitivity of the inspection to the local rate of change in the CDs. Even if two test images have the exact same change in CD relative to the nominal conditions, if the CD of one of the test images changed slowly over multiple values of the parameters while the CD of another test image changed quickly between the most recent reference focus and the current test focus, the sensitivity of the inspection can be tuned to detect the CD of the test image that changed the quickest, and which is therefore likely to be most important to the user. For cases where the test image is compared to multiple reference images, weighting factors can be applied to the multiple comparisons to arrive at a final defect score. The final defect score can be used to determine if a test image is defective or not and to prioritize the effective size of the defect.

In addition, since the vPWQ method is based on simulation, vPWQ can be used to more accurately determine the rate of change of the critical dimensions as a function of focus and/or exposure (the “exposure conditions”). The determination of the rate of change can be performed in several ways. The most accurate method would be to compute the true derivative of the CD, dCD/dE and dCD/dF, for each feature at each combination of exposure conditions. Another method is to compute the slope of the aerial image, dE/dx, or the normalized image log slope (NILS) at the threshold energy for each feature and combination of exposure conditions (Eth). The smaller the slope or NILS, the more rapidly the CD will change with a change in exposure or process conditions. Therefore, this slope can be taken as an indication of the rate of change of the CD.

The slope or derivative data can be used independently as the sole criteria for determining if a feature is defective or not, or the slope and derivative can be used together with the test to reference comparison to prioritize the importance of the defects detected by the comparison algorithms. Similarly, the cascading test to reference comparison can be used independently, or in combination with, the test to nominal reference comparisons described above. These possible combinations allow the defects to be detected and/or prioritized based on the size of the defect alone, the rate of change of the defect alone, or a combination of size and rate of change. Weighting factors can be applied to the multiple terms used in this comparison to filter and/or prioritize defects. The weighting factors can be linear or non-linear, and the weighting algorithm can include cross-terms or higher power coefficients of the inputs. For example, the weighting for a 2 nm CD error could vary depending on whether the rate of change of the CD is high or low, while on the other hand, the weighting for a 10 nm CD error can be set to be high regardless of the rate of change.

Any of the options described above can be used independently or in combination. For clarity, the possible options are numbered, and the combinations of the options that would enhance the value of the inspection are listed below.

Option 1: Test to reference comparison with the reference always at the nominal operating point

Option 2: Compute derivatives of the CD with respect to dose and/or focus

Option 3: Compute the spatial derivative of the aerial image and/or NILS

Option 4: Cascading test to reference comparisons

Option 1 alone is essentially the same as the comparison that may be performed in the defect detection step of vPWQ and PWQ. Options 2, 3, or 4 could each be used independently in place of Option 1. The interesting combinations are then:

Options 1 and 2; 1 and 3; or 1, 2, and 3

Options 4 and 2; 4 and 3; or 4, 2, and 3

Options 1 and 4; 1, 4, and 2; 1, 4, and 3; or all 4 options together.

In any of these combinations, the different options can have a greater or lesser influence on the defect filtering or prioritization depending on the weighting factors that are applied.

The use of CD rate of change information in addition to absolute CD error data as described above allows improved detection of regions of the design and/or reticle that will be most prone to process window limiting failures and pattern dependent yield loss. The rate of change data allows for higher sensitivity to be applied to the inspection (either physical or virtual), without flooding the detection system with an impractically large number of defect detections, thus enhancing the usable sensitivity of the system.

Derivatives generally cannot be readily computed from physical wafers used for wafer based PWQ, but the normal test to reference and cascading test to reference comparisons can also be combined for enhanced PWQ. In one example, instead of the current BABA or BBABBA layout, where B is the reference at nominal best focus and exposure and A is the test case, a cascading approach would have a layout with an ABCDEFGH pattern, where each exposure would have it's settings offset slightly from the previous field, making this layout more sensitive to small changes in pattern fidelity vs. process conditions. This layout also provides more possible test conditions on a wafer. For arbitration purposes, the defect would be assigned to the field with settings farthest from nominal. Any random errors caused by this rule would simply be removed when stacking the multiple replications of each set of test conditions. The same concept can be applied to the BBA type arrangement.

FIG. 9 is a flow chart of another embodiment of a computer-implemented method for detecting defects in reticle design data. As shown in FIG. 9, this embodiment includes system design and verification, as shown in step 132. System design and verification can be performed using design data 134. In addition, the system design that is verified in step 132 may be provided to design data 134. System design and verification may be performed using any system and method known in the art. The method also includes logic design and verification, as shown in step 136. Logic design and verification 136 may be performed using design data 134 that was generated by system design and verification step 132. In addition, the logic design that is verified in step 136 may be provided to design data 134. Logic design and verification may be performed using any method and system known in the art.

The method includes physical design and verification, as shown in step 138. Physical design and verification may be performed in step 138 using design data 134 that was verified in step 136. Physical design and verification may be performed using any method and system known in the art such as DRC and LVS. In addition, the physical design that is verified in step 138 may be provided to design data 134. As shown in step 140, the method includes mask data preparation. Mask data preparation may be performed using design data 134 and lithography model 142. Mask data preparation may be performed using any method or system known in the art. The mask data may be provided to geometry data 144.

Instead of performing an optical rule check on the geometry data, the method includes vPWQ, as shown in step 146. vPWQ is performed using the mask data generated in step 140 (the results of which may be obtained from geometry data 144) and lithography model 142. vPWQ may also be performed according to any of the embodiments described herein. As described further herein, vPWQ may use the mask database as input and perform a full-die F-E matrix calculation. This calculation may be performed relatively quickly using the system described above. For instance, for 5 different focus values and 7 different exposure values, the calculation may be performed in about 10 hours for a 90 nm generation reticle design. The version of the vPWQ method that was used to perform this calculation detected a relatively large portion of CD defects (about 30% of all CD defects) and detected all catastrophic events such as shorts, opens, and printing SRAF. Obviously, these results were generated by only one version of the vPWQ method, and the defect detection results may be tailored and/or optimized as described above.

Output from the vPWQ method may be provided to the mask write, which is performed in step 148. The mask write process may also use geometry data 144 to perform all steps involved in printing the reticle design data on the reticle. The method includes performing mask metrology on the fabricated mask, as shown in step 150. Mask metrology may be performed using any system and method known in the art. The method also includes inspection of the fabricated mask, as shown in step 152. Mask inspection may be performed using geometry data 144. Mask inspection may be performed using any method and system known in the art.

Depending on the results of the mask metrology and inspection (if the mask passes qualification specifications), the method includes printing the mask on a wafer, as shown in step 154. Printing the mask on the wafer may include using any system and method known in the art. The method also includes wafer metrology, as shown in step 156. Wafer metrology of the printed wafers may include any method or system known in the art. Results of wafer metrology may also be provided to lithography model 142. The results of the wafer metrology may be used to calibrate and/or update the lithography model. As shown in step 158, the method includes wafer inspection. Wafer inspection may be performed using any system and method known in the art. The method shown in FIG. 9 may also include any other step(s) described herein.

FIG. 10 is a flow chart of a different embodiment of a computer-implemented method for detecting defects in reticle design data. In particular, FIG. 10 illustrates one embodiment of a vPWQ method that may be used in any of the methods described herein. As shown in FIG. 10, reticle design and RET decoration data 160 may be used to generate reticle data 162. In this manner, reticle data 162 may include the decorated reticle design data. In addition, fab model data 164 may be generated using lithography data 166 such as scanner parameters, resist parameters, and predetermined process window (such as focus and dose range) that can be used to determine which different values of one or more parameters of the wafer printing process for which simulated images will be generated.

Reticle data 162 and fab model data 164 are provided to vPWQ module 168. vPWQ module 168 may include any hardware and/or software that can be used to generate the simulated images as described above using reticle data 162 and fab model data 164. In one embodiment, the vPWQ module may include a simulation engine such as that included in the PROLITH software. The simulation engine may be configured to generate the first and second simulated images as described herein. In another embodiment, the vPWQ module may be configured as a system that includes a simulation engine as described above coupled to a processor. The processor may be configured to detect defects in the reticle design data using the second simulated images according to any of the embodiments described herein. The vPWQ method performed by vPWQ module 168 may include any other step(s) described herein. The vPWQ module may be further configured as described herein.

As shown in FIG. 10, vPWQ module 168 generates output 170 that includes an error list. The error list may include all potential defects that were detected by the vPWQ module. One or more additional functions may be performed on output 170 by either the vPWQ module or another software module or other hardware. For example, potential defects in the error list may be examined to determine if the potential defects are actual defects, what kind of defects the potential defects are, etc. In addition, the output may be used to determine the process window that can be used with the reticle design data. Determining the process window for a wafer printing process to be used with the reticle may be performed as described above. In addition, the output may be formatted for presentation to a user, use by another software module, storage in one or more modules such as a fab database, etc. The method shown in FIG. 10 may include any other step(s) described herein.

FIG. 11 is a flow chart of an additional embodiment of a computer-implemented method for detecting defects in reticle design data. As shown in FIG. 11, mask layer data 172 is modified by RET decoration 174 and data fracture 178. The modified mask layer data is used to generate mask writer data 178. Mask writer data 178 is provided to vPWQ module 180. For example, mask writer data 178 may be provided to input database 182 of vPWQ module 180. The vPWQ module may also include a model describing the reticle manufacturing process. This model may include mask writer model 184. The vPWQ module may use mask writer model 184 with mask writer data 178 in input database 182 to generate a first simulated image illustrating how the mask writer data will be printed on a reticle using the reticle manufacturing process.

The vPWQ module may also include one or more models describing the wafer printing process. These models may include scanner model 186 and resist model 188. In addition, different values 190 of one or more parameters of a wafer printing process may be provided to input database 182. These one or more parameters may include, for example, focus F and exposure E. In addition, the different values of the one or more parameters provided to input database 182 may include nominal values (e.g., F0, E0) for the parameter(s). The different values of the one or more parameters provided to input database 182 may also include test values (e.g., Fn, En). These test values may include values that are within a predetermined process window for the reticle. In some embodiments, these test values may span the predetermined process window.

The vPWQ module uses scanner model 186, resist model 188, the first simulated image, and different values 190 to generate second simulated images 192. The second simulated images illustrate how the mask writer data printed on the reticle will print on a wafer at the different values of the one or more parameters of the wafer printing process. The second simulated images may also illustrate how the entire chip will be printed on the wafer at the different values of the one or more parameters of the wafer printing process. In this embodiment, vPWQ module 180 may also generate reference simulated image 194 using scanner model 186, resist model 188, the first simulated image, and the nominal vales for the parameters(s) of the wafer printing process. Reference simulated image 194 is compared to second simulated images 192 to determine differences 196 between the simulated images. The vPWQ module may use tolerance specifications 198 to determine what qualifies as a difference. The differences between the compared simulated images may be used to detect defects in the reticle design data as described further herein.

In some embodiments, instead of, or in addition to, detecting defects in the reticle design data using simulated images that illustrate how the reticle design data will be printed on a wafer by a wafer printing process, defect detection may be performed using simulated images that illustrate the pattern on the wafer after a different semiconductor manufacturing process. For example, in one embodiment, vPWQ module 180 may include etch model 200. Etch model 200 describes an etch process that will be performed on the wafer after the reticle design data is printed on the wafer by the lithography process. vPWQ module 180 may use etch model 200 in combination with the second simulated images to generate additional simulated images that illustrate how the reticle design data will be printed on the wafer by the etch process. These additional simulated images may be compared to a reference simulated image to detect differences between the simulated images as described above. The differences between the simulated images may be used to detect defects in the reticle design data. Similar image simulation and defect detection may also or alternatively be performed by the vPWQ module for any other processes that will be performed on the wafer and that may affect the pattern printed on the wafer. Such processes may include, for example, deposition and chemical-mechanical polishing.

vPWQ module 180 generates output 202 based on differences 196 between simulated images 192 and reference simulated image 194. Output 202 may include coordinates of the differences between the simulated images, portions of the simulated images (test and/or reference) corresponding to the positions of the differences, a database clip, a process window determined for the reticle design data, and/or the severity (e.g., the magnitude) of the differences detected between the different simulated images. vPWQ module 180 may also be configured to allow one or more user actions 204 to be performed based on output 202. The user actions may include, for example, rejection of the reticle design data, selection of additional simulation to be performed by the vPWQ module, adjustment of one or more parameters of the vPWQ module, and/or alteration of the rules used by the vPWQ module. The method illustrated in FIG. 11 may include any other step(s) described herein.

FIG. 12 is a flow chart illustrating yet another embodiment of a computer-implemented method for detecting defects in reticle design data. In particular, FIG. 12 illustrates different points in a semiconductor manufacturing process at which some form of PWQ can be performed. For example, as shown in FIG. 12, this method may include performing vPWQ 206 on mask layer database 205. After the mask layer database is modified by RET decoration 210, vPWQ 208 may be performed on the decorated mask layer data. After vPWQ 208, the decorated mask layer data may be used to generate reticle layout 212. Reticle layout 212 is used to perform data fracture 214. After data fracture 214, vPWQ 216 may be performed on the fractured data. vPWQ 206, 208, and 216 may be performed as described herein.

After vPWQ 216 is performed, the mask may be manufactured as shown in step 218. After the mask is manufactured, the method may include inspecting the fabricated mask, as shown in step 220. Inspecting the fabricated mask may include vPWQ 222 using an image of the fabricated mask. In other words, vPWQ 222 may be performed as described herein with the exception that instead of using first simulated images to generate the test simulated images, in vPWQ 222, an image of the actual mask may be used to generate the test simulated images. After inspection of the mask, assuming that the mask passes qualification, the mask is received by the production facility, as shown in step 224. When the mask is received by the production facility, vPWQ 226 may again be performed using an image of the fabricated mask as described above.

The method also includes printing wafers using the fabricated mask, as shown in step 228. After the wafers are printed, vPWQ 230 may be performed using images of the actual printed wafers. In other words, vPWQ 230 may be performed as described herein with the exception that the second simulated images may be replaced with images of the printed wafers. After vPWQ 230 has been performed, the method may include etching the printed wafers, as shown in step 232. After the printed wafers have been etched, vPWQ 234 may be performed using images of the actual etched wafers. In other words, vPWQ 234 may be performed as described herein with the exception that the second simulated images may be replaced with images of the etched wafers. In addition, vPWQ may also be performed after other steps of the semiconductor manufacturing process. In this manner, the vPWQ methods described herein have application at many different points throughout a semiconductor manufacturing process, as shown in FIG. 12. The method shown in FIG. 12 may include any other step(s) described herein.

A system configured to perform one or more of the computer-implemented methods described herein includes a computer system. The computer system may be configured as described above. The system also includes a carrier medium. The carrier medium may be coupled to, or included in, the computer system using any method or device known in the art. Program instructions implementing methods such as those described herein may be transmitted over or stored on the carrier medium. The carrier medium may be a transmission medium such as a wire, cable, or wireless transmission link. The carrier medium may also be a storage medium such as a read-only memory, a random access memory, a magnetic or optical disk, or a magnetic tape.

In an embodiment, the computer system may be configured to execute the program instructions to perform a computer-implemented method according to any of the above embodiments. In general, the term “computer system” may be broadly defined as any device having one or more processors, which executes instructions from a memory medium.

The program instructions may be implemented in any of various ways, including procedure-based techniques, component-based techniques, and/or object-oriented techniques, among others. For example, the program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (“MFC”), or other technologies or methodologies, as desired. The system may be further configured as described herein.

In general, the methods and systems described above can be used to perform a process window inspection to determine regions of reticle design data (e.g., a semiconductor chip design) that are most prone to fail at different values of one or more parameters of a wafer printing process (e.g., different values of stepper focus and exposure) around the nominal values for the one or more parameters. Prior to development of these methods and systems, a PWQ experiment would be performed to understand the tradeoffs between the different values of the one or more parameters. As described further above, PWQ experiments generally involve printing wafers at different focus and exposure values and measuring one or more characteristics such as CD of various patterned features formed on the wafers and inspecting the wafers for defects.

The concepts described above may be implemented much more broadly. For instance, there are many more parameters than those described above that can impact the printing of reticle design data on wafers, and all such parameters can be considered by simulation and for control. With an understanding of the tradeoffs in the individual error budgets for the various parameters that affect the printing of the reticle design data on wafers, which can be determined as described further herein, the most efficient process choices can be made, both for the wafer fabrication process and the reticle design data.

One embodiment for creating a wafer fabrication process includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. The simulated images may be generated according to any of the embodiments described herein. For instance, in one embodiment, the method includes generating the simulated images by generating a first simulated image illustrating how the reticle design data will be printed on a reticle using a reticle manufacturing process and generating the simulated images using the first simulated image. Therefore, the simulated images used in the methods described further herein may be the second simulated images described above and generated according to any of the embodiments described herein.

In one embodiment, the different values for which the simulated images are generated span a predetermined process window for the different parameters. The predetermined process window may be determined as described above. Alternatively, the different values for which simulated images are generated may be determined arbitrarily or based on knowledge of the process tools and/or materials that will be used for the wafer fabrication process.

The overall error budget for the wafer fabrication process may be predetermined based on the design of the device being fabricated on the wafer. For instance, predetermined characteristics of the device (e.g., electrical characteristics) and selected process yield (e.g., bin yield) may be used to determine the overall error budget. The overall error budget may be defined in a number of manners such as the acceptable variation in the physical characteristics of the design printed on the wafer. For example, the overall error budget may be defined for CD as 150 nm+/−5 nm. Different CD error budgets may be defined for different patterned features in reticle design data printed on the wafer at the same time. In another example, the overall error budget for feature placement on the wafer may defined as the selected location +/−10 μm. Obviously, these are only examples of overall error budgets for a wafer fabrication process, and the overall error budget may be determined based on the predetermined characteristics of the device and the selected process yield. The overall error budget may be determined by the device designer or the tool used to create the device design based on characteristics of the device design, the amount of tolerance of the device design to variations in the wafer fabrication process, and the amount of tolerance of the device to variations in the reticle design data printed on the wafer.

The overall error budget may also be defined differently for different processes (e.g., lithography and etch). However, the overall error budget may often be defined with respect to the physical characteristics of the reticle design data printed in a device material on the wafer (e.g., as opposed to a resist material on the wafer). For instance, instead of defining the overall error budget for a wafer fabrication process based on post-lithography characteristics of the wafer such as dimensions of resist features formed on the wafer, the overall error budget for the wafer fabrication process may be defined by post-etch characteristics of the wafer such as the characteristics of the features in the reticle design data etched into a device material such as an insulating layer or a conductive layer.

One of the significant challenges for wafer and device manufacturers is determining a wafer fabrication process that has an overall error budget for a particular device design that is equal to or less than the predetermined overall error budget. Creating a wafer fabrication process is not trivial for a number of reasons. For example, several different processes are used to print reticle design data on a wafer such as device design, reticle manufacturing, lithography, and etch processes. The performance of each of these processes will affect the performance of all subsequently performed processes. For example, the performance of the device design, reticle manufacturing, and lithography processes affects the performance of the etch process. In addition, within each process, different parameters of the processes may have interrelated effects on characteristics of the fabricated wafer. For example, in a lithography process, exposure dose and post exposure bake (PEB) temperature both affect the width of features in the reticle design data printed on a wafer after the lithography process. Therefore, since these parameters have an interrelated effect on the dimensions of the features printed on a wafer by the lithography process, the individual error budgets of these parameters have a combined effect on the overall error budget of the lithography process.

In some embodiments, to the extent that different parameters of a wafer fabrication process can be separated based on whether the parameters independently affect how the reticle design data will print on a wafer, the individual error budget for one or more parameters of the wafer fabrication process may be determined independently. For instance, simulated images that illustrate how the reticle design data will be printed on the wafer at different values of a parameter of the wafer fabrication process and at constant values of other parameters of the wafer fabrication process may be generated as described herein. The constant values may be selected to be, for example, nominal or best known values. The simulated images may be evaluated (e.g., by quantifying one or more characteristics of the reticle design data in the simulated images) to determine which values of the parameter resulted in reticle design data that falls within the overall error budget for the wafer fabrication process. The range of those values that resulted in simulated images that include reticle design data within the overall error budget may be determined as the full individual error budget for the parameter.

Quantifying one or more characteristics such as CD of the reticle design data illustrated in the simulated images may result in identification of “defects” in the reticle design data. For example, features of the reticle design data having characteristic(s) that fall outside of the overall error budget may be considered defective. Therefore, the detection of such defects is analogous to defect detection based on metrology-type analysis of a physical wafer. However, in another embodiment, the method may include detecting defects in the simulated images, which may be performed in a manner that is analogous to defect detection based on inspection-type analysis of a physical wafer. Such defects may include defects that may not be detected by the analysis described above. For example, the method may include comparing the simulated images to a reference image such as a simulated image at the best known value of the parameter or an image representing how the reticle design data would ideally be printed on the wafer. Such a comparison for defect detection on physical wafers is often referred to as “die-to-reference die” defect detection. The method embodiments described herein may include using any other suitable methods and/or algorithms for defect detection using the simulated images.

In such embodiments, determining the individual error budget for the parameter may include determining the individual error budget based on the overall error budget and the defects in the simulated images. For example, characteristics of the defects such as the type of defects (e.g., bridging between two features, missing features, etc.), size of the defects (e.g., size of the bridging between two features), shape (e.g., shape of the bridging between two features), severity of the defects (e.g., a partial bridging or a complete bridging, estimated kill ratio or kill probability, estimated impact on device characteristics, estimated impact on yield, etc.), context of the defects (e.g., portion of the reticle design data in which the defects are located), and the like may be determined from the defect detection results. One or more of these characteristics and values of the parameter corresponding to the simulated images in which the defects appear may be evaluated to determine at which values of the parameter unacceptable defects appear. This information about the defects and the overall error budget, possibly in combination with the metrology-type analysis results described above, may be used to determine the individual error budget of the parameter.

In other embodiments, the individual error budgets for two or more parameters of a wafer fabrication process may be determined collectively. For instance, the different values of each of the two or more parameters that are selected for evaluation may be used to define all possible combinations of values of the two or more parameters. A simulated image that illustrates how the reticle design data will be printed on the wafer at each of the possible combinations of values of the two or more parameters may be generated as described herein. The simulated images may be evaluated (e.g., by quantifying one or more characteristics of the reticle design data in the simulated images and/or by detecting defects in the simulated images) to determine which of the possible combinations of values resulted in reticle design data that falls within the overall error budget for the wafer fabrication process. The range of values corresponding to the combinations that resulted in simulated images that include reticle design data within the overall error budget may be used to determine the individual error budgets for each of the parameters. Such embodiments may also include detecting defects in the simulated images and determining the individual error budgets based on the overall error budget and the defects in the simulated images, which may be performed as described further above. In addition, the evaluation described above may be used in combination with defect detection results to determine the individual error budgets for two or more parameters of a wafer fabrication process collectively.

For a wafer fabrication process, the individual error budgets for some of the parameters of the wafer fabrication process may be determined independently, and the individual error budgets for other parameters of the process may be determined collectively. Whether the individual error budget for each parameter is determined independently or collectively may be determined based on which parameters have interrelated effects on how the reticle design data will be printed on a wafer. Parameters that have interrelated effects on the printing of the reticle design data may be identified based on prior knowledge about the parameters of the wafer fabrication process, simulation results, or experimental results.

In one embodiment, the wafer fabrication process for which the individual error budgets are determined includes a lithography process. In another embodiment, the wafer fabrication process includes an etch process. In addition, individual error budgets for different parameters of a single process (e.g., a lithography process or an etch process) may be determined as described herein. Furthermore, the wafer fabrication process for which the individual error budgets are determined may include any other process involved in the wafer fabrication process or that has an effect on the reticle design data printed on a wafer such as, but not limited to, a device design process and a reticle manufacturing process. The term “device design process” is generally defined herein as the process (which may include a number of sub-processes) that creates the reticle design data.

Although such an approach may be relatively simple and quick, as noted above, the performance of any particular wafer fabrication process may be dependent upon the wafer fabrication processes that are performed prior to the particular process. Therefore, in some embodiments, the methods described herein may be performed for a combination of individual processes that have some effect on the characteristics of the reticle design data printed on the wafer. For example, in one embodiment, the wafer fabrication process for which individual error budgets are determined as described herein includes a device design process, a reticle manufacturing process, and a lithography process. Therefore, in such an embodiment, the individual error budgets are determined for different parameters of the device design, reticle manufacturing, and lithography processes based on the overall error budget for the wafer fabrication process and simulated images that illustrate how the reticle design data will be printed in a resist material on the wafer at different values of the different parameters. Such an embodiment may be particularly suitable for instances when the overall error budget is defined by post-lithography characteristics of the reticle design data printed on the wafer or the performance of the lithography process is of interest.

As noted above, however, often, the overall error budget is defined by the characteristics of the reticle design data as printed in a device material post-etch. As such, in some embodiments, the wafer fabrication process for which individual error budgets are determined as described herein includes a device design process, a reticle manufacturing process, a lithography process, and an etch process. In this manner, in such embodiments, the individual error budgets are determined for different parameters of each of these processes based on the overall error budget for the wafer fabrication process and simulated images that illustrate how the reticle design data will be printed in a device material on the wafer at different values of the different parameters.

In some embodiments, the different parameters of the wafer fabrication process for which individual error budgets are determined in the method embodiments described herein include all parameters of the wafer fabrication process that can alter how the reticle design data will be printed on the wafer. For example, every parameter of the wafer fabrication process has some error associated with it, and how the individual error budgets for each of the parameters affect the reticle design data printed on a wafer can be determined as described herein. Therefore, the methods described herein are advantageous over other methods in which only a subset of parameters (e.g., stepper focus and exposure) are considered. In particular, the use of simulation to model the variations of reticle design data printability across stepper focus and exposure values is already proving its value. However, many more parameters can be varied by a simulation engine in addition to those described above. These other parameters can be included in the simulation either through a physical understanding (e.g., an empirical model based on scientific theory) of the effects of the parameters on how the reticle design data will be printed on a wafer or through calibration of the model using analysis results for actual wafers printed with a variety of reticle design data and for different values of the different parameters. In other words, all parameters of the wafer fabrication process that have at least some effect on how the reticle design data will be printed on a wafer and that can be included in a model that can be used for generating the simulated images can be evaluated as described herein.

Parameters that can impact the printability of reticle design data on wafers and that may be evaluated as described herein include, for example, resist parameter variations (errors) such as thickness, chemistry, processing, indices of refraction (n), and absorption (k), reticle parameter variations (errors) such as bias (including non-linear line-width-dependent bias), corner rounding, figure offset (which may be determined using bias), phase (for phase shifting masks), and attenuation (for attenuating phase shift masks), optical parameters such as aberrations (in addition to focus and exposure dose), and any combination thereof. A more extensive list of parameters that can impact the printability of reticle design data on wafers and that may be evaluated as described herein include the following list of parameters and the units in which they may be expressed taken from the PROLITH full physical model parameters. Additional information about the parameters listed herein can be found in literature related to the PROLITH family of products, which are commercially available from KLA-Tencor, or in literature relating to wafer fabrication processes (Carl: any specific reference (publicly available) that you want to mention here?).

Film Stack Parameters:

    • Layer 1:
      • Thickness (nm)
      • Absorption Parameter A (1/μm)
      • Absorption Parameter B (1 μm)
      • Rate Constant C (cm2/mJ)
      • Unexposed Refractive Index (real)
      • Exposed Refractive Index (real)
      • Refractive Index Change on Expose (real)
      • Refractive Index Substrate (real)
      • Refractive Index Substrate (Imaginary)

Resist Parameters:

    • Resist Type: (e.g., Positive Chemically Amplified)
    • Resist Material:
    • Developer:
    • Resist Thickness (nm)
    • Absorption Parameter A (1/μm)
    • Absorption Parameter B (1 μm)
    • Rate Constant C (cm2/mJ)
    • Unexposed Refractive Index (real)
    • Exposed Refractive Index (real)
    • Refractive Index Change on Expose (real)
    • Thermal Decomposition Activation Energy (kcal/mol)
    • Thermal Decomposition Ln(Ar) (1/sec)
    • PEB Acid Diffusivity Activation Energy (kcal/mol)
    • PEB Acid Diffusivity Ln(Ar) (nm2/sec)
    • PEB Base Diffusivity Activation Energy (kcal/mol)
    • PEB Base Diffusivity Ln(Ar) (nm2/sec)
    • Amplification Reaction Order
    • Amplification Reaction Activation Energy (kcal/mol)
    • Amplification Reaction Ln(Ar) (1/sec)
    • Diffusion-Controlled Reaction Activation Energy (kcal/mol)
    • Diffusion-Controlled Reaction Ln(Ar) (1/sec)
    • Acid Evaporation Activation Energy (kcal/mol)
    • Acid Evaporation Ln(Ar) (1/sec)
    • Bulk Acid Loss Activation Energy (kcal/mol)
    • Bulk Acid Loss Ln(Ar) (1/sec)
    • Relative Quencher Concentration
    • Room Temperature Diffusion Length (nm)
    • Acid Diffusivity Variation
    • Reacted/Unreacted Acid Diffusivity Ratio
    • Exponential Acid Diffusivity Factor
    • Base Diffusivity Variation
    • Development Rmax (nm/s)
    • Development Rmin (nm/s)
    • Development Rresin (nm/s)
    • Development n
    • Development I
    • Relative Surface Rate
    • Inhibition Depth (nm)

Coat and Prebake

    • Prebake time (sec)
    • Prebake Temperature (° C.)

Imaging Tool

    • Source Shape:
    • Illumination Spectrum:
    • Pupil Filter:
    • Aberrations:
    • Illumination Polarization:
    • Immersion Enabled:
    • Wavelength (nm)
    • Wavelength Range (nm)
    • Numerical Aperture
    • Reduction Ratio
    • Flare
    • Annular Inner Sigma
    • Annular Outer Sigma

Exposure and Focus

    • Exposure (mJ/cm2) (e.g., 46)
    • Focus (μm) (e.g., 0)

Post Exposure Bake

    • PEB Time (sec)
    • PEB Temperature (° C.)
    • Contaminant Surface Concentration
    • Contaminant Diffusion Length (nm)

Development

    • Develop Time (sec)

Etch

    • Number of Etch Stages
    • Stage 1
      • Etch Time (sec)
      • Ion Spread (deg.)
      • Horizontal Rate (nm/sec)
      • Vertical Rate (nm/sec)
      • Horizontal Rate (nm/sec)
      • Vertical Rate (nm/sec)
      • Faceting
        The above list of parameters is not meant to be a complete list of all possible parameters that can be evaluated in the methods described herein. For example, different parameters and different sets of parameters that can be evaluated in the methods described herein include any other parameters included in any theoretical models of the wafer fabrication process known in the art or other models included in other commercially available simulation products known in the art.

Furthermore, although the above list includes parameters of a lithography process and an etch process, as described above, the wafer fabrication process that is created by the method embodiments described herein may include a device design process and a reticle manufacturing process. Therefore, the parameters for which individual error budgets are determined in the method embodiments described herein may include any parameters of the device design process and/or the reticle manufacturing process. However, instead of determining individual error budgets for the device design process and the reticle manufacturing process, the characteristics of the reticle used to generate the simulated images may be selected arbitrarily or based upon expected characteristics of the reticle. Examples of such characteristics are listed above as reticle parameter variations (errors). Therefore, in some embodiments, the different parameters for which individual error budgets are determined include different characteristics of the reticle design data.

The method embodiments described herein may also include determining individual error budgets for all of the different parameters listed above or only some of the parameters listed above. For example, some of the values of the parameters such as resist type and resist material may be fixed in the steps described herein. However, the method embodiments described herein can be used to create a wafer fabrication process by determining individual error budgets for a relatively large number of different parameters of the wafer fabrication process, particularly in comparison to the number of different parameters of the process that can reasonably be evaluated experimentally. In addition, the method embodiments described herein can determine individual error budgets for a relatively large number of different parameters of the wafer fabrication process substantially quicker and at substantially lower cost compared to experimental evaluation of the same number of different parameters.

The method embodiments described herein also include creating the wafer fabrication process based on the overall error budget and the individual error budgets. In one embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget and the individual error budgets. For example, based on the overall error budget and the individual error budgets, for a parameter of the wafer fabrication process such as temperature of the PEB step, the method may include selecting an operating set point of 130° C. and a level of control of +/−0.5° C. Obviously, these are merely examples of an operating set point and a level of control for one parameter of a wafer fabrication process, and the selected operating set points and levels of control will vary depending on the overall error budget and the individual error budgets.

Individual error budgets of parameters of the wafer fabrication process that are relatively independent of each other generally add in quadrature. Therefore, the operating set points and levels of control for independent parameters of the wafer fabrication process may be selected based on the individual error budget values of the independent parameters that add in quadrature to an overall error budget value that is less than or equal to the predetermined overall error budget. In this manner, the individual error budget values used to create the wafer fabrication process may be less than or different than the full individual error budget values determined as described above. The operating set points and levels of control may be selected based on these individual error budget values. For instance, the median values of the parameters corresponding to these individual error budget values may be selected as the operating set points for the parameters, and the range of the values on either side of the median value within the independent error budget values may be used to select the level of control for the parameters.

In some embodiments, creating the wafer fabrication process includes modifying predetermined (i.e., pre-selected or initial) operating set points for the different parameters based on the overall error budget and the individual error budgets. In this manner, the methods described herein may modify nominal set points of some parameters to make the design more robust based on the analysis. For example, the method may determine from the error budget analysis that the interaction between two parameters makes a nominal set point close to one edge of the process window. The interaction may be, for example, the interaction of exposure and mask bias that leads to CDs that are larger than the desired value. To create a more robust process, the method can modify the set point of one (or both) of the parameters to better center the nominal condition or operating set point within the process window. For example, the mask bias or the exposure set point may be decreased in the previous example.

In another embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget and how variations in the individual error budgets affect how the reticle design data will be printed on the wafer. In other words, the wafer fabrication process may be created based on how the individual error budgets of each of the different parameters impact the overall error budget or performance of the wafer fabrication process. For example, relatively small errors in some parameters of a wafer fabrication process may cause relatively dramatic changes in how the reticle design data will be printed on a wafer, which may indicate that relatively tight control of such parameters is relatively important to successful printing of the reticle design data on wafers. In one particular example, the mask error enhancement factor (MEEF) can be generally defined as the ratio of the wafer error to the reticle error. In this manner, if there is a region of high MEEF in the design, then a small error on the reticle can translate into a large error on the printed wafer. Therefore, regions of high MEEF in the design can be determined from the simulated images as described above. For instance, the rate of change in one or more characteristics of the reticle design data in the simulated images may be determined as a function of the rate of change in a parameter of the wafer fabrication process. Such information may be used to determine how the individual error budgets will affect the reticle design data printed on a wafer and to select how tightly the parameters should be controlled.

In another example, one or more characteristics of the reticle design data in the simulated images may be determined to change much more quickly at the outer limits of the individual error budgets. For instance, at the outer limits of an individual error budget for a parameter such as focus of an exposure step of a lithography process, the dimensions and/or shape of the reticle design data in the simulated images may change relatively rapidly across a relatively small range of values of focus compared to the change in those characteristics across values of focus located more centrally within the individual error budget. In one such instance, to avoid the potentially large variations in the reticle design data printed on a wafer if the focus is allowed to drift across the entire range of focus values that fall within the full individual error budget, the level of control selected for the focus may be smaller than that which corresponds to the full individual error budget determined for focus such that the focus is more tightly controlled. In this manner, the characteristic(s) of the reticle design data may be more uniform from wafer-to-wafer.

Using the full range of parameters that can impact the printing of reticle design data on a wafer allows the full individual error budget for each of the parameters to be determined by considering their mutual interaction. For example, in one embodiment, the individual error budget for one of the different parameters is determined as a function of the individual error budget for another of the different parameters. In this manner, the function may describe the tradeoff in the individual error budgets for these parameters. In such an embodiment, parameters of the wafer fabrication process that have an interrelated effect on how the reticle design data will be printed on the wafer may be analyzed collectively as described above, and the results of the analysis may be a function describing how the individual error budgets for two or more parameters affect the overall error budget.

These individual error budgets, possibly in combination with one or more functions describing the interrelated effects of the individual error budgets on the overall error budget, can then be used to determine the optimal tradeoff between operating points and levels of control for different parameters of the wafer fabrication process, which can be used to create a wafer fabrication process that can achieve good (or at least acceptable) wafer print results. For instance, in one embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for at least two of the different parameters based on the overall error budget and a function describing an interrelated effect of the individual error budgets for the at least two of the different parameters on how the reticle design data will be printed on the wafer. In other words, the function may describe a tradeoff between the individual error budgets for two or more parameters of the wafer fabrication process. In this manner, to the extent that tradeoffs can be made between different parameters of the wafer fabrication process, an understanding of those tradeoffs can obtained as described herein and used to make the most efficient process development decisions. Those decisions can be made manually, semi-automatically (e.g., user-assisted by the computer-implemented method embodiments described herein), or automatically by the computer-implemented methods described herein.

In one such example, which takes advantage of the use of a broader range of parameters as described herein, the bias term in a reticle manufacturing process can lead to features of the reticle design data being formed on the reticle with a width that is larger than desired. This reticle bias parameter, as well as the stepper dose, can have a direct impact on the width of the features that print on the wafer. Since these parameters interact, their individual error budgets are related. For example, if the dose is more carefully controlled, control of the reticle bias and CD specifications may be relatively relaxed.

In an additional embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and controllability of the different parameters. For example, some parameters of the wafer fabrication process may be more easy to control than others. In one such example, the focus of a lithography process may be more difficult to control than the dose of the lithography process due to relatively larger changes in the focus over time. Therefore, when selecting the operating set points and the levels of control for one or more parameters of the wafer fabrication process, tighter levels of control may be selected for parameters that are easier to control (or parameters that have errors that are easier to fix), and more relaxed levels of control may be selected for parameters that are more difficult to control. In this manner, the wafer fabrication process may require less monitoring since relatively small drifts in the “difficult to control” parameters will not cause these parameters to be outside of their selected control levels and will not cause the overall process to exceed the overall error budget. The controllability of the different parameters may be determined based on prior knowledge about the parameters or experimental results. The methods described herein can automatically or semi-automatically create the wafer fabrication process using the controllability of the different parameters, for example, as a variable in an algorithm, as a weighting factor in the various decisions involved in the process creation, or in rules used to select the operating set points and levels of control for the different parameters.

In a similar manner, the wafer fabrication process can be created taking into account the cost of implementing various levels of control for various parameters of the wafer fabrication process. For example, in one embodiment, creating the wafer fabrication process includes selecting operating set points and levels of control for the different parameters based on the overall error budget, the individual error budgets, and cost of implementing the levels of control. In one such example, a parameter that is known (e.g., based on prior knowledge or experimental results) to drift significantly over time may require relatively frequent monitoring if a relatively tight level of control is selected for the parameter. Such frequent monitoring of the parameter results in increased costs to perform the monitoring, loss in production time and profits due to the monitoring, and possibly loss in yield if drifts in the parameter are undetected during production. Therefore, the tradeoff between the level of control selected for such a parameter and cost may be used in the methods described herein to select the operating set points and levels of control for the different parameters of the wafer fabrication process. The methods described herein can automatically or semi-automatically create the wafer fabrication process using the cost associated with different levels of control for different parameters, for example, as a variable in an algorithm, as a weighting factor in the various decisions involved in the process creation, or in rules used to select the operating set points and levels of control for the different parameters.

As described above, therefore, the embodiments described herein can be used to examine a relatively broad range of parameters of a wafer fabrication process. The use of such a range of parameters in the embodiments described herein allows for the development of full individual error budgets for the parameters for which appropriate tradeoffs can be made for optimal efficiency. The embodiments described herein, therefore, have a number of advantages over other methods and systems for creating a wafer fabrication process. For instance, the embodiments described herein can be used to make appropriate tradeoffs between the individual error budgets for the various parameters of a wafer fabrication process in a least-cost method. In particular, the methods described herein can be performed without fabricating a reticle, without fabricating wafers with the reticle, and without analysis of the wafers by metrology and/or inspection. Although such experimentation can be used to determine how the various parameters interact to yield properly printed reticle design data, this experimentation is expensive. In addition, such experimentation is significantly time consuming.

In comparison, since the embodiments described herein use simulation to generate images that illustrate how the reticle design data will be printed on a wafer at different values of one or more, and possibly a relatively large number of, different parameters of the wafer fabrication process that can be analyzed by image and/or data processing (e.g., by a processor as described herein), the embodiments described herein provide fast, inexpensive, and efficient methods for evaluating or studying the effects of individual error budgets of each of the different parameters on the printing of the reticle design data on a wafer and for creating a wafer fabrication process. Since the methods are much quicker than those involving the experimentation described above, the time-to-market for devices produced by wafer fabrication processes created as described herein will be quicker.

Furthermore, as lithography and wafer fabrication processes in general become more challenging, more parameters of the wafer fabrication process will need to be controlled to properly yield wafers. The method embodiments described herein can be used to meet these needs since not only the primary parameters such as dose and focus but all relevant parameters of the wafer fabrication processes can be evaluated. In addition, the method embodiments described herein allow lithography engineers to more optimally determine the individual error budgets of the various parameters that affect the printing of reticle design data on wafers. With an understanding of the individual error budget tradeoffs, the most effective process choices can be made.

The individual error budget tradeoffs that can be determined using the method embodiments described herein can also be used to drive design choices that will result in larger overall error budgets. For example, in one embodiment, the different parameters for which individual error budgets are determined in the methods described herein include different characteristics of the reticle design data. In one such embodiment, the method includes creating a design process for the reticle design data based on the overall error budget and the individual error budgets for the different parameters. In particular, the methods described herein can be used to determine the tradeoffs between the different parameters of a wafer fabrication process from the device design process through the etch process (and possibly processes performed subsequent to etch). Based on these tradeoffs, the design process (e.g., rules used in the design process) may be altered, for example, to improve the manufacturability of other device designs created by the design process. In this manner, using a design process created as described herein, device designs can be created that are potentially easier and less costly to manufacture by requiring fewer, more controllable, or less expensive tradeoffs in individual error budgets for the parameters of the wafer fabrication process.

In another such embodiment, the method includes altering the reticle design data based on the overall error budget and the individual error budgets for the different parameters. In other words, the embodiments described herein are not limited to making decisions about process parameters. Instead, the embodiments described herein may involve decision making about process parameters of the wafer fabrication process in addition to decision making about the characteristics of the reticle design data. For example, the methods described herein may be used to alter the reticle design data in a feedback manner based on the evaluation of the different parameters of the wafer fabrication process and the tradeoffs in the individual error budgets for the different parameters made to create the wafer fabrication process. In this manner, the most efficient process and design choices can be made to optimize the yield of the wafer fabrication process in a relatively fast, inexpensive, and efficient manner.

Another embodiment relates to a processor that is configured to perform a method for creating a wafer fabrication process. The method includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. Determining the individual error budgets may be performed by the processor according to any of the embodiments described further herein. The method also includes creating the wafer fabrication process based on the overall error budget and the individual error budgets. Creating the wafer fabrication process may be performed by the processor according to any of the embodiments described further herein. The method that the processor is configured to perform may include any other step(s) described herein. The processor may be further configured as described herein. The processor has all of the advantages of the method embodiments described herein.

One embodiment of a processor configured as described above is illustrated in FIG. 13. In particular, processor 236 is included in system 238, which also includes simulation engine 240. System 238 is configured to create a wafer fabrication process. Simulation engine 240 is configured to generate simulated images illustrating how reticle design data will be printed on a wafer at different values of different parameters of the wafer fabrication process. Simulation engine 240 may be configured to generate the simulated images according to any embodiments described herein. In addition, the simulation engine may be configured to generate any other simulated images described herein. Simulation engine 240 may be further configured as described herein.

Processor 236 is configured to determine individual error budgets for the different parameters based on an overall error budget for the wafer fabrication process and the simulated images generated by simulation engine 240. Therefore, processor 236 may be coupled to simulation engine 240 (e.g., via a transmission medium or data link) such that processor 236 can receive the simulated images from the simulation engine. Although processor 236 and simulation engine 240 may appear to be physically located in proximity to each other within system 238 in FIG. 13, it is to be understood that the processor and the simulation engine may be housed physically separately and possibly in remote locations. In such instances, the processor and the simulation engine may be coupled by a transmission medium that includes “wired” and/or “wireless” portions. The transmission medium may include any suitable transmission medium known in the art.

Processor 236 may be configured to determine the individual error budgets according to any of the embodiments described herein. Processor 236 is also configured to create the wafer fabrication process based on the overall error budget and the individual error budgets. The processor may be configured to create the wafer fabrication process according to any of the embodiments described herein. The processor may be configured to perform any other step(s) of any other embodiments described herein. The system may be further configured as described herein. In addition, the system has all of the advantages of the method embodiments described herein.

Further modifications and alternative embodiments of various aspects of the invention may be apparent to those skilled in the art in view of this description. For example, computer-implemented methods and methods for detecting defects in reticle design data are provided. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the invention may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description of the invention. Changes may be made in the elements described herein without departing from the spirit and scope of the invention as described in the following claims.

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Classifications
U.S. Classification716/55, 705/7.35, 438/5
International ClassificationG06F17/30, G06Q99/00, G03F1/00, G07G1/00, G03F7/20
Cooperative ClassificationG03F1/36, G03F7/70616, G03F1/84, G03F7/70441, G03F7/70433, G03F7/7065, G03F7/70533, G03F1/144, G06Q30/0206, G03F7/705, G03F7/70666
European ClassificationG03F1/84, G03F7/70L2J, G03F7/70L2B, G03F7/70L10, G03F7/70L10L, G03F7/70J2, G03F7/70L10H, G03F7/70J2B, G03F1/14G, G03F1/36, G06Q30/0206
Legal Events
DateCodeEventDescription
Mar 14, 2006ASAssignment
Owner name: KLA-TENCOR TECHNOLOGIES CORP., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HESS, CARL;REEL/FRAME:017692/0267
Effective date: 20060307