Publication number | US20060174183 A1 |

Publication type | Application |

Application number | US 11/045,585 |

Publication date | Aug 3, 2006 |

Filing date | Jan 28, 2005 |

Priority date | Jan 28, 2005 |

Also published as | DE602005014844D1, EP1686693A1, EP1686693B1, EP2093888A2, EP2093888A3, EP2093888B1, EP2093888B8, US7607072, US7865814, US7937649, US8321770, US8407571, US20090313531, US20090319874, US20090319875, US20100050060, USRE44614 |

Publication number | 045585, 11045585, US 2006/0174183 A1, US 2006/174183 A1, US 20060174183 A1, US 20060174183A1, US 2006174183 A1, US 2006174183A1, US-A1-20060174183, US-A1-2006174183, US2006/0174183A1, US2006/174183A1, US20060174183 A1, US20060174183A1, US2006174183 A1, US2006174183A1 |

Inventors | Jonathan Ashley, Kelly Fitzpatrick, Erich Haratsch |

Original Assignee | Ashley Jonathan J, Fitzpatrick Kelly K, Haratsch Erich F |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (8), Referenced by (11), Classifications (8), Legal Events (9) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 20060174183 A1

Abstract

Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

Claims(24)

determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of said plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of said plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of said plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and

determining a reliability value for at least one bit decision.

an add-compare-select unit for generating at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of said plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of said plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of said plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and

a reliability unit that determines a reliability value for at least one bit decision.

generating a path metric difference Δ_{−1 }for a first single-step-trellis period of a multiple-step-trellis cycle based on a difference between a first path that is a winning path for each single-step-trellis period of a multiple-step-trellis cycle and another path that is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis of a multiple-step-trellis cycle.

defining a plurality of paths through a multiple-step trellis into a given state using at least three selection signals, wherein a first of said plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of said plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of said plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle.

a multiple-step-trellis Soft-Output Viterbi algorithm detector that determines values of one or more bits associated with said received signal using a multiple-step trellis and determines one or more reliability values, wherein said determined bits and reliabilities are generated at a rate of the received signal divided by the number of steps in said multiple-step trellis.

determining values of one or more bits associated with said received signal using a multiple step trellis; and

determining one ore more reliability values, wherein said determined bits and said reliabilities are generated at a rate of the received signal divided by the number of steps in said multiple-step trellis.

Description

- [0001]The present application is related to U.S. patent application Ser. No. 10/853,087, entitled “Method and Apparatus for Multiple Step Viterbi Detection with Local Feedback,” filed on May 25, 2004 and incorporated by reference herein.
- [0002]The present invention relates generally to equalization, detection and decoding techniques using the Soft-Output Viterbi Algorithm (SOVA).
- [0003]A magnetic recording read channel converts an analog read channel into an estimate of the user data recorded on a magnetic medium. Read heads and magnetic media introduce noise and other distortions into the read signal. As the information densities in magnetic recording increase, the intersymbol interference (ISI) becomes more severe as well. In read channel chips, a Viterbi detector is typically used to detect the read data bits in the presence of intersymbol interference and noise.
- [0004]The Soft-Output Viterbi Algorithm (SOVA) is a well known technique for generating soft decisions inside a Viterbi detector. A soft decision provides a detected bit with a corresponding reliability. These soft decisions can be used by an outer detector to improve the error rate performance of the overall system. For a more detailed discussion of SOVA detectors, see, for example, J. Hagenauer and P. Hoeher, “A Viterbi Algorithm with Soft-decision Outputs and its Applications,” IEEE Global Telecommunications Conference (GLOBECOM), vol. 3, 1680-1686 (November 1989). SOVA architectures exist for one-step trellises, where one soft decision is generated per clock cycle. SOVA detectors may be implemented, for example, in next-generation read channel systems, and data rates in excess of 2 Gigabits-per-second will have to be achieved. It is challenging to achieve such high data rates with existing SOVA architectures that consider one-step trellises.
- [0005]A need therefore exists for a method and apparatus for performing SOVA detection at the high data rates that are required, for example, by evolving high-end storage applications. A further need exists for a method and apparatus for performing SOVA detection employing a multiple-step trellis.
- [0006]Generally, methods and apparatus are provided for performing a Soft-Output Viterbi algorithm (SOVA). According to one aspect of the invention, the values of one or more bits associated with a received signal and one or more reliability values are determined using a multiple-step trellis. The determined bits and reliabilities are generated at a rate of the received signal divided by the number of steps in the multiple-step trellis.
- [0007]According to another aspect of the invention, a number of paths are defined based on whether the path is a winning or losing path for first and second single-step-trellis periods of a multiple-step-trellis cycle. The various paths are used to generate path metric differences Δ
_{0 }and Δ_{−1}. The path metric differences Δ_{0 }and Δ_{−1 }are then used to determine at least one reliability value for at least one bit decision associated with the maximum-likelihood path through the multiple-step trellis. - [0008]A more complete understanding of the present invention, as well as further features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.
- [0009]
FIG. 1 illustrates a one-step trellis diagram for a channel with memory L=2; - [0010]
FIG. 2 illustrates the two-step SOVA for the one-step trellis shown inFIG. 1 ; - [0011]
FIG. 3 is a schematic block diagram for a SOVA implementation employing a one-step trellis; - [0012]
FIG. 4 illustrates a one-step trellis for a channel with memory L=3; - [0013]
FIG. 5 illustrates a two-step trellis for a channel with memory L=3; - [0014]
FIG. 6 a schematic block diagram showing a SOVA implementation for a two-step trellis; - [0015]
FIG. 7 illustrates a detailed schematic block diagram of a SOVA implementation for a two-step trellis; - [0016]
FIG. 8 illustrates the path metric differences computed by a SOVA detector for a two-step trellis; - [0017]
FIG. 9 is a schematic block diagram showing an exemplary implementation of the ACS operation ofFIG. 7 and the generation of path metric differences Δ_{−1 }and Δ_{0}; - [0018]
FIG. 10 is a schematic block diagram showing an alternate implementation of the ACS operation ofFIG. 7 and the generation of the path metric differences Δ_{−1 }and Δ_{0}; - [0019]
FIG. 11 is a schematic block diagram showing an exemplary implementation of the survivor memory unit ofFIG. 7 ; - [0020]
FIG. 12 is a schematic block diagram showing an exemplary implementation of the path comparison ofFIG. 7 for bits corresponding to even one-step-trellis periods; - [0021]
FIG. 13 is a schematic block diagram showing an exemplary implementation of the path comparison ofFIG. 7 for bits corresponding to odd one-step-trellis periods; and - [0022]
FIG. 14 is a schematic block diagram showing an exemplary implementation of the reliability update ofFIG. 7 for the maximum-likelihood (ML) path. - [0023]The present invention recognizes that the limitation on achievable data rates in a SOVA detector is overcome by employing a multiple-step trellis. The multiple-step trellis is obtained from a one-step trellis by collapsing transitions over multiple time steps into one. In other words, each transition in the multiple-step trellis corresponds to multiple transitions in the one-step trellis. For example, in an exemplary two-step trellis, each transition in the two-step trellis corresponds to two transitions in the original one-step trellis. SOVA detectors in accordance with the present invention can operate at data rates that are about twice the data rates of conventional designs that use one-step trellises. Even larger speed-ups are achievable for multiple-step trellises with step sizes larger than two.
- [0024]The present invention is illustrated in the context of a two-step SOVA, where Viterbi detection is followed by reliability processing. For a discussion of suitable two-step SOVA architectures for one-step trellises, see, for example, O. J. Joeressen and H. Meyr, “A 40-Mb/s Soft-Output Viterbi Decoder,” IEEE J. Solid-State Circuits, vol. 30, 812-818 (July, 1995), and E. Yeo et al., “A 500-Mb/s Soft-Output Viterbi Decoder,” IEEE Journal of Solid-State Circuits, vol. 38, 1234-1241 (July, 2003). The present invention applies, however, to any SOVA implementation, as would be apparent to a person of ordinary skill in the art. For a discussion of suitable one-step SOVAs, see, for example, J. Hagenauer and P. Hoeher, “A Viterbi algorithm with Soft-Decision Outputs and its Applications,” IEEE Global Telecommunications Conference (GLOBECOM), vol. 3, 1680-1686 (November, 1989), and O. J. Joeressen et al., “High-Speed VLSI Architectures for Soft-Output Viterbi Decoding,” Journal of VLSI Signal Processing, vol. 8, 169-181 (1994), incorporated by reference herein. It is important to distinguish the terms “one-step SOVA” and “two-step SOVA” from the term “multiple-step trellis.” While the term “n-step SOVA” indicates the number of steps, n, required to perform Viterbi and reliability processing, the term “multiple-step trellis” indicates a trellis obtained from a one-step trellis by collapsing transitions over multiple time steps into one.
- [0025]
FIG. 1 shows a one-step trellis**100**, where a state is defined by the two most recent state bits b_{0}b_{−1 }and denoted as state(b_{0}b_{−1}). This trellis corresponds e.g. to an ISI channel with memory L=2. The bit b_{0 }is associated with the transition:

state(*b*_{−1}*b*_{−2})→state(*b*_{0}*b*_{−1}). - [0026]
FIG. 2 illustrates the two-step SOVA for an expanded version**200**of the trellis**100**shown inFIG. 1 . The two-step SOVA is explained, e.g., in O. J. Joeressen and H. Meyr, “A 40 Mb/s Soft-Output Viterbi Decoder,” IEEE Journal of Solid-State Circuits, Vol. 30, 812-18 (July, 1995). The first step of the two-step SOVA determines the maximum likelihood (ML) path**210**inFIG. 2 , in a similar manner to the conventional Viterbi algorithm.FIG. 2 illustrates the steady-state of the Viterbi algorithm at time step n=3, after the four survivor paths into all four states {state(b_{3}b_{2})} have been determined. The starting state**250**{state(b_{0}b_{−1})} of the ML path**210**can be identified by a D-step trace-back from the {state(b_{D}b_{D−1})} with the minimum path metric, where D is the path memory depth of the survivor memory unit. In the example ofFIG. 2 , it is assumed that D=3. - [0027]In the second step of the two-step SOVA, the reliabilities for the bit decisions along the ML path
**210**terminating in the starting state state(b_{0}b_{−1}) are updated. The reliability update depth is denoted by U. - [0028]Let b′
_{0}, b′_{−1}, . . . denote the state bits for the ML path**210**that terminates in the starting state state(b′_{0},b′_{−1}). Also, let {tilde over (b)}_{0}, {tilde over (b)}_{−1}, . . . denote the state bits for the competing, losing path**230**inFIG. 2 that terminates in the starting state, state({tilde over (b)}_{0},{tilde over (b)}_{−1})=state(b′_{0},b′_{−1}). - [0029]The absolute path metric difference between the ML path
**210**and competing path**230**into the starting state, state(b′_{0},b′_{−1}), is denoted by Δ′_{0}. The U intermediate reliabilities for the bits b′_{0}, b′_{−1}, . . . , b′_{−U+1 }that are updated using Δ′_{0 }are denoted by R′_{0,0}, R′_{−1,0}, . . . , R′_{−U+1,0}, respectively. The reliabilities are updated according to following rule:$\mathrm{initialization}\text{:}\text{\hspace{1em}}{R}_{0,-1}^{\prime}=+\infty ,\text{}i=0,-1,\dots \text{\hspace{1em}},-U+1\text{:}\text{\hspace{1em}}{R}_{i,0}^{\prime}=\{\begin{array}{cc}\mathrm{min}\left({R}_{i,-1}^{\prime},{\Delta}_{0}^{\prime}\right)& \mathrm{if}\text{\hspace{1em}}{b}_{i}^{\prime}\ne {\stackrel{~}{b}}_{i,0},\\ {R}_{i,-1}^{\prime}& \mathrm{otherwise},\text{\hspace{1em}}\end{array}\text{}{R}_{-U+1}^{\prime}={R}_{-U+1,0}^{\prime},$

where R′_{−1,−1}, R′_{−2,−1}, . . . , R′_{−U+1,−1 }are the intermediate reliabilities that were updated in the previous clock cycle using the path metric difference Δ′_{−1 }for the starting state state(b′_{−1},b′_{−2}), and R′_{−U+1 }is the final reliability for bit b′_{−U+1}. - [0030]It can be seen from the updating formula that the reliability for bit b′
_{0 }is first initialized to infinity (R′_{0,−1}=+∞). Then, as the starting state**250**for the ML path**210**moves from state(b′_{0},b′_{−1}) to state(b′_{U−1},b′_{U−2}), and as corresponding absolute path metric differences Δ′_{0 }to Δ′_{U−1 }become available, the reliability for bit b′_{0 }is updated U times by using either the previous reliability, if the bit b′_{0 }agrees with the bit of the respective competing path, or using the minimum of the path metric difference and previous reliability. - [0031]The updating of reliabilities is shown in
FIG. 2 for U=3, where the ML path**210**and competing path**230**merge into the starting state state(b′_{0},b′_{−1})=state(00), and the intermediate reliabilities R′_{0,0}, R′_{−1,0}, and R′_{−2,0 }are updated based on the path metric difference Δ′_{0 }and the respective intermediate reliabilities from the previous updating procedure, i.e. R′_{−1,−1 }and R′_{−2,−1}. In the example ofFIG. 2 , only R′_{−2,0 }is updated by taking the minimum of R′_{−2,−1 }and Δ′_{0}, as the bits b′_{−2 }and {tilde over (b)}_{−2,0 }differ from each other. - [0032]
FIG. 3 is a schematic block diagram showing a SOVA detector for a one-step trellis**300**(referred to in the following as a one-step-trellis SOVA detector). As shown inFIG. 3 , a one-step-trellis SOVA detector**300**processes a received signal to generate soft decisions, in a well known manner. Each soft decision includes the detected bit and a corresponding reliability value. The SOVA detector**300**generates soft decisions at the same rate, ƒ_{S}, at which the input signals are received, ƒ_{R}. For a more detailed discussion of the SOVA, see, for example, J. Hagenauer and P. Hoeher, “A Viterbi Algorithm with Soft-Decision Outputs and its Applications,” IEEE Global Telecommunications Conference (GLOBECOM), vol. 3, 1680-1686 (November, 1989). - [0033]
FIG. 4 illustrates a one-step trellis**400**for an ISI channel having a memory L=3. There are eight channel states, and two branches corresponding to the bits b_{n}=0 and b_{n}=1 leave each state, state(b_{−1}b_{−2}b_{−3}), to reach a respective successor state, state(b_{0}b_{−1}b_{−2}) . - [0034]As previously indicated, the present invention increases the maximum data rate that may be achieved by a SOVA detector by transforming the original one-step trellis
**400**into a multiple-step trellis**500**, shown inFIG. 5 .FIG. 5 illustrates an exemplary two-step trellis**500**for an ISI channel having a memory L=3, corresponding to the one-step trellis**400**ofFIG. 4 , in accordance with the present invention. The trellises in bothFIGS. 4 and 5 are for the illustrative case that the channel memory is equal to L=3. While the present invention is described using the exemplary two-step trellis**500**ofFIG. 5 , the invention generalizes to cases where more than two steps are processed at once in a multiple-step trellis, as would be apparent to a person of ordinary skill in the art. As shown inFIG. 5 , when one step is processed in the two-step trellis**500**, two steps from the original one-step trellis**400**are processed at once. In this manner, if a two-step trellis is used, the maximum data rate that can be achieved in a hardware implementation is effectively increased by a factor of about two compared to a one-step-trellis implementation. A higher data rate increase can be achieved if more than two steps from the original one-step trellis are processed at once in the multiple-step trellis. - [0035]
FIG. 6 is a schematic block diagram showing a SOVA implementation for a two-step trellis**600**(also referred to in the following as a two-step-trellis SOVA detector) incorporating features of the present invention. As shown inFIG. 6 , the serial received signal is converted to a parallel signal at stage**610**and the parallel signals are processed by the two-step-trellis SOVA detector**600**, for example, using the exemplary implementation discussed below in conjunction withFIG. 7 . The two-step-trellis SOVA detector**600**generates the detected bits and reliabilities at half the rate, ƒ_{S}=½·ƒ_{R}, at which the input signals are received, ƒ_{R}. Thus, two soft decisions are generated per clock cycle. The parallel output of the two-step trellis SOVA detector**600**may be converted to a serial signal at stage**650**. - [0036]
FIG. 7 illustrates a schematic block diagram of an exemplary two-step SOVA architecture**700**for a two-step trellis incorporating features of the present invention. As shown inFIG. 7 , the exemplary SOVA architecture**700**for a two-step trellis comprises a branch metric unit (BMU)**710**. - [0037]The BMU
**710**is explained for the two-step trellis shown inFIG. 5 without loss of generality. The BMU**710**computes one-step-trellis branch metrics, m(0000), m(0001), m(1111), as follows:

*m*(*b*_{0}*b*_{−1}*b*_{−2}*b*_{−3})=[*y−e*(*b*_{0}*b*_{−1}*b*_{−2}*b*_{−3})]^{2},

where the subtracted term e(b_{0}b_{−1}b_{−2}b_{−3}) is the ideal (noise-less) channel output under the condition that the state bit block (on which the ideal output depends) is b_{0}b_{−1}b_{−2}b_{−3}. - [0038]In each two-step-trellis clock cycle, each one-step-trellis branch metric is used as a summand in two distinct two-step-trellis branch metrics. The two-step-trellis branch metric for the 5 state bits b
_{0}b_{−1}b_{−2}b_{−3}b_{−4}, where b_{0 }is the most recent bit at the later one-step-trellis period of the two-step-trellis cycle, is given by:

*m*_{branch}(*b*_{0}*b*_{−1}*b*_{−2}*b*_{−3}*b*_{−4})=*m*(*b*_{−1}*b*_{−2}*b*_{−3}*b*_{−4})+*m*(*b*_{0}*b*_{−1}*b*_{−2}*b*_{−3}) - [0039]In addition, the exemplary two-step-trellis SOVA architecture
**700**comprises an add-compare-select unit (ACSU)**900**, discussed below in conjunction withFIGS. 9 and 10 , a survivor memory unit (SMU)**1100**, discussed below in conjunction withFIG. 11 , a path comparison unit**1200**, discussed below in conjunction withFIGS. 12 and 13 , a reliability unit**1400**, discussed below in conjunction withFIG. 14 , and a number of delay operators D**1**-D**3**. - [0040]The BMU
**710**, ACSU**900**, and SMU**1100**implement the first step of the two-step SOVA, i.e., maximum-likelihood sequence detection using the Viterbi algorithm. The second step of the two-step SOVA is implemented by the path comparison unit**1200**, which computes the paths that compete with a respective win-win path, and the reliability update unit**1400**, which updates the reliabilities for the ML path. - [0041]A conventional one-step-trellis SOVA implementation computes one absolute path metric difference per state at each (one-step-trellis) clock cycle, as described, e.g., in O. J. Joeressen and H. Meyr, “A 40 Mb/s Soft-Output Viterbi Decoder,” IEEE Journal of Solid-State Circuits, Vol. 30, 812-18 (July, 1995). The present invention recognizes that in the exemplary implementation for a two-step trellis, where two steps from the original one-step trellis
**400**are processed at once, two path metric differences are computed per state at each (two-step-trellis) clock cycle. Thus, as discussed below in conjunction withFIG. 9 andFIG. 10 , the ACSU**900**generates, for each state, two path metric differences Δ_{−1 }and Δ_{0 }for the first and second period of the (two-step-trellis) clock cycle. - [0042]
FIG. 8 illustrates the computation of the path metric differences Δ_{−1 }and Δ_{0 }in a two-step-trellis SOVA detector**600**for the exemplary one-step and two-step trellises**400**and**500**, where n is the one-step-trellis time index and m is the two-step-trellis time index. In a two-step-trellis SOVA implementation, each two-step-trellis cycle contains two one-step-trellis periods. For example, as shown inFIG. 8 , the cycle associated with the two-step-trellis index m=0 contains the two one-step-trellis periods associated with the one-step-trellis indices n=0 and n=−1.FIG. 8 shows four competing paths**810**,**820**,**830**,**840**. Each path**810**,**820**,**830**,**840**can be indentified with a respective two-bit selection signal indicating whether the path wins or loses in each one-step-trellis period of the two-step-trellis cycle into the state that terminates in the state defined by the 3-bit block b_{0}b_{−1}b_{−2}=000. For example, the win-lose path**810**wins (relative to the lose-lose path) in the first period (n=−1) and loses (relative to the win-win path) in the second period (n=0) of the two-step-trellis cycle. - [0043]
FIG. 8 shows the four competing paths**810**,**820**,**830**and**840**that terminate in the state defined by the 3-bit block b_{0}b_{−1}b_{−2}=000. - [0044]The path metric difference Δ
_{0 }for the second period of the two-step-trellis cycle, into the state associated with the one-step-trellis index n=0, is the difference between the win-win path segment**820**-**0**and the win-lose path segment**810**-**0**. The path metric difference Δ_{−1 }for the first period of the two-step-trellis cycle, into the respective state associated with the one-step-trellis index n=−1, is the difference between the win-win path segment**820**-**1**and the lose-win path segment**830**-**1**. - [0045]In a conventional one-step-trellis SOVA implementation, the ACS generates a single ACS decision, e, indicating, for each state, which branch to trace back along the winning path through the trellis. According to an exemplary convention, a value of e=0 provides an indication to trace back the upper branch from a state. The present invention recognizes that in a two-step-trellis SOVA implementation, the ACS
**900**needs to generate, for each two-step-trellis cycle, two-bit ACS decisions ef, indicating, for each two-step-trellis cycle, which branches to trace back along the win-win path through the trellis, where e corresponds to the first period and f to the second period of the two-step-trellis cycle. Thus, a two-bit ACS decision of ef=00 provides an indication to trace back the upper branches out of the state that terminates in the state defined by the 3-bit block b_{0}b_{−1}b_{−2}=000 through the trellis**800**along the win-win path**820**to the state defined by the 3-bit block b_{−2}b_{−3}b_{−4}=000. - [0046]Again, the path metric difference Δ
_{0 }for the second period of the two-step-trellis cycle is the difference between the win-win path segment**820**-**0**and the win-lose path segment**810**-**0**. Similarly, the path metric difference Δ_{−1 }for the first period of the two-step-trellis cycle is the difference between the win-win path segment**820**-**1**and the lose-win path segment**830**-**1**. Thus, to compute the path metric differences, Δ_{0 }and Δ_{−1}, three different paths need to be distinguished (win-win path**820**, win-lose path**810**, and lose-win path**830**). The two-bit ACS decisions ef, however, only allows two of these paths to be distinguished. The win-win path**820**can be identified using the two-bit ACS decision ef=00. The lose-win path**830**can be identified using the two-bit selection signal e{overscore (f)}=01, which can be derived from the ACS decision by using e and inverting f ({overscore (f)} denotes the inversion of f). While the second win-lose path segment**810**-**0**can be identified in terms of the ACS decision e, i.e. by {overscore (e)}=1, the first win-lose path segment**810**-**1**cannot be identified in terms of the ACS decision, f. Thus, in order to sufficiently define the win-lose path**810**through the two-step trellis, an additional selection signal F is generated, as discussed further below. - [0047]The best path, i.e., the win-win path
**820**into state(b_{0}b_{−1}b_{−2}) is given by the bit sequence b_{0}b_{−1}b_{−2}b_{−3}b_{−4}=b_{0}b_{−1}b_{−2}ef=00000. - [0048]The lose-win-path
**830**is thus the path that lost to the win-win path**820**in the first period of the two-step-trellis cycle and then became part of the win-win path**820**. This path**830**is given by the bit sequence b_{0}b_{−1}b_{−2}b_{−3}b_{−4}=b_{0}b_{−1}b_{−2}e{overscore (f)}=00001, and it can be traced back from state(b_{0}b_{−1}b_{−2}) to state state(b_{−1}b_{−2}e), and then from state(b_{−1}b_{−2}e) to state(b_{−2}e{overscore (f)}) using the ACS decision e and the inverted ACS decision {overscore (f)}. The path metric difference Δ_{−1 }is defined as the path metric difference between the win-win path segment**820**-**1**and the lose-win path segment**830**-**1**. - [0049]The win-lose-path
**810**is the winning path into state(b_{−1}b_{−2}{overscore (e)}) and the losing path into state(b_{0}b_{−1}b_{−2}). Denote the one-step-trellis ACS decision for the two paths into state state(b_{−1}b_{−2}{overscore (e)}) by F. Then, the win-lose-path**810**can be traced back from state(b_{0}b_{−1}b_{−2}) to state(b_{−1}b_{−2}{overscore (e)}) and then to state(b_{−2}{overscore (e)}F). In the example ofFIG. 8 , the win-lose path**810**is given by the state sequence b_{0}b_{−1}b_{−2}b_{−3}b_{−4}=b_{0}b_{−1}b_{−2}{overscore (e)}F=00010. The path metric difference Δ_{0 }is defined as the path metric difference between the win-win path segment**820**-**0**and win-lose path segment**810**-**0**. - [0050]The lose-lose-path
**840**can be traced back from state(b_{0}b_{−1}b_{−2}) to state(b_{−1}b_{−2}{overscore (e)}) and state(b_{−2}{overscore (e)}F), but it is not of importance for the computation of the path metric differences Δ_{−1 }and Δ_{0}. - [0051]In summary, for each state(b
_{0}b_{−1}b_{−2}) two path metric differences Δ_{−1 }and Δ_{0 }are computed, the former for the first period and the latter for the second period of a two-step-trellis cycle. The lose-win path**830**can be traced back from state(b_{0}b_{−1}b_{−2}) to state(b_{−2}e{overscore (f)}) using the two-bit selection signal e{overscore (f)}, and the win-lose path**810**can be traced from state(b_{0}b_{−1}b_{−2}) to state(b_{−2}{overscore (e)}F) using the two-bit selection signal {overscore (e)}F. - [0052]Returning to
FIG. 7 , the path metric differences Δ_{0 }and Δ_{−1}, and the ACS decisions e, f and F are delayed in the delay buffers D**2**for a time that is equal to the delay of the path memory and the delay buffer D**1**. The path comparison unit**1200**generates, for each state and bit within the reliability update window, an equivalence bit that indicates whether the win-win path and a respective competing path agree in terms of the bit decision. The path metric differences and equivalence bits that correspond to the starting state of the ML path are selected based on a selection signal that is defined by the state bits in the delay buffer D**1**. The state bits for the ML path at the output of SMU are first stored in the delay buffer D**1**and then in the delay buffer D**3**. - [0053]
FIG. 9 is a schematic block diagram showing an exemplary implementation of the ACSU**900**ofFIG. 7 and the generation of path metric differences Δ_{−1 }and Δ_{0 }and the additional ACS decision F. The exemplary ACSU**900**considers an 8-state two-step trellis with 4 transitions per state, such as the trellis**500**shown inFIG. 5 , in which each state is defined by the past 3 state bits b_{0}b_{−1}b_{−2}. Each two-step-trellis branch metric m_{branch}(b_{0}b_{−1}b_{−2}b_{−3}b_{−4}) depends on the 3 state bits b_{−2}b_{−3}b_{−4 }that define the starting state of a transition in the two-step trellis**800**, and also on the 2 state bits b_{0}b_{−1 }that correspond to the path extension. The path metric for above path extension is computed by:

*m′*_{path}(*b*_{0}*b*_{−1}*b*_{−2}*b*_{−3}*b*_{−4})=*m*_{path}(*b*_{−2}*b*_{−3}*b*_{−4})+*m*_{branch}(*b*_{0}*b*_{−1}*b*_{−2}*b*_{−3}*b*_{−4}),

where m_{path}(b_{−2}b_{−3}b_{−4}) is the path metric for the winning path into state state(b_{−2}b_{−3}b_{−4}) at the previous two-step-trellis cycle. - [0054]For each state, the ACSU performs the ACS operation to determine the winning path using a set of adders
**910**, a comparator**920**and a selector**930**. For example, for state(000), the four path metrics for the path extensions into this state are computed as

*m′*_{path}(00000)=*m*_{path}(000)+*m*_{hrate}(00000)

*m′*_{path}(00010)=*m*_{path}(010)+*m*_{hrate}(00010)

*m′*_{path}(00001)=*m*_{path}(001)+*m*_{hrate}(00001)

*m′*_{path}(00011)=*m*_{path}(011)+*m*_{hrate}(00011) - [0055]The path metric for the winning path
**820**into state(b_{0}b_{−1}b_{−2}) is determined with a 4-way comparison**920**among the path metrics for the 4 path extensions into this state, i.e., it is the minimum of the 4 values m′_{path}(b_{0}b_{−1}b_{−2}00), m′_{path}(b_{0}b_{−1}b_{−2}10), m′_{path}(b_{0}b_{−1}b_{−2}01), and m′_{path}(b_{0}b_{−1}b_{−2}11). - [0056]In the ACSU
**900**, the path metric differences Δ_{−1 }and Δ_{0 }are computed after the two-step-trellis ACS operation, as shown inFIG. 9 . The two-bit, two-step-trellis ACS decision ef generated by the comparator**920**is used to select the path metric for the winning path (also referred to as the win-win path**820**) at the selector**930**as in a conventional two-step-trellis ACSU. The path metric**940**of the lose-win path**830**is chosen by a selector**950**using the 2-bit selection signal e{overscore (f)}. The path metric difference Δ_{−1 }is computed by taking the absolute value of the difference between the path metric of the win-win path**820**and lose-win path**830**, as computed by a subtractor**955**. - [0057]The win-lose path
**810**and lose-lose path**840**are chosen using two 2-to-1 multiplexers**960**,**965**, based on the selection signal {overscore (e)}. This is equivalent to selecting the win-lose and lose-lose path**840**using two 4-to-1 multiplexers that are driven by the 2-bit selection signals {overscore (e)}**0**and {overscore (e)}**1**respectively. The two selected path metrics are compared by a comparator**970**to identify the path metric**975**of the win-lose path**810**, and the corresponding ACS decision F is generated. The path metric**975**is selected by the selector**972**. The path metric difference Δ_{0 }is computed by a subtractor**980**that computes the absolute value of the difference between the path metric of the win-win path**820**and win-lose path**810**. - [0058]
FIG. 10 shows an alternate implementation of the ACS operation and generation of the path metric differences Δ_{−1 }and Δ_{0}. For each state, the ACSU**1000**performs the ACS operation to determine the winning path using a set of adders**1010**, a set of comparators**1020**, selection logic and a selector**1030**. The path metric for the winning path**820**into state(b0b_{−1}b_{2}) is determined with six parallel concurrent two-way comparisons**1020**. For a more detailed discussion of the implementation of the ACS operation for multiple-step trellises using parallel concurrent comparisons, see U.S. patent application Ser. No. 10/853,087, entitled “Method and Apparatus for Multiple-Step Viterbi Detection with Local Feedback,” filed on May 25, 2004 and incorporated by reference herein. - [0059]In the ACSU
**1000**, the path metric differences Δ_{−1 }and Δ_{0 }are selected or computed after the two-step-trellis ACS operation, as shown inFIG. 10 . The two-bit, two-step-trellis ACS decision ef generated by the selection logic**1030**is again used to select the path metric for the winning path (also referred to as the win-win path**820**) by a selector**1035**as in a conventional two-step-trellis ACSU. The path metric difference Δ_{−1 }is selected by a selector**1045**(controlled by selection logic**1040**that processes the 2-bit ACS decision ef) that selects the output of the appropriate comparator**1020**that produced the absolute value of the difference between the path metric of the win-win path**820**and lose-win path**830**. - [0060]Similarly, the path metric difference Δ
_{0 }is selected by a selector**1055**(controlled by selection logic**1050**that processes the first bit, e, of the 2-bit ACS decision ef and the selection signal F) that selects the output of the appropriate comparator**1020**that produced the absolute value of the difference between the path metric of the win-win path**820**and win-lose path**810**. - [0061]The ACS decision F is generated in the ACSU
**1000**as follows. The path metric difference between the win-win path**820**and win-lose path**810**and the path metric difference between the win-win-path**820**and the lose-lose path**840**are chosen using two selectors**1060**,**1065**, each of which is controlled by selection logic that processes the 2-bit ACS decision ef. The two selected path metric differences are compared by a comparator**1070**to generate the corresponding ACS decision F. - [0062]
FIG. 11 is a schematic block diagram showing an exemplary implementation of the survivor memory unit**1100**ofFIG. 7 . Generally, the SMU**1100**stores and updates the state bits for all 8 survivor paths using a conventional register-exchange architecture, where the multiplexers**1110**are controlled by the two-bit, two-step-trellis ACS decision ef.FIG. 11 shows the double row of the survivor memory unit**1100**that stores the odd and even state state bits {circumflex over (b)}_{0}, {circumflex over (b)}_{−1}, {circumflex over (b)}_{−2}, {circumflex over (b)}_{−3}, {circumflex over (b)}_{−4}, {circumflex over (b)}_{−5}, . . . along the survivor path into state(b_{0}_{−1}b_{−2}). The top row in the exemplary embodiment processes the predefined state bit b_{0 }and corresponding predefined state bits from other states, under control of the ACS decision ef, whereas the bottom row processes the predefined state bit b_{−1 }and corresponding predefined state bits from other states, under control of the ACS decision ef. The double row structure ofFIG. 11 is implemented for all 8 states. Per state and stored survivor bit pair, the SMU**1100**implements two multiplexers**1110**and two registers**1120**as a constituent functional unit. The SMU**1100**produces at the output the final survivor bits {circumflex over (b)}_{−D+2 }and {circumflex over (b)}_{−D+1}, where D is the path memory depth. In the exemplary embodiment**1100**, D=8. For a discussion of the register-exchange SMU architecture, see, e.g., R. Cypher and C. B. Shung, “Generalized Trace-Back Techniques for Survivor Memory Management in the Viterbi Algorithm,” Journal of VLSI Signal Processing, 85-94 (1993). - [0063]The ML path
**820**is the path with the overall minimum path metric. The survivor bits {circumflex over (b)}_{−D+2 }and {circumflex over (b)}_{−D+1 }that correspond to the state with the overall minimum path metric are provided to the delay buffer D**1**(FIG. 7 ) and denoted as b′_{−D+2 }and b′_{−D+1}. These bits are the state bits for the ML path**820**, and they both determine the starting state for the reliability update operation and also the final bit decisions. - [0064]As previously indicated, the two-step-trellis SOVA architecture
**700**ofFIG. 7 comprises a number of delay buffers D**1**-D**3**. The delay buffer D**1**delays the state bits at the end of the SMU**1100**that belong to the ML path**820**by two two-step-trellis clock cycles. The final three bits of this buffer D**1**define the starting state for the second step of the two-step SOVA. The starting state signal is used to select the path metric differences and equivalence bits for the ML path. - [0065]The ACS decisions e, f, F and the path metric differences Δ
_{−1}, Δ_{0 }for all states are also delayed in the delay buffers D**2**. The delay of D**2**is equal to the sum of the delay of the path memory and the buffer D**1**. The delay buffer D**3**further delays the state bits that are outputted by the buffer D**1**. The delay of D**3**is equal to the delay of the reliability update unit. - [0066]As previously indicated, the path comparison unit
**1200**, shown inFIG. 12 andFIG. 13 , computes for each state the paths that competes with the survivor path, i.e., win-win path**820**. In addition, the path comparison unit**1200**generates, for each state and bit within the reliability update window, an equivalence bit that indicates whether the win-win path**820**and a competing path agree in terms of the bit decision. - [0067]
FIG. 12 is a schematic block diagram showing an exemplary implementation of the path comparison unit**1200**-even for bits corresponding to even one-step-trellis periods andFIG. 13 is a schematic block diagram showing an exemplary implementation of the path comparison unit**1200**-odd for bits corresponding to odd one-step-trellis periods (collectively referred to as the path comparison unit**1200**). The path comparison unit**1200**receives at each two-step-trellis cycle for each state the delayed ACS decisions e, f and F, from which the selection signals ef, e{overscore (f)} and {overscore (e)}F are derived. The path comparison unit**1200**stores and updates the bits that correspond to all survivor paths. The path comparison unit**1200**also computes equivalence bits for each surviving bit: an equivalence bit is 1 if the bit for the survivor path**820**and competing path disagree, and 0 otherwise. - [0068]The survivor bits {circumflex over (b)}
_{0}, {circumflex over (b)}_{−1}, {circumflex over (b)}_{−2}, {circumflex over (b)}_{−3}, {circumflex over (b)}_{−4}, {circumflex over (b)}_{−5}, . . . are generated as shown inFIG. 12 for even one-step-trellis periods and inFIG. 13 for odd one-step-trellis periods of a two-step-trellis cycle. - [0069]In
FIGS. 12 and 13 , the survivor bits of the win-lose path**810**, which are selected by {overscore (e)}F, and the survivor bits of the lose-win path**830**, which are selected by e{overscore (f)}, are compared to the survivor bits of the win-win path**820**, which are selected by ef, to generate corresponding equivalence bits. The path comparison unit**1200**resembles the register-exchange implementation of the survivor memory unit**1100**. The bottom row of the path comparison units**1200**-even,**1200**-odd contain registers**1220**and multiplexers**1210**that store and select the survivor paths for every state. - [0070]In addition, the top and middle rows of the path comparison units
**1200**-even,**1200**-odd contain two multiplexers**1210**per one-step-trellis period and state that select the bits of the competing lose-win path**830**and win-lose path**810**using the selection signals e{overscore (f)} and {overscore (e)}F, respectively, and there are two XOR gates that generate respective equivalence bits indicating whether the bit for the respective path (the lose-win path**830**or win-lose path**810**associated with the selection signals e{overscore (f)} and {overscore (e)}F) and the bit for the winning (win-win) path are equivalent. The notation q_{−2,0 }indicates the equivalence bit for survivor bit {circumflex over (b)}_{−2 }and path metric difference Δ′_{0}, while q_{−2,−1 }indicates the equivalence bit for survivor bit {circumflex over (b)}_{−2 }and path metric difference Δ′_{−1}. Each column of the path comparison units**1200**-even,**1200**-odd corresponds to an even and odd one-step-trellis period, respectively. - [0071]The structure in
FIGS. 12 and 13 is required for each state. WhileFIGS. 12 and 13 show a number of columns each containing three multiplexers, two XOR gates and one register, the first column inFIG. 12 only includes two multiplexers, one XOR gate and one register, as it computes only one equivalence bit, i.e. q_{0,0 }in the exemplary embodiment. The path comparison unit generates, for each state, equivalence bits up to q_{−U+2,−1}, q_{−U+2,0 }and q_{−U+1,−1}, q_{−U+1,0}, respectively, where U is the reliability update length. In the exemplary embodiment**1200**, U=6. - [0072]
FIG. 14 is a schematic block diagram showing an exemplary implementation of the reliability update unit**1400**ofFIG. 7 that updates the reliabilities for the maximum-likelihood path**820**. The exemplary reliability update unit**1400**computes and stores two reliability values per two-step-trellis cycle. - [0073]Δ′
_{−1 }and Δ′_{0 }are the delayed path metric differences for the ML path**820**into the starting state (seeFIG. 7 ). These two values are selected among the buffered path metric differences using the starting state signal as shown inFIG. 7 . - [0074]q′
_{0,0}, q′_{−1,−1}, q′_{−1,0}, q′_{−2,−1}, q′_{−2,0}, q′_{−3,−1}, q′_{−3,0}, . . . are the equivalence bits for the ML path into the starting states state(b′_{−1}b′_{−2}b′_{−3}) and state(b′_{0}b′_{−1}b′_{−2}). These signals are selected among the equivalence bits computed in the path comparison unit (seeFIGS. 12 and 13 ) using the starting state signal as shown inFIG. 7 . - [0075]The reliabilities R′
_{0,0}, R′_{−1,0}, R′_{−2,0}, R′_{−3,0}, R′_{−4,0}, R′_{−5,0}, . . . are updated based on Δ′_{0}, whereas R′_{−1,−1}, R′_{−2,−1}, R′_{−3,−1}, R′_{−4,−1}, R′_{−5,−1 }. . . are updated based on Δ′_{−1}. - [0076]R
_{max }is a hard-wired value and denotes the maximum reliability value, e.g., R_{max}=∞. The first reliabilities R′_{0,0 }and R′_{−1,−1 }consider R_{max }as an initialization value in the exemplary embodiment. - [0077]After initialization, a functional element, such as the exemplary functional element
**1410**, comprises four functional units, such as the exemplary functional unit**1420**, and two registers. Each functional unit**1420**comprises a comparator, a multiplexer and an AND gate. The top row of the reliability update unit**1400**computes reliability values for even one-step-trellis periods and the bottom row computes reliability values for odd one-step-trellis periods. For example, R′_{0,0 }(computed in the previous two-step-trellis cycle) and Δ′_{−1 }are used to compute R′_{−2,−1}, under control of the corresponding equivalence bit q′_{−2,−1}. Thereafter R′_{−2,−1 }and Δ′_{0 }are used to compute R′_{−2,0 }under control of the corresponding equivalence bit q′_{−2,0}. Thus, two functional units operate in series to first compute R′_{−2,−1 }and then R′_{−2,0}. In an analogous fashion, two functional units operate in series to first compute R′_{−3,−1 }and then R′_{−3,0}, by using the path metric differences, Δ′_{−1 }and Δ′_{0}, and corresponding equivalence bits. In summary, two groups of functional units operate in parallel to compute the reliability values R′_{−2,0 }and R′_{−3,0 }for the same two-step-trellis cycle, where each group comprises two functional units that operate in series. - [0078]The reliability unit
**1400**computes the final reliabilities R′_{−U+2}=R′_{−U+2,0 }and R′_{−U+1}=R′_{−U+1,0}, where U is the reliability update length. Soft decisions S′_{i }are generated based on the final reliability values and corresponding bit decisions, e.g. according to the rule:${S}_{i}^{\prime}=\{\begin{array}{c}{R}_{i}^{\prime}\text{\hspace{1em}}\mathrm{if}\text{\hspace{1em}}\text{\hspace{1em}}{b}_{i}^{\prime}\equiv 0\\ -{R}_{i}^{\prime}\text{\hspace{1em}}\mathrm{if}\text{\hspace{1em}}{b}_{i}^{\prime}\equiv 1\end{array}.$ - [0079]It is to be understood that the embodiments and variations shown and described herein are merely illustrative of the principles of this invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention.

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US6094465 * | Mar 21, 1997 | Jul 25, 2000 | Qualcomm Incorporated | Method and apparatus for performing decoding of CRC outer concatenated codes |

US6396878 * | Feb 25, 1998 | May 28, 2002 | Nokia Telecommunications Oy | Reception method and a receiver |

US6581182 * | May 15, 2000 | Jun 17, 2003 | Agere Systems Inc. | Iterative decoding with post-processing of detected encoded data |

US7020214 * | Jul 18, 2001 | Mar 28, 2006 | Lucent Technologies Inc. | Method and apparatus for path metric processing in telecommunications systems |

US7032163 * | Aug 17, 2001 | Apr 18, 2006 | Hitachi, Ltd. | Error correction decoder for turbo code |

US7085992 * | Oct 24, 2001 | Aug 1, 2006 | Infineon Technologies Ag | Method and device for decoding a sequence of physical signals, reliability detection unit and viterbi decoding unit |

US7136413 * | Aug 23, 2002 | Nov 14, 2006 | Mediatek, Inc. | Method and apparatus for generation of reliability information with diversity |

US7222288 * | Jul 30, 2004 | May 22, 2007 | Hellosoft, Inc. | Modified soft output Viterbi algorithm for truncated trellis |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US7673224 | Sep 12, 2006 | Mar 2, 2010 | Agere Systems Inc. | Low power viterbi decoder using a novel register-exchange architecture |

US7805664 * | Oct 1, 2007 | Sep 28, 2010 | Marvell International Ltd | Likelihood metric generation for trellis-based detection and/or decoding |

US8074157 * | Dec 6, 2011 | Agere Systems Inc. | Methods and apparatus for reduced complexity soft-output viterbi detection | |

US8432780 | Apr 30, 2013 | Mediatek Inc. | Viterbi decoding apparatus using level information generator supporting different hardware configurations to generate level information to Viterbi decoder and related method thereof | |

US8762824 | Jun 28, 2010 | Jun 24, 2014 | Marvell International Ltd. | Error pattern generation for trellis-based detection and/or decoding |

US20080072127 * | Sep 12, 2006 | Mar 20, 2008 | Tuhin Subhra Chakraborty | Low power viterbi decoder using a novel register-exchange architecture |

US20090187813 * | Jul 23, 2009 | Haratsch Erich F | Methods and Apparatus for Reduced Complexity Soft-Output Viterbi Detection | |

US20100269026 * | Oct 21, 2010 | Shaohua Yang | Error pattern generation for trellis-based detection and/or decoding | |

US20110090773 * | Apr 21, 2011 | Chih-Ching Yu | Apparatus for generating viterbi-processed data using an input signal obtained from reading an optical disc | |

US20110090779 * | Apr 21, 2011 | Mediatek Inc. | Apparatus for generating viterbi-processed data | |

US20110167323 * | Jan 7, 2010 | Jul 7, 2011 | Mediatek Inc. | Error-Correcting Apparatus and Method Thereof |

Classifications

U.S. Classification | 714/792 |

International Classification | H03M13/03 |

Cooperative Classification | H03M13/4192, H03M13/395, H03M13/4153 |

European Classification | H03M13/39C, H03M13/41T3, H03M13/41S1A |

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