|Publication number||US20060180924 A1|
|Application number||US 11/393,324|
|Publication date||Aug 17, 2006|
|Filing date||Mar 30, 2006|
|Priority date||Nov 12, 2004|
|Also published as||CN1790705A, CN100411169C, US7230334, US7888786, US7948077, US8115302, US20060103011, US20070210446, US20080265406, US20080315403|
|Publication number||11393324, 393324, US 2006/0180924 A1, US 2006/180924 A1, US 20060180924 A1, US 20060180924A1, US 2006180924 A1, US 2006180924A1, US-A1-20060180924, US-A1-2006180924, US2006/0180924A1, US2006/180924A1, US20060180924 A1, US20060180924A1, US2006180924 A1, US2006180924A1|
|Inventors||Paul Andry, Evan Colgan|
|Original Assignee||Andry Paul S, Colgan Evan G|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (10), Classifications (16)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Divisional of U.S. patent application Ser. No. 10/987,985, filed on Nov. 12, 2004, which is fully incorporated herein by reference.
This invention was made with Government support under Contract No. H98230-04-C-0920 awarded by the Maryland Procurement Office. The Government has certain rights in this invention.
The present invention relates generally to apparatus and methods for packaging semiconductor IC (integrated circuit) chips with integrated cooling modules. More specifically, the present invention relates to apparatus and methods for integrating microchannel cooling modules within high-density chip packages and system-on-a-package modules comprising multiple high-performance IC chips.
In the design and manufacture of semiconductor IC chip packages and modules (e.g., SCM (single chip modules), MCMs (multi-chip modules), etc.), it is imperative to implement mechanisms that can effectively remove heat generated by IC chips, such as microprocessors or other high-performance chips, to ensure continued reliable operation of the IC chips. Effective heat removal becomes increasingly problematic as chip geometries are scaled down and operating speeds are increased, which results in increased power density. Moreover, as chip packages or electronic modules become more compact with multiple IC chips densely packed together, the increased heat density generated by operation of the chips in such close proximity can adversely affect integrated circuit components and cause physical damage to the package structure due to differences in thermal expansion of the package components. Accordingly, there is a continuing need for improved devices and methods for effectively cooling high-density and/or high-performance IC chip packages and modules.
One method of dense packaging of high performance chips, known as “system on a package”, uses a silicon carrier with electrical through vias as an additional intermediate package layer between the chips and a ceramic first level package to provide high density and high performance electrical interconnects, such as described in U.S. Pat. No. 6,593,644, entitled “System on a Package Fabricated on a Semiconductor or Dielectric Wafer with Wiring on One Face, Vias Extending Through the Wafer, and External Connections on the Opposing Face,” which is commonly assigned and fully incorporated herein by reference. Packaging structures and method described in this patent provide a number of significant advantages, but one critical factor that should be considered for practical implementations of package structures with silicon carriers is the size and thickness of such silicon carriers. For a silicon carrier to be useful, the carrier should be larger in size than the size of the chip or chip array to be mounted on the carrier. For example, the largest practical size for a high performance chip is currently about 20 mm×20 mm . Therefore, to mount a 2×2 array of such chips, the silicon carrier would need to be over 40 mm×40 mm in size.
Another factor that is considered when using silicon carriers in package structures is the thickness of the silicon carrier. It is desirable to make the silicon carrier substrate as thin as possible due the difficulties associated with forming electrical through vias and filling the vias with a conductive material and minimizing the inductance of the electrical interconnects. For example, if a silicon carrier is 0.2 mm thick and 40 mm wide, the width/thickness ratio is 200:1. As reported in the literature, a practical silicon carrier thickness is primarily limited by the ultimate aspect ratio of the through vias. In general, aspect ratio values much higher than about 10:1 are considered to be difficult to manufacture and make highly reliable. By way of example, the consortium composed mainly of Japanese Electronics companies known as the Association of Super-Advanced Electronic Technologies (ASET) has worked intensively on silicon carrier through-via technology for the past five years (see Takahashi, K. et al., “Current Status of Research and Development of Three-dimensional Chip Stacking Technology”, Jpn. J. Appl. Phys. Vol. 40, (2001) pp. 3032-3037), and such work has culminated in a reportedly robust process employing 10 um wide vias and a carrier thickness fixed at 50 um (see Takahashi, K. et al., “Process Integration of 3D Chip Stack with Vertical Interconnection”, Proc. 54th Electron. Components and Technol. Conf. Las Vegas, Nev., June 2004, pp. 601-609).
Some of the practical difficulties which occur with a large area and thin silicon carrier include increased risk of fracturing the silicon carrier during processing, bonding or assembly, as well as providing an effective means for cooling the chips mounted on the silicon carrier. It is difficult to use a conventional cooling means such as a thermal paste layer and a heat sink attached to the back surface of the chips since the force used to hold the heat sink in place and the large force used during assembly to insure a thin and uniform thermal paste layer could crack the silicon carrier. Therefore, packaging structures and methods that provide increased stiffness of a silicon carrier while providing a high performance cooling solution are highly desirable.
Exemplary embodiments of the invention generally include apparatus and methods for packaging semiconductor IC chips with integrated cooling modules. More specifically, exemplary embodiments of the invention include apparatus and methods for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips.
In general, electronic modules according to exemplary embodiments of the invention are designed such that high-performance (high power) IC chips are disposed in close proximity to an integrated cooling module (or cooling plate) for effective heat extraction. More specifically, exemplary embodiments of the invention include electronic modules which comprises an integrated cooling module and high-performance IC chips bonded directly to the cooling module. For instance, in one exemplary embodiment of the invention, the non-active surface of an IC chip can be rigidly bonded to a microchannel cooler device using solder, silver filled epoxy, or similar filled polymer.
In other exemplary embodiments of the invention, electronic modules are designed having a cooling module disposed between carrier substrates having a plurality of IC chips mounted on the carrier substrates. In such exemplary embodiments, high-performance IC chips are mounted in surface regions of the carrier substrates that are aligned with the cooling module. In other exemplary embodiments of the invention, conductive vias can be formed through the cooling module (e.g., in thermal microfins of a microchannel cooler) to provide electrical signal paths across the cooling module between the carrier substrates and/or the IC chips mounted on the carrier substrates.
In another exemplary embodiment of the invention, an electronic module comprises a first level carrier substrate and an intermediate carrier substrate bonded to the first level carrier substrate, wherein the intermediate carrier substrate comprises a plurality of IC chips flip-chip bonded thereto. A cooling device, such as a microchannel cooler, is thermally bonded to the non-active surfaces of each IC chip mounted on the intermediate carrier substrate using rigid bonding material. The cooling device is formed of a material which is thermal expansion matched to the material from which the intermediate substrate carrier is formed to reduce mechanical stresses caused by differences in thermal expansion. The microchannel cooling device provides cooling for the chips and additionally increases the structural integrity of the electronic assembly by rigidly bonding the microchannel cooler to the back surfaces of IC chips mounted on the intermediate carrier. Moreover, microchannel cooler is light weight and the bonding material can be compatible with a C4 reflow, such that the microchannel cooler could be assembled to the intermediate carrier package with the IC chips before bonding the intermediate carrier package to the first level package.
Exemplary packaging methods and structures according to the invention may be used for building a compact computer system-on-a-package comprising multiple IC processor chips, IC memory chips, and communication chips and modules, which are densely packed together with an integrated cooling module. In such embodiments, the high-performance IC processor chips are disposed in proximity to the integrated cooling module for efficient heat extraction.
These and other exemplary embodiments, aspects, features, and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
The electronic module (100) further comprises separate CIO (communication and input/output) modules (106) and (107) for corresponding IC processor chips (102) and (103), respectively. The CIO module (106) is connected to the IC processor chip (102) via an array of vertical pins, or solder columns, (108) mounted therebetween, and the CIO module (107) is connected to the IC processor chip (103) via an array of vertical pins, or solder columns, (109) mounted therebetween.
In one exemplary embodiment of the invention, each vertical pin or solder column may be formed of two separate solder bumps, wherein one solder bump originates on an IC processor chip and another solder bump originates on a corresponding CIO module, thus giving an effective “double bump” standoff height. Moreover, the IC memory chips may be thinned considerably, e.g., to 100 microns thick, using standard backside grind techniques, and the C4s used to join the IC memory chips to the corresponding IC processor chips may be reduced in height, making it possible to use more or less standard bumping techniques to assemble the module (100).
The CIO modules (106) and (107) can be bonded thermally to the non-active surfaces of the memory chips in IC memory chip arrays (104) and (105), respectively, if the CIO modules (106) and (107) need to dissipate heat through the memory chips and the IC processor chips. Alternatively, if the power of the CIO modules (106) and (107) are low, enabling heat to be easily dissipated to the surroundings, the CIO modules (106) and (107) do not have to be bonded to the respective memory chips of chip arrays (104) and (105) to the memory chips.
The CIO modules (106) and (107) are constructed to include the required electrical interconnects, bonding pads, integrated circuits/devices, I/O components, etc., that enable electrical connection/communication with other electronic components, devices, modules, power sources, etc. The IC processor chips (102) and (103) can directly communicate via a communication link provided by a flexible cable (110). Each end of the cable (110) is soldered to one of the IC processor chips (102) and (103) and disposed along the side of the module (100).
With the exemplary package structure of
In one exemplary embodiment, the non-active surfaces of the IC processor chips (102) and (103) are rigidly bonded to the cooling device (101) using a silver filled epoxy, filled polymer adhesive, filled thermoplastic or solder, or other thermally conductive bonding material with low thermal resistance. To reduce mechanical stresses, the material of the cooling device (101) is selected to have a TCE (thermal coefficient of expansion) that closely matches the TCE of the material of the IC processor chips (102) and (103). The ability to effectively use a rigid bond is limited not only by the difference in the TCEs of the materials that form the cooling device (101) and the IC chips, but also on the temperature range (cycle) in which the semiconductor package will operate or be exposed to, as well as size of the area over which the rigid bond will be formed.
In one exemplary embodiment, the cooling device (101) comprises a microchannel cooling device having a plurality of coolant inlet/outlets (101 a) to enable coolant to flow in and out of the cooling device (101). Microchannel cooling devices can be implemented for effectively cooling electronic devices under conditions of increased heat flux/high power densities (power/unit area), e.g., ˜800 W/cm2.
It is to be understood that the cooling device (300) depicted in
In one exemplary embodiment, the electronic module (200) comprises a computer “system on a package”, wherein the first carrier substrate (202) comprises an array of IC processor chips (204) and arrays of IC memory chips (206) and (207) mounted on a surface thereof, and the second carrier substrate (203) comprises an array of IC processor chips (205) and arrays of IC memory chips (208) and (209) mounted on a surface thereof. The high-performance processor chip arrays (204) and (205) are mounted active area down in surface regions of respective carrier substrates (202) and (203) that are aligned with the cooling module (201). The carrier substrates (202) and (203) comprise one or more levels of metallization to provide the required conductive lines and interconnections for signal transmission between the IC memory chips and processor chips.
Moreover, in the exemplary embodiment of
The electronic module (200) further comprises separate CIO modules (210) and (211) for corresponding IC processor chip arrays (204) and (205), respectively. The CIO module (210) is connected to the carrier substrate (202) by soldering pins or solder columns (212) and the CIO module (211) is connected to the second carrier substrate (203) by soldering pins or solder columns (213). Alternatively, the CIO modules (210) and (211) can be connected to respective carrier substrates (202) and (203) using a pin and socket connection, as is well known to those of ordinary skill in the art. The CIO modules (210) and (211) are constructed to include the required electrical interconnects, bonding pads, integrated circuits/devices, I/O components, etc., that enable electrical connection/communication with other electronic components, devices, modules, power sources, etc.
In the exemplary embodiment of
In another exemplary embodiment, the cooling device (201) can be made the same size as the carrier substrates (202) and (203), in which case the mechanical support structures (214) and (215) would not be needed. With this exemplary embodiment, since the power dissipation rates are generally lower in the memory regions, the cooling channels in the cooling device (201) can be designed accordingly to handle higher power density in the processor region and relatively lower power density in the memory regions.
In one exemplary embodiment, the carrier substrates (202) and (203) are rigidly bonded to the cooling device (201) using a silver filled epoxy, filled polymer adhesive, filled thermoplastic or solder, or other thermally conductive bonding material with low thermal resistance. To reduce mechanical stresses in the thermal interface between the cooling module (201) and carrier substrates (202) and (203) due to thermal expansion/contraction, the material of the cooling device (201) is selected to have a TCE that closely matches the TCE of the material of the carrier substrates (202) and (203). Moreover, mechanical stresses in the thermal interface between the cooling device (201) and the carrier substrates (202) and (203) are reduced by limiting the size of the cooling device (201) to be aligned with only the high-performance IC processor chips. In particular, the cooling device (201) is made smaller than the carrier substrates (202) and (203) and thus, the surface area over which the rigid bond (or other thermal interface) between the cooling device and carrier substrates is limited (as compared to forming the cooling device (201) to have the same planar dimensions as the carrier substrates).
In another exemplary embodiment of the invention, the cooling device (201) is constructed to have a plurality of conducting through vias that provide connection paths between the first and second carrier substrates (202) and (203). In this exemplary embodiment, the surface regions of the carrier substrates (202) and (203) that are aligned with the cooling module (201) have bonding pads/connectors that can be bonded (via solder balls) to exposed portions of the conducting through vias (or other interconnects) on the respective mating surfaces of the cooling module (201) to provide electrical connections between IC chips on the different silicon carriers. Moreover, thermal conduction from the high performance processor chip arrays (204) and (205) to their respective silicon carriers (202) and (203) can be enhanced by filling the empty space among the solder ball bonds between the processor chips and silicon carriers as much as possible with additional solder balls (i.e. thermal via's) and by using a thermally conductive, and electrically insulating, underfill material. Additional structures to reduce the thermal conductivity in the silicon carriers and in the chip metallization levels can be formed, aligned with the additional solder balls, as is known to those of ordinary skill in the art.
It is to be appreciated that in one exemplary embodiment when the IC memory chips and carrier substrates (202) and (203) are made from silicon (or other TCE matched materials) the area density of the individual solder connections may be increased and/or the height of solder connections may be reduced to provide a further reduction in thermal resistance from the IC memory chip arrays (204) and (205) to the respective carrier substrates (202) and (203). Indeed, it is advantageous to keep the thermal resistance as small as possible to avoid a large delta T, which is the leading factor in chip-to-carrier stress (assuming matched TCEs). This approach is useful with high-density micro joins with pitches as low as “1 on “2” mil.
The carrier substrate (502) is constructed to comprise high density wiring on the top surface thereof for providing electrical interconnections to the IC chips (503) and (504) via high-density solder bump arrays (B3) and (B4) (˜0.05 mm pitch), respectively. Moreover, the intermediate carrier substrate (502) comprises a plurality of conductive vias that are formed through the carrier substrate (502) to enable electrical connections with the first level package substrate (501) via the solder bump array (B2). The intermediate carrier substrate (502) and ceramic substrate (501) are designed to provide a space transformation between electrical connections between the fine pitch solder ball arrays (B3 and B4) and the printed circuit board bond ball array (B1) and to interconnect multiple chips on the intermediate carrier substrate (502).
The electronic module (500) further comprises an integrated microchannel cooling device (505) that is thermally bonded to the non-active surfaces of the IC chips (503) and (504) via respective rigid thermal bonds (B5) and (B6). The bonding material used for the rigid thermal bonds (B5) and (B6) may comprise any suitable material with low thermal resistivity, such as a solder, metal layer, Ag epoxy, or a filled polymer, to thereby allow sufficient heat conduction from the chips to the microchannel plate (506). A low thermal resistance bond such as a metal joint, solder joint, or a filled thermal adhesive such as a Ag epoxy, or other joining means could be used, as long as the bonding thickness is sufficiently thin and compatible with the cooling requirements. Further, it is desirable that the bonds (B5) and (B6) are reworkable, so that the microchannel cooler (505) can be removed from the chips, when necessary, to either replace the microchannel cooler device (505) or replace one or more of the chips (503) and (504).
In one exemplary embodiment, the microchannel cooler module (505) comprises a microchannel plate (506) connected to a manifold plate (507) via bond (B7). The microchannel cooling device (505) extends over the IC chips and is approximately the same size, or slightly larger than, the intermediate carrier substrate (502). The microchannel and manifold plates (506) and (507) may be formed from silicon substrates, or other materials having TCE that matches the TCE of the material forming the IC chips (503) and (504). The microchannel plate (506) comprises a plurality of microfins (506 a) that define channels (506 b), which are formed in surface regions of the microchannel plate (506) that are aligned with the IC chips (503) and (504). Further, the manifold plate (507) (or manifold cover), which is bonded to the microchannel plate (506), comprises a plurality of fluid manifolds formed therein, wherein each fluid manifold comprises a corresponding manifold channel (507 b) formed in one surface the manifold plate (507) and a corresponding pattern/series of fluid vias (507 a) that form openings which extend from the opposing surface of the manifold plate (507) to various points along the corresponding manifold channel (507 b).
The microchannel and manifold plates (506) and (507) may be formed using the methods described in U.S. patent application Ser. No. 10/883,392, filed Jul. 1, 2004, entitled “Apparatus and Methods for Microchannel Cooling of Semiconductor Integrated Circuit Packages”, which is commonly assigned and fully incorporated herein by reference. In general, this application describes methods for constructing integrated microchannel cooler devices that include supply/return manifolds and microchannels/microfins which are structured, patterned, dimensioned and/or arranged in a manner that minimizes pressure drop and increases uniformity of fluid flow and distribution along coolant flow paths, as well as maintain the structural integrity of the manifold plate to prevent breakage during manufacturing. For instance, as explained in detail in U.S. Ser. No. 10/883,392, the manifold plate (507) is designed such that the inlets/outlets (507 a) for a given manifold channel (507 b) are formed as a series of circular openings, or openings with rounded corners, arranged in a zig-zag pattern, to reduce wafer cracking during manufacturing. The manifold channel (507 b) comprises tapered channel segments formed between the circular openings on the plate surface that faces the microchannels. The manifold is designed to reduce the potential of wafer breakage by using circular openings to minimize stress concentrations which can serve as crack nucleation sites, minimizing the total cavity area of the channel manifolds by using recessed regions of the microchannel pattern to act as a manifold in conjunction with the manifold channels, and avoid aligning the cavities along the (100) Si cleavage planes. In another exemplary embodiment of the invention, an integrated microchannel cooler device (505) may be formed from a single plate that is constructed with both microchannels and supply/return manifolds structures using the methods described in the above incorporated application.
The microchannel plate (506) and manifold plate (507) are bonded using bonding material (B7) that is sufficient to provide a watertight seal, but the bond (B7) does not have to provide a low thermal resistance. Accordingly, bonding methods such as direct wafer bonding, fusion bonding, anodic bonding, glass frit bonding, solder bonding, polymer adhesive bonding, or any other suitable bonding method may be used to join the microchannel and manifold plates (506) and (507).
The electronic module (500) further comprises a gasket (508) and package cap (509). The package cap (509) comprises fluid inlet/outlet manifolds (509 a) that are aligned to corresponding inlets/outlets (507 a) of the microchannel cooler device (505). The package cap (509) is connected to the back surface of the microchannel cooler (505) via the gasket (508). In one exemplary embodiment, the gasket (508) is adhered to both the microchannel cooler (505) and the package cap (509) using a high temperature epoxy or other suitable adhesive. In the exemplary embodiment of
For instance, the fluid distribution manifolds (509 a) can be designed in a manner to minimize overall system pressure drop by using variable cross-sectional fluid supply/return channels for delivering coolant fluid to/from integrated microchannel cooler devices. Moreover, with the exemplary microchannel cooling device (505) depicted in
With the higher power-density chip (601), it is desirable to have a lower total thermal resistance in the thermal bond (b1) between the chip (601) and the microchannel cooler device (605) to maintain the same maximum junction temperature as compared to the lower power density chips (602) and (603). In particular, when assembling a microchannel cooler (605) over multiple chips (601˜603) on a carrier (604) as depicted in the exemplary embodiment of
As discussed above, the use of a silicon carrier has a number of significant advantages such as using finer pitch electrical connections to the chips to provide greater electrical signaling capacity and greater wiring capacity. However, silicon carriers are difficult to cool using conventional methods because of their limited thickness and large area. A typical silicon carrier is between about 50 microns and about 200 microns thick (and could be as thick as 500 microns), but the lateral size could be 4 or 5 cm along each edge.
The exemplary package structures of
Although exemplary embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present system and method is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as defined by the appended claims.
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|US7468886||Mar 5, 2007||Dec 23, 2008||International Business Machines Corporation||Method and structure to improve thermal dissipation from semiconductor devices|
|US7724527||Aug 25, 2008||May 25, 2010||International Business Machines Corporation||Method and structure to improve thermal dissipation from semiconductor devices|
|US7928562 *||Jul 22, 2008||Apr 19, 2011||International Business Machines Corporation||Segmentation of a die stack for 3D packaging thermal management|
|US8030754||Jan 31, 2007||Oct 4, 2011||Hewlett-Packard Development Company, L.P.||Chip cooling channels formed in wafer bonding gap|
|US8035218||Nov 3, 2009||Oct 11, 2011||Intel Corporation||Microelectronic package and method of manufacturing same|
|US8063482 *||Jun 30, 2006||Nov 22, 2011||Intel Corporation||Heat spreader as mechanical reinforcement for ultra-thin die|
|US8642386||Aug 9, 2011||Feb 4, 2014||Intel Corporation||Heat spreader as mechanical reinforcement for ultra-thin die|
|WO2008042193A2 *||Sep 26, 2007||Apr 10, 2008||Intel Corp||Cold plate and mating manifold plate for ic device cooling system enabling the shipment of cooling system pre-charged with liquid coolant|
|WO2008094646A1 *||Jan 31, 2008||Aug 7, 2008||Hewlett Packard Development Co||Chip cooling channels formed in wafer bonding gap|
|WO2011056306A2 *||Sep 20, 2010||May 12, 2011||Intel Corporation||Microelectronic package and method of manufacturing same|
|U.S. Classification||257/712, 257/E23.08, 257/E23.098, 257/E25.013|
|Cooperative Classification||H01L2924/01019, H01L2224/32245, H01L2224/16225, H01L2225/06517, H01L25/0657, H01L23/473, H01L2225/06589, H01L2924/15311, H01L2224/73253|
|European Classification||H01L25/065S, H01L23/473|