US20060189127A1 - Method to improve palanarity of electroplated copper - Google Patents
Method to improve palanarity of electroplated copper Download PDFInfo
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- US20060189127A1 US20060189127A1 US11/410,229 US41022906A US2006189127A1 US 20060189127 A1 US20060189127 A1 US 20060189127A1 US 41022906 A US41022906 A US 41022906A US 2006189127 A1 US2006189127 A1 US 2006189127A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
- H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D3/00—Electroplating: Baths therefor
- C25D3/02—Electroplating: Baths therefor from solutions
- C25D3/38—Electroplating: Baths therefor from solutions of copper
-
- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
- C25D5/10—Electroplating with more than one layer of the same or of different metals
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- C—CHEMISTRY; METALLURGY
- C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
- C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- C25D7/00—Electroplating characterised by the article coated
- C25D7/12—Semiconductors
- C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
Definitions
- the invention relates to the general field of integrated circuits with particular reference to filling trenches with metal.
- Accelerators serve to increase the deposition rate during electroplating. They are usually small organic molecules containing a polar sulfur, oxygen, or nitrogen functional group. In addition to increasing the deposition-rate, they promote denser nucleation which leads to the growth of films having a finer grain structure. Accelerators are usually present in the plating bath at a low concentration level (1-25 ppm).
- Suppressors are additives that reduce the plating rate and are usually present in the plating bath at higher concentrations (200-2,000 ppm), so that their concentration at the interface is not strongly dependent on their rate of mass transfer or diffusion to the wafer surface. They are generally polymeric surfactants with high molecular weight such as polyethylene glycol (PEG). The suppressor molecules slow down the deposition rate by adsorbing on the wafer surface where they form a diffusion barrier.
- PEG polyethylene glycol
- Levelers are additives whose purpose is to reduce surface roughness. They are similar to suppressors in that they reduce deposition rate. However, they are present in very small concentrations ( ⁇ 25 ppm) so their blocking effects at the surface are highly localized. The net effect is that they selectively reduce deposition on the high spots thereby giving the low spots a chance to ‘catch up’.
- narrow trenches typically having widths less than about 1 microns
- wide trenches typically having widths greater than about 2 microns.
- FIG. 1 Seen there, in cross-section, is a portion of a substrate (typically a silicon wafer) 11 in whose upper surface several narrow trenches 12 and one wide trench 13 have been formed. After electro-deposition of metal layer 14 the latter is found to have the profile shown, i.e. it locally thicker over the narrow trenches and locally thinner over the wide trench.
- Another object of at least one embodiment of the present invention has been that said trenches have at least two different widths.
- Still another object of at least one embodiment of the present invention has been that, at the conclusion of said process, said metal layer has a planar surface.
- the plating bath used during the first step is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches.
- the net result is a final layer having a planar surface, with all trenches being properly filled.
- FIG. 1 illustrates a problem associated with filling, through electroplating, a surface that contains trenches whose widths vary over a wide range.
- FIG. 2 is a plot of deposition rate vs. concentration for two different accelerator additives.
- FIG. 3 is a schematic cross-section through a substrate part way through the process of the present invention.
- FIG. 4 is a schematic cross-section through a substrate at the conclusion of the process of the present invention.
- accelerators are 3-sulfopropyldisulfide, 41 sulfonated acetylthiourea, 3-mercapto-1-propanesulfonate (MPSA), and dibenzyl-dithio-carbammate.
- the precise concentration of accelerator additive that is needed to produce a given deposition rate can vary from one additive to another.
- FIG. 2 which compares the effects of two different chemicals when added to a plating bath as an accelerator.
- Curves 21 and 22 are plots of ‘potential difference needed to initiate plating’ (which equates with film growth rate) vs. additive concentration in parts per thousand.
- the chemical associated with curve 21 is less effective than the one associated with curve 22 .
- Examples of the former include 3-sulfopropyldisulfide, while examples of the latter include 3-mercapto-1-propanesulfonate (MPSA).
- the process of the present invention begins with the provision of silicon wafer 11 (as seen for example in FIG. 1 ) in whose upper surface there are multiple trenches having a range of widths. These trenches will have been lined with a barrier layer to contain the copper.
- This barrier layer may be of a material such as TiN that is sufficiently conductive to serve as a cathode for the copper deposition and/or an additional seed layer of copper, or copper doped with titanium, magnesium, zirconium, tin, or zinc, may first be laid down as a seed layer.
- an aqueous solution of at least one copper salt is also provided at the start of the process.
- a typical formulation for this aqueous solution would be 10-50 g/l cap 1 SGHS, 5-300 g/l H 2 SO 4 , and 20-100 ppm HCl.
- Two plating solutions are then formed from this. Each is the original aqueous copper solution to which an accelerator chemical has been added. A different chemical may be used for each plating solution and, in general, the additive concentration in the second plating solution will be greater than in the first one.
- accelerator additives suitable for use in the first plating solution include (but are not limited to) 3-sulfopropyldisulfide and 3-mercapto-1-propanesulfonate (MPSA) at a concentration that is between about 10 and 100 ppm. Additionally, the first plating solution will include a short chain polymer (less than about 200 units per chain) having low molecular weight (less than about 10,000).
- our preferred accelerator additive has been 3-sulfopropyl disulfide at a concentration is between about 10 and 50 ppm, but other accelerator additives such as sulfonated acetylthiourea, 3-mercapto-1-propanesulfonate, dibenzyl-dithio-carbammate-, 2-mercaptoethanesulfonate, or n,n-dimethyl-dithiocabamic acid-(3-sulfopropyl)ester could also have been used. Additionally, the second plating solution will include a long chain polymer (more than about 1,000 units per chain) having high molecular weight (more than about 50,000).
- the wafer is now transferred to a second bath that contains the second of the two plating solutions mentioned above, i.e. to a plating solution in which there is dissolved a more powerful accelerator additive and/or a higher concentration of accelerator.
- Electroplating is now resumed.
- the plating solution in the second bath is now such as to be optimized for filling wide trenches. The result is that electroplated material in the trench builds up faster than outside it so that electroplated layer 44 ( FIG. 4 ) that is obtained once the wide trenches have been overfilled, ends up with a surface that is essentially planar, for an additional copper thickness that is between about 0.3 and 0.5 microns.
- Two other embodiments of the present invention apply the above process with some modifications. Both additional embodiments still make use of two different solutions but only a single plating chamber, or container, is required. Such an approach is useful, for example, in a small-scale operation such as a pilot line.
- the wafer when the first plating step has been completed (narrow trenches overfilled), the wafer is left in place (so that electrical connections to it need not be disconnected), the first plating solution is emptied out of the container, is replaced by the second plating solution, and plating is resumed.
- the wafer when the first plating step has been completed (narrow trenches overfilled), the wafer is left in place (so that electrical connections to it need not be disconnected), while the first plating solution is gradually and continuously replaced by the second plating solution.
- the step can be further simplified by merely adding additional accelerant to the bath.
Abstract
Narrow trenches in a substrate tend to fill more rapidly than wide trenches This results in a non-planar surface once all trenches have been filled. The present invention solves this problem by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.
Description
- This application is a divisional of U.S. application Ser. No. 10/763,306 filed Jan. 23, 2004 entitled, “Method to Improve of Electroplated Copper”.
- The invention relates to the general field of integrated circuits with particular reference to filling trenches with metal.
- With the introduction of the damascene process, the formation of wires by filling trenches has become routine. Additionally, particularly for the case of copper-filled trenches, the method of choice for depositing the metal has been electroplating. However, as trenches have become narrower and narrower, it has become necessary to employ a range of additives that need to be included in the plating solution to give the best filling results. The technology involved is further complicated by the fact that the effects of these multiple additives are often interactive.
- We can identify three broad additive types:
- Accelerators serve to increase the deposition rate during electroplating. They are usually small organic molecules containing a polar sulfur, oxygen, or nitrogen functional group. In addition to increasing the deposition-rate, they promote denser nucleation which leads to the growth of films having a finer grain structure. Accelerators are usually present in the plating bath at a low concentration level (1-25 ppm).
- Suppressors are additives that reduce the plating rate and are usually present in the plating bath at higher concentrations (200-2,000 ppm), so that their concentration at the interface is not strongly dependent on their rate of mass transfer or diffusion to the wafer surface. They are generally polymeric surfactants with high molecular weight such as polyethylene glycol (PEG). The suppressor molecules slow down the deposition rate by adsorbing on the wafer surface where they form a diffusion barrier.
- Levelers are additives whose purpose is to reduce surface roughness. They are similar to suppressors in that they reduce deposition rate. However, they are present in very small concentrations (<25 ppm) so their blocking effects at the surface are highly localized. The net effect is that they selectively reduce deposition on the high spots thereby giving the low spots a chance to ‘catch up’.
- It has been known for some time that narrow trenches (typically having widths less than about 1 microns) tend to fill more rapidly than wide trenches (typically having widths greater than about 2 microns). This results in problems of the type schematically illustrated in
FIG. 1 . Seen there, in cross-section, is a portion of a substrate (typically a silicon wafer) 11 in whose upper surface severalnarrow trenches 12 and onewide trench 13 have been formed. After electro-deposition ofmetal layer 14 the latter is found to have the profile shown, i.e. it locally thicker over the narrow trenches and locally thinner over the wide trench. - The general approach that the prior art has taken to dealing with this problem has been to try to balance the concentrations of the various additives so as to find a single formulation that works well for both narrow and wide trenches simultaneously. As will be shown, the present invention has abandoned this approach in favor of a two-step plating method.
- A routine search of the prior art was performed with the following references of interest being found:
- In U.S. Pat. No. 6,346,479 B1, Woo et al. show an electroplating process of first filling holes using an electroplating process that has been optimized for conformal coating followed by a second electroplating step that has been optimized for non-conformal coating. Trench width is not explicitly taught as a criterion for determining which solution to use where.
- Chen et al., in U.S. Pat. No. 6,207,222 B1, show multi-step plating to fill a Cu dual damascene opening while U.S. Pat. No. 6,140,241 (Shue et al.), U.S. Pat. No. 6,136,707 (Cohen), and U.S. Pat. No. 5,814,557 (Venkatranman) all show related plating processes.
- It has been an object of at least one embodiment of the present invention to provide a process for filling trenches in a substrate by depositing a metal layer through electroplating.
- Another object of at least one embodiment of the present invention has been that said trenches have at least two different widths.
- Still another object of at least one embodiment of the present invention has been that, at the conclusion of said process, said metal layer has a planar surface.
- These objects have been achieved by performing the electro-deposition in two steps. The plating bath used during the first step, is optimized for filling narrow trenches while the plating bath used during the second step, is optimized for filling wide trenches. The net result is a final layer having a planar surface, with all trenches being properly filled.
-
FIG. 1 illustrates a problem associated with filling, through electroplating, a surface that contains trenches whose widths vary over a wide range. -
FIG. 2 is a plot of deposition rate vs. concentration for two different accelerator additives. -
FIG. 3 is a schematic cross-section through a substrate part way through the process of the present invention. -
FIG. 4 is a schematic cross-section through a substrate at the conclusion of the process of the present invention. - Some examples of accelerators are 3-sulfopropyldisulfide, 41 sulfonated acetylthiourea, 3-mercapto-1-propanesulfonate (MPSA), and dibenzyl-dithio-carbammate.
- The precise concentration of accelerator additive that is needed to produce a given deposition rate can vary from one additive to another. We illustrate this in
FIG. 2 which compares the effects of two different chemicals when added to a plating bath as an accelerator.Curves curve 21 is less effective than the one associated withcurve 22. Examples of the former include 3-sulfopropyldisulfide, while examples of the latter include 3-mercapto-1-propanesulfonate (MPSA). - The process of the present invention begins with the provision of silicon wafer 11 (as seen for example in
FIG. 1 ) in whose upper surface there are multiple trenches having a range of widths. These trenches will have been lined with a barrier layer to contain the copper. This barrier layer may be of a material such as TiN that is sufficiently conductive to serve as a cathode for the copper deposition and/or an additional seed layer of copper, or copper doped with titanium, magnesium, zirconium, tin, or zinc, may first be laid down as a seed layer. - Also provided at the start of the process is an aqueous solution of at least one copper salt. A typical formulation for this aqueous solution would be 10-50 g/l cap1 SGHS, 5-300 g/l H2SO4, and 20-100 ppm HCl. Two plating solutions are then formed from this. Each is the original aqueous copper solution to which an accelerator chemical has been added. A different chemical may be used for each plating solution and, in general, the additive concentration in the second plating solution will be greater than in the first one.
- Examples of accelerator additives suitable for use in the first plating solution include (but are not limited to) 3-sulfopropyldisulfide and 3-mercapto-1-propanesulfonate (MPSA) at a concentration that is between about 10 and 100 ppm. Additionally, the first plating solution will include a short chain polymer (less than about 200 units per chain) having low molecular weight (less than about 10,000).
- For the second plating solution, our preferred accelerator additive has been 3-sulfopropyl disulfide at a concentration is between about 10 and 50 ppm, but other accelerator additives such as sulfonated acetylthiourea, 3-mercapto-1-propanesulfonate, dibenzyl-dithio-carbammate-, 2-mercaptoethanesulfonate, or n,n-dimethyl-dithiocabamic acid-(3-sulfopropyl)ester could also have been used. Additionally, the second plating solution will include a long chain polymer (more than about 1,000 units per chain) having high molecular weight (more than about 50,000).
- Then, in a bath that contains the first plating solution, electroplating onto the wafer surface is initiated and allowed to proceed until sufficient copper has been deposited to overfill all trenches whose width is less than about 0.2 microns while under-filling all trenches whose width exceeds this. At this point, the thickness of deposited copper would typically be between about 0.1 and 0.2 microns. The result is illustrated in
FIG. 3 where it can be seen that thenarrow trenches 12 have uniformly over-filled whilewide trench 13 is till only partially filled. It is clear that if electroplating were allowed to continue under these conditions, the result would be as was seen inFIG. 1 . - Instead, in a departure from the prior art, the wafer is now transferred to a second bath that contains the second of the two plating solutions mentioned above, i.e. to a plating solution in which there is dissolved a more powerful accelerator additive and/or a higher concentration of accelerator. Electroplating is now resumed. The plating solution in the second bath is now such as to be optimized for filling wide trenches. The result is that electroplated material in the trench builds up faster than outside it so that electroplated layer 44 (
FIG. 4 ) that is obtained once the wide trenches have been overfilled, ends up with a surface that is essentially planar, for an additional copper thickness that is between about 0.3 and 0.5 microns. - Two other embodiments of the present invention apply the above process with some modifications. Both additional embodiments still make use of two different solutions but only a single plating chamber, or container, is required. Such an approach is useful, for example, in a small-scale operation such as a pilot line.
- In the first of these additional embodiments, when the first plating step has been completed (narrow trenches overfilled), the wafer is left in place (so that electrical connections to it need not be disconnected), the first plating solution is emptied out of the container, is replaced by the second plating solution, and plating is resumed.
- In the second additional embodiment, when the first plating step has been completed (narrow trenches overfilled), the wafer is left in place (so that electrical connections to it need not be disconnected), while the first plating solution is gradually and continuously replaced by the second plating solution. If the only difference between the two plating solutions is in the concentration of the accelerator additive, the step can be further simplified by merely adding additional accelerant to the bath. In this embodiment, there is no need to terminate electro-deposition while the solutions are being changed it being, in fact, advantageous to allow deposition to continue since, as the plating solution composition changes, it becomes steadily more suited to wider and wider trenches.
- Table I below provides a summary of the composition of the two baths:
Concentration Chemical Components Bath 1 Bath 2 VMS Cu/H2S04/Cl 3060 g/L Cu, 5-30 g/L 15-60 g/L Cu, 5-300 g/L H2S04 and 20-100 mg/L H2S04 and 20-100 mg/L (ppm) C1 (ppm) CI Accelerator Bis (3-sulfopropyl) disulfide, 10-30 ppm 5-10 ppm 3-mercapto-propylsulfonic acid, 3-sulfopropul)ester Suppressor Polyalkylene glycols, 50-200 ppm 200-1000 ppm Polyoxyalkyene glycols, copolymer of polyoxyalkyenes Leveler Alkylated polyalkyleneimine, 0 ppm 1-20 ppm 2-mercatothiazoline
Claims (15)
1. A process for filling trenches with copper, comprising:
providing a silicon wafer having an upper surface in which are a plurality of trenches that have at least two different widths, all trenches being lined with a conductive barrier layer;
providing an aqueous solution that comprises at least one copper salt;
forming a first plating solution that contains a first concentration, in said aqueous solution, of a first accelerator additive;
forming a second plating solution that contains a second concentration, in said aqueous solution, of a second accelerator additive, said second concentration being greater than said first concentration;
filling a container with said first plating solution and immersing said wafer therein, then electroplating onto said upper surface a first thickness of copper that is sufficient to overfill all trenches whose width is less than an amount while under-filling all trenches whose width is greater than said amount;
while leaving said wafer in container, replacing said first plating solution with said second plating solution; and
then electroplating on said wafer a second thickness of copper that is sufficient to overfill all trenches.
2. The process described in claim 1 wherein the step, of replacing said first plating solution with said second plating solution, further comprises a continuous change in accelerator concentration without interruption of electroplating.
3. The process described in claim 1 wherein said aqueous solution further comprises 10-50 g/L copper salts, 5-300 g/L H2SO4, and 20-100 ppm HCI.
4. The process described in claim 1 wherein said first accelerator additive is 3-mercapto-1propanesulfonate at a concentration that is between about 10 and 100 ppm.
5. The process described in claim 1 wherein said second accelerator additive is 3sulfopropyl disulfide.
6. The process described in claim 5 wherein said second accelerator additive concentration is between about 10-100 ppm.
7. The process described in claim 1 wherein said accelerator additive is sulfonated sulfonated acetylthiourea, 3-mercapto-1propanesulfonate, dibenzyl-dithio-carbammat, 2-mercaptoethanesulfonate, or n,n-dimethyl-dithiocabamic acid-(3-sulfopropyl)ester.
8. A process for filling trenches with copper, comprising:
providing a silicon wafer having an upper surface in which are a plurality of trenches that have at least two different widths, all trenches being lined with a seed layer;
providing an aqueous solution that comprises at least one copper salt;
forming a first plating solution that contains a first concentration, in said aqueous solution, of a first accelerator additive;
forming a second plating solution that contains a second concentration, in said aqueous solution, of a second accelerator additive, said second concentration being greater than said first concentration;
filling a plating bath with said first plating solution and immersing said wafer therein, then electroplating onto said seed layer a first thickness of copper that is sufficient to overfill all trenches whose width is less than an amount while under-filling all trenches whose width is greater than said amount;
while leaving said wafer in said plating bath, replacing said first plating solution with said second plating solution; and
then electroplating on said wafer a second thickness of copper that is sufficient to overfill all trenches.
9. The process described in claim 8 wherein the step, of replacing said first plating solution with said second plating solution, further comprises a continuous change in accelerator concentration without interruption of electroplating.
10. The process described in claim 9 wherein said aqueous solution further comprises 10-50 g/L copper salts, 5-300 g/L H.sub.2SO.sub.4, and 20-100 ppm HCl.
11. The process described in claim 9 wherein said first accelerator additive is (3-sulfopropyl) disulfide, 3-mercapto-propylsulfonic at a concentration that is between about 10-100 ppm.
12. The process described in claim 9 wherein said second accelerator additive is 3sulfopropyl disulfide.
13. The process described in claim 12 wherein said second accelerator additive concentration is between about 10-100 ppm.
14. The process described in claim 9 wherein said second accelerator additive is sulfonated acetylthiourea, 3-mercapto-1propanesulfonate, dibenzyl-dithio-carbammat, 2-mercaptoethanesulfonate, or n,n-dimethyl-dithiocabamic acid-(3-sulfopropyl)ester.
15. The process described in claim 8 wherein said seed layer is copper, or copper doped with titanium, magnesium, zirconium, tin, or zinc.
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US10/763,306 US7064068B2 (en) | 2004-01-23 | 2004-01-23 | Method to improve planarity of electroplated copper |
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US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US8225239B2 (en) | 2006-03-09 | 2012-07-17 | Tela Innovations, Inc. | Methods for defining and utilizing sub-resolution features in linear topology |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US7989347B2 (en) | 2006-03-30 | 2011-08-02 | Freescale Semiconductor, Inc. | Process for filling recessed features in a dielectric substrate |
US7577049B1 (en) | 2006-08-08 | 2009-08-18 | Tela Innovations, Inc. | Speculative sense enable tuning apparatus and associated methods |
CN101517131B (en) * | 2006-10-03 | 2011-02-16 | 三井金属矿业株式会社 | Method of preparing electrolytic copper solution acidified with sulfuric acid, sulfuric-acid-acidified electrolytic copper solution prepared by the preparation method, and electrodeposited copper film |
US7979829B2 (en) * | 2007-02-20 | 2011-07-12 | Tela Innovations, Inc. | Integrated circuit cell library with cell-level process compensation technique (PCT) application and associated methods |
US8286107B2 (en) | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
MY152456A (en) | 2008-07-16 | 2014-09-30 | Tela Innovations Inc | Methods for cell phasing and placement in dynamic array architecture and implementation of the same |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
EP2483456A2 (en) * | 2009-09-28 | 2012-08-08 | Basf Se | Wafer pretreatment for copper electroplating |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
GB201021326D0 (en) * | 2010-12-16 | 2011-01-26 | Picofluidics Ltd | Electro chemical deposition apparatus |
US9269612B2 (en) * | 2011-11-22 | 2016-02-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms of forming damascene interconnect structures |
CN103290438B (en) * | 2013-06-25 | 2015-12-02 | 深圳市创智成功科技有限公司 | For copper electroplating solution and the electro-plating method of wafer-level packaging |
CN105002527B (en) * | 2015-07-31 | 2017-06-16 | 广东光华科技股份有限公司 | Leveling agent solution and its preparation method and application |
CN112672521B (en) * | 2021-01-19 | 2022-04-22 | 中国电子科技集团公司第二十九研究所 | Method and device for processing blind groove structure of multilayer board |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5814557A (en) * | 1996-05-20 | 1998-09-29 | Motorola, Inc. | Method of forming an interconnect structure |
US6136707A (en) * | 1999-10-02 | 2000-10-24 | Cohen; Uri | Seed layers for interconnects and methods for fabricating such seed layers |
US6140241A (en) * | 1999-03-18 | 2000-10-31 | Taiwan Semiconductor Manufacturing Company | Multi-step electrochemical copper deposition process with improved filling capability |
US6207222B1 (en) * | 1997-08-19 | 2001-03-27 | Applied Materials, Inc. | Dual damascene metallization |
US6346479B1 (en) * | 2000-06-14 | 2002-02-12 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device having copper interconnects |
US6943112B2 (en) * | 2002-07-22 | 2005-09-13 | Asm Nutool, Inc. | Defect-free thin and planar film processing |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5815579A (en) * | 1995-03-08 | 1998-09-29 | Interval Research Corporation | Portable speakers with phased arrays |
-
2004
- 2004-01-23 US US10/763,306 patent/US7064068B2/en not_active Expired - Fee Related
-
2006
- 2006-04-24 US US11/410,229 patent/US20060189127A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5814557A (en) * | 1996-05-20 | 1998-09-29 | Motorola, Inc. | Method of forming an interconnect structure |
US6207222B1 (en) * | 1997-08-19 | 2001-03-27 | Applied Materials, Inc. | Dual damascene metallization |
US6140241A (en) * | 1999-03-18 | 2000-10-31 | Taiwan Semiconductor Manufacturing Company | Multi-step electrochemical copper deposition process with improved filling capability |
US6136707A (en) * | 1999-10-02 | 2000-10-24 | Cohen; Uri | Seed layers for interconnects and methods for fabricating such seed layers |
US6346479B1 (en) * | 2000-06-14 | 2002-02-12 | Advanced Micro Devices, Inc. | Method of manufacturing a semiconductor device having copper interconnects |
US6943112B2 (en) * | 2002-07-22 | 2005-09-13 | Asm Nutool, Inc. | Defect-free thin and planar film processing |
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