US20060208755A1 - In-tray burn-in board, device and test assembly for testing integrated circuit devices in situ on processing trays - Google Patents
In-tray burn-in board, device and test assembly for testing integrated circuit devices in situ on processing trays Download PDFInfo
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- US20060208755A1 US20060208755A1 US11/437,198 US43719806A US2006208755A1 US 20060208755 A1 US20060208755 A1 US 20060208755A1 US 43719806 A US43719806 A US 43719806A US 2006208755 A1 US2006208755 A1 US 2006208755A1
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- burn
- board
- integrated circuit
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- circuit devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2893—Handling, conveying or loading, e.g. belts, boats, vacuum fingers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
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- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
A burn-in board for burn-in and electrical testing of a plurality of integrated circuit devices that are disposed in one or more processing trays may include a substrate having an interface surface and a plurality of electrical contacts disposed on the interface surface for establishing, through engagement with the one or more processing trays, electrical communication between the leads of the integrated circuit devices and a tester. One or more ports may be defined in the substrate so as to extend between the interface surface and another surface of the substrate wherein the port or ports are sized and configured to enable application of a negative pressure between the substrate and the one or more processing trays upon engagement of the substrate therewith and upon application of a vacuum through the one or more ports.
Description
- This application is a continuation of application Ser. No. 11/093,920 filed Mar. 22, 2005, pending, which is a divisional of application Ser. No. 10/917,875, filed Aug. 12, 2004, now U.S. Pat. No. 6,927,596, issued Aug. 9, 2005, which is a divisional of application Ser. No. 10/164,974, filed Jun. 6, 2002, now U.S. Pat. No. 6,815,967, issued Nov. 9, 2004, which is a continuation of application Ser. No. 09/510,793, filed Feb. 23, 2000, now U.S. Pat. No. 6,476,629, issued Nov. 5, 2002.
- 1. Field of the Invention
- The present invention relates generally to the manufacture and processing of integrated circuit devices. Specifically, the present invention relates to an in-tray burn-in board and method of use for performing burn-in and electrical testing of a plurality of integrated circuit devices disposed in processing trays.
- 2. State of the Art
- During the manufacture of integrated circuit (IC) devices, processing trays—also referred to as component trays, in-process trays, or carrier trays—are typically used throughout many phases of production for handling IC devices. Processing trays may be configured for use with a number of different types of packaged IC devices, including dual in-line packages (DIPs), zigzag in-line packages (ZIPs), thin small outline packages (TSOPs), small outline J-lead packages (SOJs), ball-grid arrays (BGAs), pin-grid arrays (PGAs), quad flat packages (QFPs), pad array carriers (PACs), and plastic leaded chip carriers (PLCCs). Processing trays may also be designed for handling bare, or unpackaged, semiconductor dice. The configuration of processing trays varies depending on the type of IC device that a particular tray is designed for use with and, also, on the function that tray is designed to perform.
- Processing trays may be configured for transporting IC devices between various manufacturing work stations where a specific production step, such as, for example, burn-in testing, may be conducted. Processing trays may also be configured for the storing and shipping of IC devices. Trays used for shipping IC devices are often custom designed for a specific customer—generally referred to as customer trays—depending on the needs of that customer. U.S. Pat. No. 5,492,223 to Boardman et al., U.S. Pat. No. 5,203,452 to Small et al., U.S. Pat. No. 5,927,503 to Nevill et al., U.S. Pat. No. 5,103,976 to Murphy, and U.S. Pat. No. 5,636,745 to Crisp et al. disclose processing trays that may be used for processing, handling, shipping, or storage, or a combination thereof, of IC devices. These conventional trays generally include a frame enclosing a planar, open lattice structure. The latticework forms a two-dimensional array of cells, each cell being adapted to receive an individual IC device.
- Another conventional processing tray design widely used within the semiconductor industry for handling IC devices during production is the JEDEC tray. These trays are designed and built in compliance with standards propagated by the Joint Electronic Device Engineering Counsel (JEDEC). Generally, a JEDEC tray includes a grid-like, open lattice structure that forms a planar, two-dimensional array of IC cells. Each IC cell is adapted to hold a single IC device. JEDEC trays are usually injection molded from plastic and vary in overall dimensions and grid size depending on the type of IC device the tray is designed to hold. JEDEC trays are stackable and also have surface features, such as locating and hold-down tabs, that facilitate manipulation of the trays by automatic processing and testing equipment.
- Another device used for handling IC devices is a burn-in board. A burn-in board is a type of IC device carrier specifically designed for holding a plurality of IC devices during burn-in and electrical testing. Burn-in is a procedure directed to the detection of IC devices likely to fail during the first few hours of operation, prior to the installation of those IC devices in higher-level packaging for eventual inclusion in electronic equipment. Burn-in testing of IC devices typically comprises the application of specified electrical biases and signals in a controlled temperature environment. The characteristics, such as voltage and frequency, of the specified electrical biases and signals may be configured so as to subject the IC devices to a test environment more severe than the electrical environment the IC devices will likely experience during normal operation. Other environmental variables, such as, for example, humidity, may also be controlled during burn-in testing.
- During a typical burn-in test, a plurality of IC devices is mounted on one or more burn-in boards, which are then placed in a test chamber having a controllable environment. Specified electrical biases and signals are applied to the IC devices while also subjecting the IC devices to thermal cycling, in which the temperature inside the test chamber is cycled between an elevated temperature—a temperature in excess of the ambient operating temperature the IC devices will likely experience during normal operation—and a below-ambient temperature—a temperature lower than the ambient operating temperature the IC device will likely experience during normal operation. Thermal cycling may include multiple temperature cycles, as well as extended testing at a specific temperature such as, for example, an elevated temperature. Applying electrical biases to the IC devices during thermal cycling accelerates the stress to which the IC devices are subjected to during burn-in. Therefore, marginal devices that might otherwise fail sometime after being placed in service are caused to fail during burn-in and are thus eliminated before shipment to customers or assembly into electronic equipment.
- Electrical testing is a procedure used to verify that IC devices function according to their minimum rated specifications and to classify IC devices based on their operating characteristics. In electrical testing, a more complete set of operating electrical signals is supplied to the IC devices to provide a thorough evaluation of their functions. After electrical testing, the IC devices may be sorted,—based on an IC device's electrical characteristics exhibited under test,—into categories, or “bins,” according to a predetermined set of performance characteristics.
- Conventional burn-in boards, which are commonly fabricated as printed circuit boards, exist in a wide variety of configurations. For example, U.S. Pat. No. 5,093,982 to Gussman, U.S. Pat. No. 5,329,093 to Okano, U.S. Pat. No. 4,684,182 to Gussman, and U.S. Pat. No. 5,247,248 to Fukunaga disclose burn-in boards for testing a plurality of IC devices. In addition, U.S. Pat. No. 5,517,125 to Posedel et al., U.S. Pat. No. 5,888,837 to Fillion et al., U.S. Pat. No. 5,367,253 to Wood et al., and U.S. Pat. No. 5,149,662 to Eichelberger disclose carrier trays specifically adapted for burn-in of a plurality of bare semiconductor dice. Also, U.S. Pat. No. 4,779,047 to Solstad et al. discloses a burn-in board configured for use with IC devices mounted on a carrier tape.
- During the manufacture of IC devices, considerable time, labor, and cost are expended in handling IC devices throughout the many phases of production. For example, a plurality of IC devices may be disposed on a first processing tray for storage during production and for transportation within the manufacturing facility. That plurality of IC devices may then be unloaded from the first processing tray and disposed on a burn-in board for burn-in and electrical testing. Upon completion of burn-in and electrical testing, the plurality of IC devices may be sorted according to performance characteristics observed during burn-in and electrical testing. The sorted IC devices may again be placed on processing trays for handling and transportation within the manufacturing facility.
- As evidence of the high costs to IC device manufacturers resulting from the handling of IC devices during production, much effort has been devoted to developing automated equipment specifically directed to the loading and unloading of IC devices for burn-in and electrical testing. For example, U.S. Pat. No. 5,307,011 to Tani, U.S. Pat. No. 4,660,282 to Pfaff, U.S. Pat. No. 5,267,395 to Jones, Jr. et al., U.S. Pat. No. 5,509,193 to Nuxoll, U.S. Pat. No. 5,842,272 to Nuxoll, and U.S. Pat. No. 4,817,273 to Lape et al. disclose apparatus for loading IC devices onto burn-in boards and for subsequent unloading of the IC devices onto processing trays or other transport media such as, for example, carrier tubes.
- It is a continuing goal of the semiconductor industry to decrease the costs of fabricating IC devices while maintaining, or even improving, device integrity, performance and operating capabilities. One approach to achieving a reduction in manufacturing costs for IC devices is to reduce the costs associated with handling the IC devices throughout the manufacturing facility and all phases of production. Therefore, a need exists in the semiconductor industry for methods and devices directed toward reducing the time and cost associated with handling IC devices during production. Specifically, a need exists in the semiconductor industry for an apparatus and method of performing burn-in and electrical testing in situ on processing trays, thereby eliminating the need to load and subsequently unload IC devices between processing trays and burn-in boards.
- Embodiments of the present invention include an in-tray burn-in board (BIB) for testing a plurality of IC devices disposed in a conventional processing tray. The in-tray BIB has a plurality of electrical contacts disposed on an interface surface that is configured to establish electrical contact with the leads or other terminals of IC devices carried by a processing tray. The electrical contacts may be spring loaded to bias the electrical contacts against the IC device leads. To facilitate alignment between the in-tray BIB and a processing tray, and electrical communication between the electrical contacts and the IC device leads, the in-tray BIB may also include one or more alignment surfaces, or one or more latching mechanisms.
- Internal conductors carried by the in-tray BIB establish electrical communication between the electrical contacts and an electrical conduit. The electrical conduit is configured for connection to a tester to establish electrical communication between the tester and the IC devices. The tester, which may be used in conjunction with an environmental chamber, is then used to perform burn-in and other electrical testing of the IC devices disposed in a processing tray.
- One or more in-tray BIBs according to the present invention may be associated with a test system, which may be automated. In one embodiment, the test system includes a displacement mechanism attached to an in-tray BIB or, alternatively, is associated with one or more processing trays, configured to move the in-tray BIB and at least one processing tray into mutual engagement. The test system may include a tray source configured to deliver processing trays and accompanying IC devices to the test system, and may also include a sorting apparatus for sorting and binning tested and characterized IC devices. In one embodiment, the test system includes a test frame configured to receive a plurality of test assemblies, each test assembly including an in-tray BIB in mutual engagement with at least one processing tray and the IC devices disposed therein. The test system may further include an environmental chamber configured to receive an in-tray BIB in mutual engagement with at least one processing tray or, alternatively, configured to receive a plurality of test assemblies disposed in the test frame.
- While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the features and advantages of this invention can be more readily ascertained from the following detailed description of the invention when read in conjunction with the accompanying drawings, in which:
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FIG. 1 is a perspective view of an in-tray burn-in board according to this invention and a conventional processing tray; -
FIG. 2 is a plan view of a conventional processing tray having a plurality of IC devices located thereon; -
FIG. 3 is a plan view of the in-tray burn-in board ofFIG. 1 ; -
FIG. 4 is a schematic view of an IC device testing system having an in-tray burn-in board according to this invention; -
FIG. 5 is a schematic view of an IC device testing system having an in-tray burn-in board according to this invention; -
FIG. 6 is a plan view of a tray source and an in-tray burn-in board according to this invention; -
FIG. 7 is a plan view of a tray source and an in-tray burn-in board according to this invention; and -
FIG. 8 is a schematic view of an IC device test system having a test frame and a plurality of in-tray burn-in boards according to this invention. -
FIGS. 1 through 8 contain many equivalent elements, and these equivalent elements will retain the same numerical designation in all figures. -
FIG. 1 shows an exemplary embodiment of an in-tray burn-in board (BIB) 10 according to this invention. The in-tray BIB 10 is associated with atray source 200 configured to deliver a plurality ofconventional processing trays 100 to the in-tray BIB 10. The in-tray BIB 10 has at least oneinterface surface 12 for establishing electrical communication with a plurality ofIC devices 90 supported in aprocessing tray 100. The in-tray BIB 10 may also be connected to adisplacement mechanism 300, which is configured to move the in-tray BIB 10 relative to thetray source 200, such that theinterface surface 12 of the in-tray BIB 10 may engage theIC devices 90 disposed in aprocessing tray 100. Further, the in-tray BIB 10 may also include one ormore latching mechanisms 20, and one or more alignment surfaces 30, disposed thereon. These and other features of the in-tray BIB 10 according to the present invention will be described hereinafter in greater detail. - Referring again to
FIG. 1 , eachprocessing tray 100 delivered bytray source 200 generally includes aframe 112 enclosing anopen lattice structure 114. Theopen lattice structure 114 defines a plurality ofcells 116, eachcell 116 being configured to receive an individual integrated circuit (IC)device 90. Thus, theprocessing tray 100 is capable of respectively receiving a plurality ofIC devices 90 within the plurality ofcells 116. Aprocessing tray 100 may also have a plurality oftabs 118 extending from theframe 112. Thetabs 118 provide additional surfaces for manipulation by automatic processing equipment to facilitate handling of theprocessing tray 100 and to ensure proper rotational alignment of theprocessing tray 100 and of theIC devices 90 and pin-outs thereof. Additionally, aprocessing tray 100 may have one or more locating features 120 disposed thereon for mating with acorresponding alignment surface 30 on the in-tray BIB 10. Aprocessing tray 100 may be configured as any suitable tray configured to receive IC devices as is known in the art such as, by way of example only, trays designed in accordance with JEDEC standards. -
FIG. 2 shows aprocessing tray 100 having a plurality ofIC devices 90 received within itscells 116. Extending from eachIC device 90 is a plurality of leads orterminals 92. TheIC devices 90 may be configured as TSOP, SOJ, or othersimilar IC packages IC devices 90 may extend towards or away from theprocessing tray 100. For example, the IC packages 90 a are positioned within theprocessing tray 100 having theirleads 92 a extending downwardly, towards the processingtray 100. Alternatively, the IC packages 90 b are received within theprocessing tray 100 with theirleads 92 b extending upwardly, away from theprocessing tray 100. Theprocessing tray 100 may also be configured, for example, to receive a plurality of BGA packages 90 c bearing an array ofball contact elements 92 c. The BGA packages 90 c may be conventional packages, chip-scale packages, or bare semiconductor dice having an array of contact or bond pads, which may haveball contact elements 92 c attached thereto. Any other type of IC device as known in the art may be received within theprocessing tray 100. - Referring to
FIG. 3 , an in-tray BIB 10 is shown with itsinterface surface 12 facing upwards. Theinterface surface 12 has a plurality ofelectrical contacts 40. Theelectrical contacts 40 may be arranged in a pattern, which will be referred to herein as afootprint 45, corresponding to the number, pitch (spacing), and arrangement of theleads 92 extending from theIC devices 90. The number offootprints 45 disposed on the in-tray BIB 10 may equal the number ofcells 116 on aprocessing tray 100. Alternatively, the number offootprints 45 may be greater than the number ofcells 116 of aprocessing tray 100 such that the in-tray BIB 10 may be adapted for use with different sizes and shapes of processingtrays 100, or for simultaneous use with more than oneprocessing tray 100. - The in-
tray BIB 10 has anelectrical conduit 80 extending therefrom for establishing electrical communication between theelectrical contacts 40 and a tester (not shown inFIG. 3 ). Theelectrical conduit 80, depicted as a ribbon cable, may be any suitable cable, connector, or wiring as is known in the art. Theelectrical conduit 80 is in electrical communication with the plurality ofelectrical contacts 40 via internal conductors (not shown) on the in-tray BIB 10. The in-tray BIB 10 may, for example, be fabricated from conventional printed circuit board materials as are known in the art, in which case the internal conductors may be conductive traces formed, for example, on the surface of the printed circuit board opposite that on whichelectrical contacts 40 are carried. Alternatively, the in-tray BIB 10 may be manufactured as a multi-layer substrate and the internal conductors may be conductive traces formed on various layers of the multi-layer substrate as known in the art. Thus, the in-tray BIB 10 may be constructed using any suitable methods and materials as known in the art. - The
electrical contacts 40 may comprise contact pads formed on theinterface surface 12 or, alternatively, theelectrical contacts 40 may comprise pins attached to the in-tray BIB 10 and extending therefrom. In a further embodiment, theelectrical contacts 40 may be spring loaded pins that are biased away from the in-tray BIB 10 and towards theleads 92 of theIC devices 90 carried in aprocessing tray 100. During engagement between theinterface surface 12 and a plurality ofIC devices 90 supported within aprocessing tray 100, biasing theelectrical contacts 40 towards theleads 92 may compensate for non-planarities of theinterface surface 12, or for non-planarities of theIC devices 90, leads 92, orprocessing tray 100. - In another embodiment, a plurality of
electrical contacts 40 comprising afootprint 45 is formed as a stand-alone socket 48. A plurality of stand-alone sockets 48 is then attached to the in-tray BIB 10 and is in electrical communication with theelectrical conduit 80.Sockets 48 may be permanently secured to the in-tray BIB 10 or, alternatively, thesockets 48 may be removably secured to the in-tray BIB 10 so thatdifferent sockets 48 may be employed for engagement with differently configuredIC devices 90. Further, the use of removable stand-alone sockets 48 facilitates replacement of worn or damagedelectrical contacts 40. Theelectrical contacts 40 may be any other suitable electrical contact as is known in the art. - Referring to
FIG. 4 andFIG. 5 , a burn-in andelectrical testing system 5 that incorporates an in-tray BIB 10 according to the present invention is shown. As shown inFIG. 4 , the in-tray BIB 10 is connected to adisplacement mechanism 300. Alternatively, the processing tray ortrays 100 may be associated with thedisplacement mechanism 300, or, in a further embodiment, both the in-tray BIB 10 and the processing tray ortrays 100 are each associated with adisplacement mechanism 300. Atray source 200, depicted inFIG. 4 , by way of example only, as a conveyor, is disposed adjacent the in-tray BIB 10 and is configured to sequentially deliver one ormore processing trays 100 to the in-tray BIB 10. The in-tray BIB 10 and itselectrical contacts 40 are in electrical communication with atester 400 viaelectrical conduit 80. Thetest system 5 may also include anenvironmental chamber 500 capable of controlling one or more desired environmental characteristics during testing such as, for example, temperature. -
Testing IC devices 90 in situ on processingtrays 100 with thetest system 5 and in-tray BIB 10 may be performed according to the following test sequence. Referring again toFIG. 4 , a plurality ofIC devices 90 is disposed in one ormore processing trays 100. Thetray source 200 delivers at least oneprocessing tray 100 adjacent the in-tray BIB 10. As shown inFIG. 6 , thetray source 200, which is shown as a rotary table, positions theprocessing tray 100 into atarget zone 15. When positioned in thetarget zone 15, theprocessing tray 100 is at least substantially aligned with the in-tray BIB 10 such that, as thedisplacement mechanism 300 moves the in-tray BIB 10 andprocessing tray 100 into mutual engagement, theelectrical contacts 40 of theinterface surface 12 are aligned with theleads 92 of theIC devices 90. Those of ordinary skill in the art will appreciate that thedisplacement mechanism 300 may be configured to move the in-tray BIB 10, the processing tray ortrays 100, or both the in-tray BIB 10 and processing tray ortrays 100, in order to create mutual engagement therebetween. In a further embodiment, as shown inFIG. 7 , the tray source 200 (shown as a conveyor) is configured to simultaneously deliver more than oneprocessing tray 100 into atarget zone 15. In the embodiment ofFIG. 7 , the in-tray BIB 10 has aninterface surface 12 adapted to simultaneously engage a plurality ofprocessing trays 100 and establish electrical communication with theIC devices 90 disposed thereon. - Once the
tray source 200 has delivered one ormore processing trays 100 into thetarget zone 15 adjacent the in-tray BIB 10, thedisplacement mechanism 300 moves the in-tray BIB 10 into engagement with the processing tray 100 (or into engagement with a plurality of processing trays 100). Upon engagement with theprocessing tray 100, theelectrical contacts 40 on theinterface surface 12 of the in-tray BIB 10 contact, and form electrical communication with, theleads 92 of theIC devices 90. As noted previously, theelectrical contacts 40 may be spring-biased towards the leads 92. TheIC devices 90 may then be subjected to burn-in and other electrical testing bytester 400 and, optionally,environmental chamber 500. Once testing of theIC devices 90 disposed in one ormore processing trays 100 located in thetarget zone 15 has been completed, thedisplacement mechanism 300 will disengage the in-tray BIB 10 from theIC devices 90 and processing tray ortrays 100. Thetray source 200 will then deliver one or moreother processing trays 100 into thetarget zone 15 and the test sequence may be repeated. - To facilitate alignment between the in-
tray BIB 10 and one ormore processing trays 100, as well as alignment between theelectrical contacts 40 and theleads 92 of a plurality ofIC devices 90, the in-tray BIB 10 may have one or more alignment surfaces. As shown inFIG. 1 , analignment surface 30 may comprise one or more register pins, which may have a circumferential surface tapered along their longitudinal axes, configured to engage one or more mating holes or other locating features 120 on aprocessing tray 100. Alternatively, as shown inFIG. 3 , aflange 31 may provide one or more alignment surfaces. Theflange 31 is configured to form a mating contact fit with at least a portion of theframe 112 of aprocessing tray 100. Theflange 31 may extend about only a portion of the perimeter of the in-tray BIB 10 and may further include aninner surface 35 that is tapered. A tapered alignment surface may facilitate alignment between the in-tray BIB 10 and aprocessing tray 100 by functioning as a cam surface that, as the in-tray BIB 10 andprocessing tray 100 engage one another, preferentially moves theprocessing tray 100 into a predetermined, aligned position with respect to the in-tray BIB 10. In a further embodiment, as shown inFIG. 3 , alignment surfaces may be provided by one ormore brackets 32 havingslots 33 configured to form a mating contact fit with a tab ortabs 118 extending from aprocessing tray 100. - To facilitate electrical contact between the
electrical contacts 40 and theleads 92 of a plurality ofIC devices 90, the in-tray BIB 10 may also include one ormore latching mechanisms 20 as shown inFIGS. 1 and 4 . Thelatching mechanism 20 is configured to grasp aprocessing tray 100 and secure theprocessing tray 100 in an abutting relationship with the in-tray BIB 10. Thelatching mechanism 20 may be amechanical clamping structure 20 a as shown inFIG. 4 . The clampingstructure 20 a may be adapted to grasp one ormore tabs 118, or any other surface, of aprocessing tray 100. Alternatively, avacuum head 20 b may be associated with the in-tray BIB 10. Referring toFIG. 4 , one ormore vacuum ports 28 may be disposed on theinterface surface 12 of the in-tray BIB 10. Thevacuum ports 28 andvacuum head 20 b are influid communication 26 with avacuum source 25. Upon engagement with aprocessing tray 100, thevacuum ports 28 in the in-tray BIB 10 come into contact with one or more surfaces of theprocessing tray 100 to produce a negative pressure area between the in-tray BIB 10 andprocessing tray 100, thereby forming a vacuum lock between theprocessing tray 100 and in-tray BIB 10. Any other suitable device as known in the art that can be adapted to grasp aprocessing tray 100 may function as alatching mechanism 20. - In another embodiment shown in
FIG. 5 , thetest system 5 may also include asorting apparatus 600. Thesorting apparatus 600 is configured to receive a plurality of tested and characterizedIC devices 90 and to sort theIC devices 90 into a plurality of categories, or bins, depending on a particular IC device's electrical characteristics exhibited under test. Thesorting apparatus 600 may include a pick-and-place mechanism 610 adapted to removeIC devices 90 from theprocessing trays 100. The pick-and-place mechanism 610 may transport theIC devices 90 toother processing trays 100, to customer trays for shipment, or to any other desired transport or storage medium. Further, thesorting apparatus 600 may be in electrical communication with thetester 400 via aconduit 82, theconduit 82 being any suitable cable or wiring as known in the art. Thetester 400 may then provide thesorting apparatus 600 with data relating to the electrical characteristics of theIC device 90 located in eachcell 116 on aprocessing tray 100, such that eachIC device 90 may be transferred to the proper category or bin. - In another embodiment shown in
FIG. 5 , thetest system 5 may also include asystem controller 700. Thesystem controller 700 may be in electrical communication with thetray source 200,displacement mechanism 300,tester 400,environmental chamber 500, and sortingapparatus 600 viaelectrical conduits 710. Theconduits 710 may comprise any suitable cable or wiring as known in the art. Thesystem controller 700 may be configured to control the operation of thetest system 5 in order to perform an automated burn-in and test sequence, as well as subsequent sorting and binning operations. Thesystem controller 700 may also be configured to control operation of the latchingmechanisms 20, such as the clampingstructure 20 a andvacuum head 20 b. - Shown in
FIG. 8 is a further alternative embodiment of the present invention. Referring toFIG. 8 , a plurality oftest assemblies 50 is disposed in atest frame 800. Eachtest assembly 50 is comprised of at least oneprocessing tray 100, and a plurality ofIC devices 90 disposed therein, coupled to an in-tray BIB 10. One or morelatching mechanisms 20 secure the processing tray ortrays 100 to the in-tray BIB 10, such that the plurality ofelectrical contacts 40 on theinterface surface 12 of the in-tray BIB 10 is electrically coupled to theleads 92 extending from theIC devices 90 disposed in the processing tray or trays 100 (not shown). The latchingmechanisms 20 may be integral to the in-tray BIB 10, such asresilient tabs 20 c attached to the in-tray BIB 10 and configured to grasp a surface of aprocessing tray 100, or, alternatively, the latchingmechanisms 20 may be stand-alone, such asclamps 20 d, as is depicted inFIG. 8 , or any other suitable latching devices. It should be understood that eachtest assembly 50 may comprisemultiple processing trays 100 interfacing with a single in-tray BIB 10. - The
test frame 800 comprises aframe structure 810 that defines a plurality oftest bays 850, eachtest bay 850 being configured to receive atest assembly 50 and to establish electrical communication therewith. Eachtest bay 850 includes a support structure orshelf 820 extending from theframe structure 810 and configured to support atest assembly 50. Eachtest bay 850 also includes aconnector 830 configured to electrically connect to theelectrical conduit 80 extending from an in-tray BIB 10. By way of example only, theelectrical conduit 80 may be a male socket connector and theconnector 830 may be a mating female socket connector. Via theelectrical conduit 80, theconnector 830, and anelectrical conduit 410, eachtest assembly 50 received in atest bay 850 is electrically connected to atester 400. Theelectrical conduit 410 may comprise any suitable cable or wiring as known in the art. Thus, a plurality ofprocessing trays 100 carryingIC devices 90 may each be secured to an in-tray BIB 10 to form atest assembly 50, and a plurality oftest assemblies 50 may be simultaneously subjected to burn-in and other electrical testing in thetest frame 800. - As shown in
FIG. 8 , thetest frame 800 may be incorporated into a test system 7. The test system 7 may include, by way of example only, atray source 200, atester 400, aBIB source 900, and anassembly apparatus 1000. Theassembly apparatus 1000 is configured to receiveprocessing trays 100 from thetray source 200 and to receive in-tray BIBs 10 from theBIB source 900. Theassembly apparatus 1000 is further configured to secure one ormore processing trays 100 and an in-tray BIB 10 in mutual engagement to form atest assembly 50 and to transfer thetest assembly 50 to atest bay 850 on thetest frame 800 for testing. Theassembly apparatus 1000 may be any suitable device, or combination of devices, as known in the art and may, by way of example only, include robotic arms and other automated manipulating devices, tracks, conveyors, and turntables, or any suitable combination thereof. It should be understood that atest assembly 50 may be manually assembled and inserted into atest bay 850 on thetest frame 800. TheBIB source 900 may be any suitable device adapted to deliver in-tray BIBs 10 to theassembly apparatus 1000. For example, theBIB source 900 may include amagazine 910, as depicted inFIG. 8 , and anunloading mechanism 920, such as a robotic arm. - The test system 7 may further include an
environmental chamber 500 that is sized and configured to receive atest frame 800 and accompanyingtest assemblies 50, and theIC devices 90 disposed therein. The test system 7 may also include asystem controller 700 electrically couples, viaelectrical conduits 710, which may be any suitable cable or wiring as known in the art, to thetray source 200,tester 400,environmental chamber 500,BIB source 900, andassembly apparatus 1000, and configured to control the operation of these systems. As was indicated with respect to thetest system 5 shown inFIGS. 5 and 6 , the test system 7 may also include sorting apparatus (not shown inFIG. 8 ) for sorting and binning tested and characterizedIC devices 90. Those of ordinary skill in the art will appreciate that the test system 7 may comprise a single integrated test system. - Using the test system 7 in conjunction with the in-
tray BIB 10 according to the present invention, a plurality ofIC devices 90 may be tested in situ on processingtrays 100 as will now be described. A plurality ofIC devices 90 is disposed in one ormore processing trays 100. Thetray source 200 delivers one ormore processing trays 100 and accompanyingIC devices 90 to theassembly apparatus 1000, and theBIB source 900 delivers an in-tray BIB 10 to theassembly apparatus 1000. Theassembly apparatus 1000 aligns at least oneprocessing tray 100 with the in-tray BIB 10 and secures the processing tray ortrays 100 into mutual engagement with the in-tray BIB 10 to form atest assembly 50. Latchingmechanisms 20 secure the processing tray ortrays 100 and in-tray BIB 10 to one another. Alignment surfaces 30 on the in-tray BIB 10 and corresponding locating features 120 on theprocessing trays 100 may facilitate alignment between the processing tray ortrays 100 and the in-tray BIB 10. Theassembly apparatus 1000 transfers eachtest assembly 50 to atest bay 850 on thetest frame 800, such that theelectrical conduit 80 of each in-tray BIB 10 is electrically coupled to arespective connector 830 on thetest frame 800. When a desired number oftest assemblies 50 is loaded into thetest frame 800, theIC devices 90 disposed in theprocessing trays 100 may be subjected to operating electrical signals and biases by thetester 400. - For burn-in testing, the
entire test frame 800, and accompanyingtest assemblies 50, may be placed in anenvironmental chamber 500. Thetest frame 800 may be manually placed in theenvironmental chamber 500 or, alternatively, automated handling equipment (not shown) may be used to place atest frame 800 in theenvironmental chamber 500. Also, asystem controller 700 may control operation of thetray source 200,tester 400,environmental chamber 500,BIB source 900, andassembly apparatus 1000 during burn-in and electrical testing. Once testing of theIC devices 90 disposed in thetest frame 800 is completed, thetest assemblies 50 are unloaded andother test assemblies 50, andenclosed IC devices 90, may be loaded into thetest frame 800 and tested. - Those of ordinary skill in the art will appreciate the advantages of the in-
tray BIB 10 herein described. The in-tray BIB 10 allows a plurality ofIC devices 90 disposed in one ormore processing trays 100 to be subjected to burn-in and other electrical testing without the need to transfer theIC devices 90 from processingtrays 100 to separate burn-in boards and, in some instances, without the subsequent step of unloading theIC devices 90 from the separate burn-in boards for transfer to other transport medium. Thus, a significant reduction in manufacturing resources—in terms of both time and cost—associated with handling IC devices is achieved using the in-tray BIB 10 of the present invention. - The in-
tray BIB 10 can be adapted for use with any conventional processing tray design and, further, can be configured for use with any conventional type of IC package, or with bare semiconductor dice. Integrity of the electrical contact between the IC device leads 92 and the in-tray BIB 10 may be maintained by the addition of one or more alignment surfaces 30, one ormore latching mechanisms 20, the use of spring-biasedelectrical contacts 40, or a combination thereof, to the in-tray BIB 10. - The in-tray-
BIB 10 may also be incorporated into atest system 5 that includes atester 400, and that may further include anenvironmental chamber 500, or asorting apparatus 600, in electrical communication with thetester 400. In addition, thetest system 5 may be automated by the addition of asystem controller 700. Automating thetest system 5 with asystem controller 700, in conjunction with in situ testing ofIC devices 90 on processingtrays 100 using the in-tray BIB 10 according to the present invention, allows a large number ofIC devices 90 disposed in a plurality ofprocessing trays 100 to be subjected to burn-in and other electrical testing with minimal intervention by a test operator and, additionally, with a significant reduction in manufacturing resources dedicated to handling theIC devices 90. In a further embodiment, a plurality of in-tray BIBs 10 is incorporated into a test system 7 that includes atest frame 800. A plurality oftest assemblies 50, each comprising at least oneprocessing tray 100 and accompanyingIC devices 90 in mutual engagement with an in-tray BIB 10, may be placed in thetest frame 800 for burn-in and other electrical testing. Thus, a large number ofIC devices 90 may be simultaneously subjected to burn-in and other electrical testing using thetest frame 800 in conjunction with a plurality of in-tray BIBs 10 according to the present invention. - The foregoing detailed description and accompanying drawings are only illustrative and not restrictive. They have been provided primarily for clearness of understanding and no unnecessary limitations are to be understood therefrom. Numerous modifications and alternative arrangements may be devised by those skilled in the art without departing from the spirit of the present invention and the scope of the appended claims.
Claims (40)
1. A system for testing integrated circuit devices disposed in processing trays, comprising:
a burn-in board having a plurality of electrical contacts located and configured for establishing direct electrical contact with a plurality of said integrated circuit devices disposed in at least one of said processing trays;
a tray source configured to deliver processing trays adjacent said burn-in board;
a displacement mechanism configured to move said burn-in board and said at least one processing tray into mutual engagement; and
a tester in electrical communication with said plurality of electrical contacts.
2. The system of claim 1 , further comprising an apparatus for sorting said plurality of integrated circuit devices responsive to testing thereof.
3. The system of claim 1 , further comprising a system controller configured for controlling the operation of said tray source, said displacement mechanism, and said tester.
4. The system of claim 1 , further comprising an environmental chamber sized and configured to receive said burn-in board and said at least one processing tray in engagement therewith during testing.
5. A system for testing integrated circuit devices disposed in processing trays, comprising:
a burn-in board having an interface surface;
a tray source configured to deliver at least two of said processing trays adjacent said burn-in board;
a plurality of electrical contacts disposed on said interface surface located and configured for establishing direct electrical contact with integrated circuit devices disposed in one of said at least two processing trays;
at least one other plurality of electrical contacts disposed on said interface surface located and configured for establishing direct electrical contact with integrated circuit devices disposed in another of said at least two processing trays;
a displacement mechanism configured to move said burn-in board and said at least two of said processing trays into mutual engagement; and
a tester electrically coupled to said plurality of electrical contacts and to said at least one other plurality of electrical contacts.
6. The system of claim 5 , further comprising an apparatus for sorting said integrated circuit devices responsive to testing thereof.
7. The system of claim 5 , further comprising a system controller configured for controlling the operation of said tray source, said displacement mechanism, and said tester.
8. The system of claim 5 , further comprising an environmental chamber sized and configured to receive said burn-in board and said at least two of said processing trays in engagement therewith during testing.
9. A test system for burn-in and electrical testing of integrated circuit devices disposed in processing trays, comprising:
a burn-in board including an interface surface and an electrical conduit;
a tray source configured to deliver at least one processing tray adjacent said burn-in board;
at least one plurality of electrical contacts disposed on said interface surface located and configured to establish direct electrical contact with integrated circuit devices disposed in said at least one processing tray, said at least one plurality of electrical contacts electrically coupled to said electrical conduit;
a displacement mechanism configured to move said burn-in board and said at least one processing tray into mutual engagement;
a tester in electrical communication with said electrical conduit; and
a system controller operably coupled to said tray source, said displacement mechanism, and said tester, and configured to control operation thereof.
10. The test system of claim 9 , further comprising:
an environmental chamber sized and configured to receive said burn-in board and said at least one processing tray in engagement therewith during testing;
wherein said system controller is operably coupled to said environmental chamber and configured to control operation thereof.
11. The test system of claim 9 , further comprising:
a sorting apparatus configured for sorting said integrated circuit devices responsive to testing thereof;
wherein said system controller is operably coupled to said sorting apparatus and configured to control operation thereof.
12. The test system of claim 9 , further comprising:
at least one latching mechanism associated with said burn-in board and configured to attach said at least one processing tray to said burn-in board;
wherein said system controller is operably coupled to said at least one latching mechanism and is configured to control operation thereof.
13. A method of testing integrated circuit devices, comprising:
disposing said integrated circuit devices in a plurality of processing trays;
delivering at least one processing tray of said plurality of processing trays adjacent a burn-in board;
moving said burn-in board and said at least one processing tray into mutual engagement;
establishing electrical contact between said burn-in board and integrated circuit devices disposed in said at least one processing tray; and
measuring at least one electrical characteristic of said integrated circuit devices disposed in said at least one processing tray.
14. The method of claim 13 , further comprising:
moving said burn-in board and said at least one processing tray away from one another to terminate said electrical contact between said burn-in board and said integrated circuit devices; and
delivering at least one other processing tray of said plurality of processing trays adjacent said burn-in board.
15. The method of claim 13 , further comprising subjecting said integrated circuit devices disposed in said at least one processing tray to thermal cycling while measuring said at least one electrical characteristic.
16. The method of claim 13 , further comprising sorting said integrated circuit devices disposed in said at least one processing tray according to said at least one electrical characteristic exhibited by each of said integrated circuit devices.
17. A method of performing burn-in and electrical testing of integrated circuit devices disposed in processing trays, comprising:
delivering at least one of said processing trays into a target zone proximate a burn-in board, said at least one processing tray having a plurality of said integrated circuit devices disposed thereon;
moving said burn-in board and said at least one processing tray into mutual engagement;
establishing electrical contact between said burn-in board and said plurality of said integrated circuit devices; and
measuring at least one electrical characteristic of said plurality of said integrated circuit devices.
18. The method of claim 17 , further comprising:
moving said burn-in board and said at least one processing tray away from one another to terminate said electrical contact;
moving said at least one processing tray out of said target zone; and
delivering at least one other of said processing trays having a plurality of said integrated circuit devices disposed thereon into said target zone.
19. The method of claim 17 , further comprising subjecting said plurality of said integrated circuit devices disposed in said at least one processing tray to thermal cycling while measuring said at least one electrical characteristic.
20. The method of claim 17 , further comprising:
sorting said plurality of said integrated circuit devices disposed in said at least one processing tray into categories according to said at least one electrical characteristic exhibited by each integrated circuit device of said plurality of said integrated circuit devices; and
transferring said plurality of said integrated circuit devices to other transport media according to said categories.
21. The method of claim 17 , further comprising:
providing a system controller; and
controlling said acts of delivering at least one of said processing trays into a target zone proximate a burn-in board,
moving said burn-in board and said at least one processing tray into mutual engagement, and
measuring at least one electrical characteristic of said plurality of said integrated circuit devices, with said system controller.
22. The method of claim 19 , further comprising:
providing a system controller;
controlling said acts of delivering at least one of said processing trays into a target zone proximate a burn-in board;
moving said burn-in board and said at least one processing tray into mutual engagement;
measuring at least one electrical characteristic of said plurality of said integrated circuit devices; and
subjecting said plurality of said integrated circuit devices disposed in said at least one processing tray to thermal cycling, with said system controller.
23. The method of claim 20 , further comprising:
providing a system controller;
controlling said acts of delivering at least one of said processing trays into a target zone proximate a burn-in board;
moving said burn-in board and said at least one processing tray into mutual engagement;
measuring at least one electrical characteristic of said plurality of said integrated circuit devices;
sorting said plurality of said integrated circuit devices; and
transferring said plurality of said integrated circuit devices, with said system controller.
24. A system for testing integrated circuit devices disposed in processing trays, comprising:
at least two test assemblies, each test assembly of said at least two test assemblies including a burn-in board in mutual engagement with at least one of said processing trays, said burn-in board including a plurality of electrical contacts located and configured for establishing direct electrical contact with a plurality of said integrated circuit devices disposed in said at least one processing tray;
a test frame including at least two test bays, each test bay of said at least two test bays configured to receive and support one of said at least two test assemblies and to establish electrical contact therewith; and
a tester in electrical communication with said at least two test assemblies.
25. The test system of claim 24 , further comprising at least one latching mechanism disposed in said each test assembly and configured to secure said burn-in board and said at least one processing tray in said mutual engagement.
26. The test system of claim 24 , further comprising:
an assembly apparatus configured to effect said mutual engagement between said burn-in board and said at least one processing tray to form said each test assembly, and further configured to move said each test assembly to one of said at least two test bays on said test frame;
a tray source configured to deliver said processing trays to said assembly apparatus; and
a burn-in board source configured to deliver said burn-in boards to said assembly apparatus.
27. The test system of claim 26 , further comprising a system controller operably coupled to said tester, said assembly apparatus, said tray source, and said burn-in board source, and configured to control operation thereof.
28. The test system of claim 24 , further comprising an environmental chamber sized and configured to receive said test frame.
29. A system for testing integrated circuit devices disposed in processing trays, comprising:
a plurality of burn-in boards, each burn-in board of said plurality of burn-in boards including an interface surface and a plurality of electrical contacts disposed on said interface surface, said plurality of electrical contacts located and configured for establishing direct electrical contact with integrated circuit devices disposed in at least one of said processing trays, said each burn-in board further including an electrical conduit electrically connected to said plurality of electrical contacts;
an assembly apparatus configured to secure one of said plurality of burn-in boards and at least one of said processing trays in mutual engagement to form a test assembly;
a test frame configured to receive a plurality of said test assemblies, said test frame including at least one shelf configured to support at least one of said test assemblies and further including at least one connector configured for electrical connection to at least one of said electrical conduits; and
a tester electrically coupled to said at least one connector on said test frame.
30. The test system of claim 29 , further comprising:
at least one other plurality of electrical contacts disposed on said interface surface of said each burn-in board, said at least one other plurality of electrical contacts located and configured for establishing direct electrical contact with integrated circuit devices disposed in at least one other of said processing trays, said electrical conduit on said each burn-in board electrically connected to said at least one other plurality of electrical contacts;
wherein said assembly apparatus is configured to secure said each burn-in board, said at least one processing tray, and said at least one other processing tray in mutual engagement to form one of said test assemblies.
31. The test system of claim 29 , further comprising:
a tray source configured to deliver said processing trays to said assembly apparatus;
a burn-in board source configured to deliver said plurality of burn-in boards to said assembly apparatus; and
an environmental chamber sized and configured to receive said test frame and said plurality of said test assemblies received in said test frame.
32. The test system of claim 31 , further comprising a system controller operably coupled to said assembly apparatus, said tester, said tray source, said burn-in board source, and said environmental chamber, and configured to control operation thereof.
33. A test assembly for testing integrated circuit devices disposed in processing trays, comprising:
a burn-in board having an interface surface;
a plurality of electrical contacts disposed on said interface surface located and configured for establishing direct electrical contact with a plurality of integrated circuit devices disposed in at least one of said processing trays;
at least one latching mechanism securing said at least one processing tray and said burn-in board in mutual engagement, thereby establishing direct electrical contact between said plurality of electrical contacts and said plurality of integrated circuit devices; and
an electrical conduit electrically connected to said plurality of electrical contacts and configured for electrically coupling said plurality of electrical contacts to a test frame.
34. The test assembly of claim 33 , further comprising at least one alignment surface disposed on said burn-in board configured, by contact with said at least one processing tray, to align said at least one processing tray with respect to said burn-in board.
35. A test assembly for testing a plurality of integrated circuit devices disposed in a plurality of cells arranged in a pattern on a processing tray, comprising:
a burn-in board including an interface surface and further including a plurality of footprints disposed on said interface surface arranged substantially congruent with said pattern, each footprint of said plurality of footprints comprising a plurality of electrical contacts located and configured for establishing direct electrical contact with a plurality of leads extending from one integrated circuit device of said plurality of integrated circuit devices;
at least one latching mechanism securing said burn-in board and said processing tray in mutual engagement, thereby aligning each integrated circuit device of said plurality of integrated circuit devices disposed in said processing tray with one footprint of said plurality of footprints; and
an electrical conduit electrically connected to said plurality of footprints and configured for electrically coupling said each footprint to a test frame.
36. A method of testing integrated circuit devices disposed in processing trays, comprising:
securing each of said processing trays in mutual engagement with a burn-in board to form a plurality of test assemblies;
establishing electrical contact between said burn-in board and a plurality of integrated circuit devices disposed in said each processing tray;
disposing each test assembly of said plurality of test assemblies in an individual test bay of a test frame and supporting said each test assembly therein;
electrically coupling said each test assembly to a test instrument; and
measuring at least one electrical characteristic of said integrated circuit devices.
37. The method of claim 36 , further comprising subjecting said integrated circuit devices disposed in said plurality of test assemblies to thermal cycling while measuring said at least one electrical characteristic.
38. The method of claim 36 , further comprising aligning said each processing tray of said plurality of processing trays with respect to said burn-in board.
39. The method of claim 36 , further comprising:
providing a system controller;
controlling said acts of securing said each processing tray in mutual engagement with a burn-in board;
disposing said each test assembly in an individual test bay of said test frame; and
measuring at least one electrical characteristic of said integrated circuit devices, with said system controller.
40. The method of claim 37 , further comprising:
providing a system controller;
controlling said acts of securing said each processing tray in mutual engagement with a burn-in board,
disposing said each test assembly in an individual test bay of said test frame;
subjecting said integrated circuit devices disposed in said plurality of test assemblies to thermal cycling; and
measuring at least one electrical characteristic of said integrated circuit devices, with said system controller.
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US20090030792A1 (en) * | 2007-07-24 | 2009-01-29 | Amit Khivesara | Content recommendation service |
US20160033584A1 (en) * | 2014-07-30 | 2016-02-04 | Semiconductor Components Industries, Llc | Method of forming a sequencing system and structure therefor |
US9913355B2 (en) * | 2014-07-30 | 2018-03-06 | Semiconductor Components Industries, Llc | Method of forming a sequencing system and structure therefor |
Also Published As
Publication number | Publication date |
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US6927596B2 (en) | 2005-08-09 |
US7365558B2 (en) | 2008-04-29 |
US20050168237A1 (en) | 2005-08-04 |
US6476629B1 (en) | 2002-11-05 |
US20060208757A1 (en) | 2006-09-21 |
US7095242B2 (en) | 2006-08-22 |
US20050012517A1 (en) | 2005-01-20 |
US6815967B2 (en) | 2004-11-09 |
US20020149389A1 (en) | 2002-10-17 |
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