|Publication number||US20060213956 A1|
|Application number||US 11/384,609|
|Publication date||Sep 28, 2006|
|Filing date||Mar 20, 2006|
|Priority date||Mar 23, 2005|
|Also published as||CN1838394A, DE102006011352A1|
|Publication number||11384609, 384609, US 2006/0213956 A1, US 2006/213956 A1, US 20060213956 A1, US 20060213956A1, US 2006213956 A1, US 2006213956A1, US-A1-20060213956, US-A1-2006213956, US2006/0213956A1, US2006/213956A1, US20060213956 A1, US20060213956A1, US2006213956 A1, US2006213956A1|
|Original Assignee||Unaxis International Trading Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (4), Classifications (22), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Applicant hereby claims foreign priority under 35 U.S.C § 119 from Swiss Application No. 538/05 filed Mar. 23, 2005, the disclosure of which is herein incorporated by reference.
The invention concerns a method for producing a wire connection between a semiconductor chip and a substrate by means of a Wire Bonder.
A Wire Bonder is a machine with which semiconductor chips are wired to a substrate after mounting. The Wire Bonder has a capillary at the tip of which a horn is clamped. The capillary serves to attach the wire to a connection point on the semiconductor chip and to a connection point on the substrate as well as to guide the wire between the two connection points.
In years gone by a multitude of methods for producing such wire connections have been developed that take into account the continuously changing demands. With a widely used standard method for producing wire loops between the connection point on the semiconductor chip and the connection point on the substrate the end of the wire protruding out of the capillary is first melted into a ball. The wire ball is then attached to the connection point on the semiconductor chip by means of pressure and ultrasound. In doing so, ultrasound from an ultrasonic transducer is applied to the horn. This process is called ball bonding. The wire is then pulled through to the required length, formed into a wire loop and soldered to the connection point on the substrate. This last process part is called wedge bonding. After attaching the wire to the connection point on the substrate, the wire is torn off and the next bonding cycle can begin. With both bonding processes the temperature to which the substrate is heated plays an important part.
The standard method is fast as it comprises a few, simple process steps. However it has the disadvantage that the “loop height” as it is known in the art is relatively large. Therefore, new methods were developed for applications with which a small loop height is necessary. A well-known method is the so-called “reverse looping”, with which a wire ball is first applied to the connection point on the semiconductor chip. On attachment, the wire ball is pressed flat, i.e. formed into a “bump”, and then the wire is torn off. The wire connection is then produced in that the end of the wire protruding out of the capillary is melted into a ball and then, in the opposite way to the standard method, the wire ball is firstly attached to the substrate, the wire pulled through to the required length, formed into a wire loop and attached to the “bump” on the semiconductor chip as a “wedge bond”.
In the U.S. patent application no. 2005-0167473, a method is described with which a “bump” is also first attached to the connection point on the semiconductor chip. Then however, the wire connection is produced as a so-called “wedge-wedge” wire connection with which the wire is first attached to the “bump” on the semiconductor chip, pulled out to the required length and then attached to the substrate.
From the U.S. Pat. No. 6,933,608 a method has become known with which on forming the wire loop the wire is first attached to the semiconductor chip and then to the substrate as with the standard method. After attaching the wire ball to the connection point on the semiconductor chip, the capillary is first raised, then moved in horizontal direction in the direction away from the second connection point on the substrate, raised further, moved back by the same distance in horizontal direction in the direction towards the second connection point on the substrate and then lowered whereby the additional loop formed in this way is pressed against the wire ball and connected to the wire ball. Subsequently, the capillary is raised again and the wire loop formed and completed as with the standard method.
The object of the invention is to develop a method for producing a wire connection with a lower loop height that requires as little time as possible.
The method in accordance with the invention is based on the principle of the standard method for producing a wire connection between a semiconductor chip and a substrate with which the end of the wire protruding out of the capillary of a Wire Bonder is melted into a wire ball, attached to a first connection point on the semiconductor chip, pulled out to the required length and attached to a second connection point on the substrate. The method is characterized in that after attaching the wire ball to the first connection point on the semiconductor chip the capillary is first raised by a predetermined distance D1 and then moved by a predetermined distance D2 in horizontal or inclined upward direction in the direction towards the second connection point on the substrate.
With a further development of the method, after carrying out these steps the capillary is a second time raised by a predetermined distance D3 in vertical direction and then moved by a predetermined distance D4 in horizontal or inclined upward direction and in the direction towards the second connection point on the substrate in order to bend the wire directly adjacent the attachment point on the semiconductor chip in such a way that the piece of wire runs parallel to the surface of the substrate.
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present invention and, together with the detailed description, serve to explain the principles and implementations of the invention. The figures are not to scale. In the drawings:
The process steps 2 and 3 have the effect that the wire is bent by 90° directly next to the deformed wire ball attached to the first connection point and therefore, unlike with the standard method described in the introduction, already runs directly above the attachment point in almost horizontal direction towards the second connection point 4 on the substrate 5.
The difference between the two embodiments therefore exists in that with the second type, in step 3′ the capillary is not moved in horizontal direction but simultaneously in horizontal and upwards in vertical direction, i.e. diagonally. The path describes an angle φ with the horizontal that typically amounts to 30 to 45°.
In other words, the expansion described can be described in that the vertical movement of the capillary at the start of the process step 4 is interrupted en route in order to insert a short horizontal or inclined upward movement that is aligned in the direction towards the second connection point 4 on the substrate 5.
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art having the benefit of this disclosure that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims and their equivalents.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7748599 *||Nov 3, 2008||Jul 6, 2010||Kaijo Corporation||Wire bonding method, wire bonding apparatus, and wire bonding control program|
|US7851347||Oct 21, 2009||Dec 14, 2010||Kabushiki Kaisha Shinkawa||Wire bonding method and semiconductor device|
|US8042725||Apr 22, 2010||Oct 25, 2011||Kaijo Corporation||Wire bonding method, wire bonding apparatus, and wire bonding control program|
|US8232656||Oct 20, 2010||Jul 31, 2012||Kabushiki Kaisha Shinkawa||Semiconductor device|
|U.S. Classification||228/180.5, 257/E21.518|
|International Classification||B23K31/02, B23K31/00|
|Cooperative Classification||H01L24/48, H01L2224/48227, H01L2924/01082, H01L2224/48095, H01L2924/01051, B23K20/007, H01L2224/4809, H01L2924/01018, H01L2224/48464, H01L2924/00014, H01L2224/85181, H01L24/85, H01L2924/01006, H01L2924/01005, H01L2924/014, H01L2924/01033|
|European Classification||H01L24/85, B23K20/00D2B2|
|Mar 20, 2006||AS||Assignment|
Owner name: UNAXIS INTERNATIONAL TRADING LTD., SWITZERLAND
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:YU, SHUI-YUAN;REEL/FRAME:017712/0623
Effective date: 20060117