Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20060219567 A1
Publication typeApplication
Application numberUS 11/397,417
Publication dateOct 5, 2006
Filing dateApr 3, 2006
Priority dateApr 4, 2005
Publication number11397417, 397417, US 2006/0219567 A1, US 2006/219567 A1, US 20060219567 A1, US 20060219567A1, US 2006219567 A1, US 2006219567A1, US-A1-20060219567, US-A1-2006219567, US2006/0219567A1, US2006/219567A1, US20060219567 A1, US20060219567A1, US2006219567 A1, US2006219567A1
InventorsWen-Hung Hu
Original AssigneeWen-Hung Hu
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Fabrication method of conductive bump structures of circuit board
US 20060219567 A1
Abstract
A fabrication method of conductive bump structures of a circuit board includes providing the circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer formed a plurality of openings to expose the electrically connecting pads; forming a conductive layer on surfaces of the insulating protection layer and openings, and forming a metal layer on the conductive layer by electroplating, with the openings of the insulating protection layer being deposited by the metal layer; forming a resist layer on the metal layer wherein the resist layer is further patterned to form a plurality of openings corresponding to the electrically connecting pads to partially expose the metal layer; forming an adhesive layer in the openings of the resist layer; and removing the resist layer, and then removing the metal layer and conductive layer not covered by the adhesive layer, to form conductive bump structures on the electrically connecting pads.
Images(8)
Previous page
Next page
Claims(16)
1. A fabrication method of conductive bump structures of a circuit board, comprising the steps of:
providing the circuit board with a plurality of electrically connecting pads formed on at least one surface thereof, and applying an insulating protection layer on the circuit board, the insulating protection layer having a plurality of openings to expose the electrically connecting pads;
forming a conductive layer on surfaces of the insulating protection layer and openings thereof, and forming a metal layer on the conductive layer by electroplating, with the openings of the insulating protection layer being deposited by the metal layer;
forming a resist layer on the metal layer, wherein the resist layer is further patterned to form a plurality of openings corresponding to the electrically connecting pads to partially expose the metal layer;
forming an adhesive layer in the openings of the resist layer; and
removing the resist layer, and then removing the metal layer and conductive layer that are not covered by the adhesive layer, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads.
2. The fabrication method of claim 1, wherein the electrically connecting pads are fabricated by steps comprising:
forming a conductive layer on an insulating surface layer of the circuit board;
forming a resist layer on the conductive layer on the insulating surface layer and forming a plurality of openings on the resist layer to partially expose the conductive layer on the insulating surface layer; and
forming the electrically connecting pads in the openings of the resist layer by electroplating.
3. The fabrication method of claim 2, further comprising removing the resist layer and the conductive layer underneath the resist layer.
4. The fabrication method of claim 1, wherein the adhesive layer is formed on the metal layer by one of an electroplating process and a printing process.
5. The fabrication method of claim 1, wherein the adhesive layer is made of a material selected from the group consisting of tin (Sn), silver (Ag), gold (Au), copper (Cu), nickel (Ni), lead (Pb), platinum (Pt) and an alloy thereof.
6. The fabrication method of claim 5, wherein the adhesive layer is reflowed to completely cover an exposed surface of the metal layer partially exposed via the openings of the resist layer.
7. The fabrication method of claim 1, wherein the metal layer is made of a material selected from the group consisting of Pb, Sn, Ag, Cu and an alloy thereof.
8. The fabrication method of claim 1, wherein the conductive layer is made of a metal material.
9. The fabrication method of claim 1, wherein the conductive layer is made of an organic polymer material.
10. A fabrication method of conductive bump structures of a circuit board, comprising the steps of:
providing the circuit board with a plurality of electrically connecting pads formed on at least one surface thereof, and applying an insulating protection layer on the circuit board, the insulating protection layer having a plurality of openings to expose the electrically connecting pads;
forming a conductive layer on surfaces of the insulating protection layer and openings thereof, and forming a metal layer on the conductive layer by electroplating, with the openings of the insulating protection layer being deposited by the metal layer;
applying a resist layer on the metal layer and patterning the resist layer such that the resist layer only covers the metal layer corresponding to the electrically connecting pads;
removing the metal layer and the conductive layer that are not covered by the resist layer; and
removing the resist layer and forming an adhesive layer on an exposed surface of the metal layer by electroless plating.
11. The fabrication method of claim 10, wherein the electrically connecting pads are fabricated by steps comprising:
forming a conductive layer on an insulating surface layer of the circuit board;
forming a resist layer on the conductive layer on the insulating surface layer and forming a plurality of openings on the resist layer to partially expose the conductive layer on the insulating surface layer; and
forming the electrically connecting pads in the openings of the resist layer by electroplating.
12. The fabrication method of claim 11, further comprising removing the resist layer and the conductive layer underneath the resist layer.
13. The fabrication method of claim 10, wherein the adhesive layer is made of a material selected from the group consisting of Sn, Ag, Au, Cu, Ni, Pb, Pt and an alloy thereof.
14. The fabrication method of claim 10, wherein the metal layer is made of a material selected from the group consisting of Pb, Sn, Ag, Cu and an alloy thereof.
15. The fabrication method of claim 10, wherein the conductive layer is made of a metal material.
16. The fabrication method of claim 10, wherein the conductive layer is made of an organic polymer material.
Description
    CROSS-REFERENCE TO RELATED APPLICATIONS
  • [0001]
    This application claims benefit under 35 USC 119 of Taiwan Application No. 094110691, filed Apr. 4, 2005.
  • FIELD OF THE INVENTION
  • [0002]
    The present invention relates to fabrication methods for conductive bump structures of circuit boards, and more particularly, to a method for fabricating conductive bump structures on electrically connecting pads of a circuit board.
  • BACKGROUND OF THE INVENTION
  • [0003]
    To make electronic products much lighter, thinner, shorter, and smaller, packages that are characterized with a small integrated circuit area, high component density, and multiple pins, such as BGA, flip chip, MCM and so on, are becoming mainstream in the market. For example, in the flip chip technique, a plurality of electrode pads are disposed on surface of an IC chip and a plurality of electrically connecting pads corresponding to the electrode pads are formed on a circuit board. Then, the chip is disposed with its active face down on the circuit board and the electrode pads of the chip are electrically connected with the electrically connecting pads of the circuit board through a plurality of solder bumps or other conductive adhesive materials formed between the chip and the circuit board.
  • [0004]
    Conventionally, solder bumps or conductive adhesive materials are disposed on electrode pads or electrically connecting pads by printing. With both reduced pitch and size of electrically connecting pads, it becomes difficult to attach the solder bumps to the electrically connecting pads, thereby resulting in the lack of enough bonding force between the solder material and the electrically connecting pads. In addition, in that the solder material support strength is not enough, it is easy for the solder material to overflow during the reflow process.
  • [0005]
    To overcome the above drawbacks, an electroplating process is used to form solder material on a circuit board. Compared with the printing method, the electroplating process with higher accuracy can meet the requirements of fine routing so as to implement high-density wiring with reduced circuit board area. To form the solder bumps, a conductive layer is first formed on the circuit. Then, solder material can be formed on the conductive layer. Detailed processing steps for the solder bumps are shown in FIGS. 1A to 1F.
  • [0006]
    As shown in FIG. 1A, a solder mask layer 11 is formed on a circuit board 10 with a plurality of electrically connecting pads 100.
  • [0007]
    As shown in FIG. 1B, a plurality of openings 110 are formed in the solder mask layer 11 to expose the electrically connecting pads 100 of the circuit board 10.
  • [0008]
    As shown in FIG. 1C, a conductive layer 12 is formed on the exposed surface of the solder mask layer 11 and the exposed surface of the electrically connecting pads 100 in the openings 110.
  • [0009]
    As shown in FIG. 1D, a resist layer is formed on the conductive layer 12, the resist layer having openings 130 formed corresponding to the electrically connecting pads 100 to expose the conductive layer 12.
  • [0010]
    As shown in FIG. 1E, conductive bumps 14 are formed on the exposed surface of the conductive layer 12 by electroplating using the conductive layer 12 as a current conducting path.
  • [0011]
    As shown in FIG. 1F, the resist layer 13 and the conductive layer 12 underneath the resist layer 13 are removed and a metal protection layer 15 is formed on the exposed surface of the conductive bumps 14 to protect the conductive bumps 14.
  • [0012]
    In this conventional fabrication method, the conductive bumps 14 are formed in the region formed by openings 110 and the laminated openings 130. However, the deeper the openings are, the more difficult it is to form the conductive bumps 14 by electroplating.
  • [0013]
    Moreover, because the conductive layer 12 has a small electroplating area, it is difficult to keep the current density stable. The unstable current density often results in uneven conductive bumps 14, thereby affecting subsequent processing steps.
  • SUMMARY OF THE INVENTION
  • [0014]
    According to the above drawbacks, a primary objective of the present invention is to provide a fabrication method of conductive bump structures which can avoid unevenness between solder bumps to ensure stable electrical connections with external electronic devices.
  • [0015]
    Another objective of the present invention is to provide a fabrication method of conductive bump structures that can avoid the small electroplating area and deep holes of the prior art, thereby facilitating the electroplating process.
  • [0016]
    A further objective of the present invention is to decrease the use of solder material for environmental concern.
  • [0017]
    Still another objective of the present invention is to provide a fabrication method of conductive bump structures that can form conductive structures on electrically connecting pads of fine pitch circuit boards for external electrical connections.
  • [0018]
    To achieve the above and other objectives, the present invention discloses a fabrication method of conductive bump structures of a circuit board, comprising: providing a circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer that has a plurality of openings to expose the electrically connecting pads; forming a conductive layer on the insulating protection layer and surface of the openings; forming a metal layer on the conductive layer by electroplating, the openings of the insulating protection layer being deposited by the metal layer; covering the metal layer with a resist layer which is further patterned such that the resist layer to form a plurality of openings corresponding to the electrically connecting pads to partially expose the metal layer; forming an adhesive layer in the openings of the resist layer; and removing the resist layer, and then removing the metal layer and the conductive layer that are not covered by the adhesive layer to form conductive bump structures on the electrically connecting pads. Therein, if the adhesive layer is made of solder material, it is further reflowed to cover exposed surface of the metal layer.
  • [0019]
    According to another embodiment of the present invention, the fabrication method of conductive bump structures of a circuit board comprises: providing a circuit board with a plurality of electrically connecting pads formed on at least one surface thereof and covering the circuit board with an insulating protection layer that has a plurality of openings to expose the electrically connecting pads; forming a conductive layer on the insulating protection layer and surface of the openings and forming a metal layer on the conductive layer by electroplating, the openings of the insulating protection layer being deposited by the metal layer; covering the metal layer with a resist layer which is further patterned such that the resist layer only covers the metal layer corresponding in position to the electrically connecting pads; removing the metal layer and the conductive layer that are not covered by the resist layer; and removing the resist layer and forming an adhesive layer on exposed surface of the metal layer.
  • [0020]
    In the present invention, a metal layer is directly formed on the whole conductive layer that is not covered by a resist layer and accordingly has a larger electroplating area compared with the prior art, thereby eliminating the prior art drawbacks such as a relatively small electroplating area, electroplating difficulty due to unstable current density, and the presence of deep holes. In addition, an even and flat surface for the metal layer of the present invention ensures that the subsequently formed conductive bump structures have uniform height, thereby improving the quality of electrical connections between the conductive bump structures and external electronic devices.
  • [0021]
    Furthermore, the metal layer can be formed of a low cost copper layer, thereby reducing the fabrication cost and speeding up the fabrication process. The present invention also reduces the use of soldering material, which not only reduces the fabrication cost and protect environment, but also avoids bridge and short circuit problems caused by too much soldering material melted in the reflowing process. Thus, the present invention can provide conductive structures on electrically connecting pads of fine pitch circuit boards for external electrical connections.
  • BRIEF DESCRIPTION OF DRAWINGS
  • [0022]
    FIGS. 1A to 1F (PRIOR ART) are cross-sectional diagrams showing a conventional fabrication method of conductive bump structures on electrically connecting pads of a circuit board;
  • [0023]
    FIGS. 2A to 2L are cross-sectional diagrams showing a fabrication method of conductive bump structures of a circuit board according to a first embodiment of the present invention; and
  • [0024]
    FIGS. 3A to 3G are cross-sectional diagrams showing a fabrication method of conductive bump structures of a circuit board according to a second embodiment of the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0025]
    Preferred embodiments of a fabrication method of conductive bump structures of a circuit board proposed in the present invention are described as follows with reference to FIGS. 2A to 2L and 3A to 3G.
  • [0026]
    FIGS. 2A to 2L show a fabrication method of conductive bump structures of a circuit board according to a first embodiment of the present invention. It should be noted that the figures are diagrams which only show basic constructions related to the present invention.
  • [0027]
    As shown in FIGS. 2A to 2D, a circuit board with a plurality of electrically connecting pads formed on surface thereof is first provided. As shown in FIG. 2A, a conductive layer 42 is formed on an insulating surface layer 41 of a circuit board to function as a current conductive path in a subsequent electroplating process. The conductive layer 42 can be a metal layer or several laminated metal layers formed of copper (Cu), tin (Sn), nickel (Ni), chromium (Cr), titanium (Ti), Cu—Cr alloy or tin-lead (Sn—Pb) alloy. Alternatively, the conductive layer 42 can be formed of conductive polymer material such as polyacetylene, polyanion or organic sulphur polymer. As shown in FIG. 2B, a resist layer 43 is formed on the conductive layer 42 by printing, spin-coating or attaching, wherein the resist layer 43 can be a photoresist layer such as a dry film layer or a liquid photoresist layer or a non-photoresist layer. Then, the resist layer 43 is patterned by development, exposure or laser to form a plurality of openings 430 to partially expose the conductive layer 42. As shown in FIG. 2C, electrically connecting pads 440 are formed in the openings 430 on the exposed surface of the conductive layer 42 by electroplating using the conductive layer 42 as a current conducting path. Meanwhile, the conductive circuit (not shown) can be formed by the electroplating process. As shown in FIG. 2D, the resist layer 43 and the conductive layer 42 underneath the resist layer 43 are then removed.
  • [0028]
    Referring to FIG. 2E, an insulating protection layer 45 is formed on surface of the circuit board. In the present embodiment, the insulating protection layer 45 is coated on the surface of the circuit board by printing, spin-coating or attaching and then patterned by exposure, development or laser to form a plurality of openings 450 to expose the electrically connecting pads 440. Wherein, the insulating protection layer 45 is formed of solder mask material.
  • [0029]
    Referring to FIG. 2F, a conductive layer 46 is formed on the insulating protection layer 45 and surface of the openings 450 to function as current conductive path in a subsequent electroplating process. The conductive layer 46 can be made of a metal, an alloy or several laminated metal layers or conductive polymer material.
  • [0030]
    Referring to FIG. 2G, a metal layer 47 is formed on the conductive layer 46 by electroplating using the conductive layer 46 as a current conductive path, and, meanwhile, the openings 450 are deposited by the metal layer 47 to keep the surface of the metal layer 47 even and flat. Wherein, the metal layer 47 can be made of Pb, Sn, silver (Ag), Cu or an alloy thereof. Preferably, the metal layer 47 is made of copper.
  • [0031]
    Referring to FIG. 2H, a resist layer 48 is formed on the metal layer 47 and then patterned to form a plurality of openings 480 corresponding to the electrically connecting pads 440 to partially expose the metal layer 47. In the present embodiment, the resist layer 48 is formed on the metal layer 47 by printing, spin-coating or attaching.
  • [0032]
    Referring to FIG. 2I, an adhesive layer 49 is formed in the openings 480, which can be formed of Cu, Sn, Pb, Ag, Ni, gold (Au), platinum (Pt) or an alloy thereof by electroplating or printing process.
  • [0033]
    Referring to FIG. 2J, the resist layer 48 is removed by chemical etching or physical stripping.
  • [0034]
    Referring to FIG. 2K, the metal layer 47 and the conductive layer 46 that are not covered by the adhesive layer 49 are removed, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads. to form conductive bump structures on the electrically connecting pads 440.
  • [0035]
    Referring to FIG. 2L, if the adhesive layer 49 is made of solder material, the adhesive layer 49 is reflowed to completely cover the exposed surface of the metal layer 47.
  • [0036]
    FIGS. 3A to 3G show a fabrication process for conductive bump structures according to a second embodiment of the present invention.
  • [0037]
    Referring to FIG. 3A, a circuit board 50 with a plurality of electrically connecting pads 510 formed on at least one surface thereof is provided.
  • [0038]
    Referring to FIG. 3B, the circuit board 50 is covered by an insulating protection layer 55. In the present embodiment, the insulating protection layer 55 is formed on the circuit board 50 by printing, spin-coating or attaching, which is then patterned to form a plurality of openings 550 to expose the electrically connecting pads 510.
  • [0039]
    Referring to FIG. 3C, a conductive layer 56 is formed on the insulating protection layer 55 and the surface of the openings 550 to function as a current conductive path in a subsequent electroplating process.
  • [0040]
    Referring to FIG. 3D, a metal layer 57 is formed on the conductive layer 56 by electroplating using the conductive layer 56 as a current conductive path, the openings 550 of the insulating protection layer 55 being deposited by the metal layer 57 to keep the surface of the metal layer 57 even and flat.
  • [0041]
    Referring to FIG. 3E, a resist layer 58 such as a dry film photoresist layer or a liquid photoresist layer is formed on the metal layer 57 by printing, spin-coating or attaching and then patterned such that the resist layer 58 only covers the metal layer 57 corresponding in position to the electrically connecting pads 510.
  • [0042]
    Referring to FIG. 3F, the metal layer 57 and the conductive layer 56 that are not covered by the resist layer 58 are removed, such that portions of the metal layer and conductive layer underneath the adhesive layer corresponding to the electrically connecting pads are retained to form the conductive bump structures on the electrically connecting pads.
  • [0043]
    Referring to FIG. 3G, the resist layer 58 is removed by chemical etching or physical stripping such that an adhesive layer 59 can be formed on the exposed surface of the metal layer 47 by electroless plating.
  • [0044]
    In the present invention, a metal layer is directly formed on the whole conductive layer that is not covered by a resist layer and accordingly has a larger electroplating area compared with the prior art, thereby eliminating the prior art drawbacks such as a relatively small electroplating area, electroplating difficulty due to unstable current density, and the presence of deep holes. In addition, the even and flat surface of the metal layer of the present invention ensures that the subsequently formed conductive bump structures have uniform height, thereby improving the quality of electrical connections between the circuit board and external electronic devices.
  • [0045]
    The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2728693 *Aug 24, 1953Dec 27, 1955Motorola IncMethod of forming electrical conductor upon an insulating base
US5545308 *Jun 19, 1995Aug 13, 1996Lynntech, Inc.Method of using conductive polymers to manufacture printed circuit boards
US7216424 *Dec 29, 2004May 15, 2007Phoenix Precision Technology CorporationMethod for fabricating electrical connections of circuit board
US20080179190 *Apr 2, 2008Jul 31, 2008Phoenix Precision Technology CorporationMethod for fabrication of a conductive bump structure of a circuit board
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7674362 *Mar 9, 2010Phoenix Precision Technology CorporationMethod for fabrication of a conductive bump structure of a circuit board
US8188377 *May 29, 2012Unimicron Technology Corp.Circuit board having electrically connecting structure and fabrication method thereof
US8274150 *May 10, 2011Sep 25, 2012Chipmos Technologies Inc.Chip bump structure and method for forming the same
US8507376Oct 7, 2009Aug 13, 2013Atotech Deutschland GmbhMethod to form solder deposits on substrates
US8871631Jun 23, 2011Oct 28, 2014Atotech Deutschland GmbhMethod to form solder deposits on substrates
US20080179190 *Apr 2, 2008Jul 31, 2008Phoenix Precision Technology CorporationMethod for fabrication of a conductive bump structure of a circuit board
US20090050359 *Aug 21, 2008Feb 26, 2009Phoenix Precision Technology CorporationCircuit board having electrically connecting structure and fabrication method thereof
US20110189848 *Oct 7, 2009Aug 4, 2011Ingo EwertMethod to form solder deposits on substrates
US20110291273 *Dec 1, 2011Chipmos Technologies Inc.Chip bump structure and method for forming the same
US20120118752 *May 17, 2012Dyconex AgMethod for Electrodeposition of an Electrode on a Dielectric Substrate
EP2180770A1 *Oct 21, 2008Apr 28, 2010Atotech Deutschland GmbhMethod to form solder deposits on substrates
EP2244285A1Apr 24, 2009Oct 27, 2010ATOTECH Deutschland GmbHMethod to form solder deposits on substrates
EP2405468A1 *Jul 5, 2010Jan 11, 2012ATOTECH Deutschland GmbHMethod to form solder deposits on substrates
EP2405469A1Jul 5, 2010Jan 11, 2012ATOTECH Deutschland GmbHMethod to form solder alloy deposits on substrates
EP2416634A1Aug 2, 2010Feb 8, 2012ATOTECH Deutschland GmbHMethod to form solder deposits on substrates
EP2453471A2 *Oct 17, 2011May 16, 2012Dyconex AGMethod for electrodeposition of an elctrode on a dielectric substrate
EP2503029A1Mar 22, 2011Sep 26, 2012Atotech Deutschland GmbHProcess for etching a recessed structure filled with tin or a tin alloy
EP2506690A1Mar 28, 2011Oct 3, 2012Atotech Deutschland GmbHMethod to form solder deposits and non-melting bump structures on substrates
WO2010046235A1 *Oct 7, 2009Apr 29, 2010Atotech Deutschland GmbhMethod to form solder deposits on substrates
WO2012004136A2Jun 23, 2011Jan 12, 2012Atotech Deutschland GmbhMethod to form solder alloy deposits on substrates
WO2012004137A3 *Jun 23, 2011Mar 1, 2012Atotech Deutschland GmbhMethod to form solder deposits on substrates
WO2012016932A1Jul 29, 2011Feb 9, 2012Atotech Deutschland GmbhMethod to form solder deposits and non-melting bump structures on substrates
WO2012126672A1Feb 9, 2012Sep 27, 2012Atotech Deutschland GmbhProcess for etching a recessed structure filled with tin or a tin alloy
Classifications
U.S. Classification205/125
International ClassificationC25D5/02
Cooperative ClassificationH05K3/421, H05K2203/043, H05K2203/054, H05K3/4007, H05K2201/09436, H05K3/064, H05K2201/0367, C25D5/022, H05K3/3484, H05K3/3473, H05K2201/09563, H05K2203/0568, H05K3/423, H05K3/062
European ClassificationH05K3/34F4, C25D5/02B, H05K3/40B, H05K3/42B
Legal Events
DateCodeEventDescription
Apr 3, 2006ASAssignment
Owner name: PHOENIX PRECISION TECHNOLOGY CORPORATION, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HU, WEN-HUNG;REEL/FRAME:017725/0125
Effective date: 20060310