|Publication number||US20060250291 A1|
|Application number||US 11/122,587|
|Publication date||Nov 9, 2006|
|Filing date||May 5, 2005|
|Priority date||May 5, 2005|
|Also published as||CN101204013A, CN101204013B, US7136005, WO2006121953A2, WO2006121953A3|
|Publication number||11122587, 122587, US 2006/0250291 A1, US 2006/250291 A1, US 20060250291 A1, US 20060250291A1, US 2006250291 A1, US 2006250291A1, US-A1-20060250291, US-A1-2006250291, US2006/0250291A1, US2006/250291A1, US20060250291 A1, US20060250291A1, US2006250291 A1, US2006250291A1|
|Inventors||Colin Lyden, Michael Coln, Robert Brewer|
|Original Assignee||Lyden Colin G, Coln Michael C, Robert Brewer|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (6), Classifications (5), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to an improved accurate, low noise analog to digital converter system.
Wide dynamic range and low noise are desirable qualities of analog to digital converter systems e.g. those used in computed tomography (CT) scanners. In that environment there is a particularly great demand for a wide dynamic range, e.g., 120 dB to accommodate very bright radiation passing through low density body areas. But at the low end it is also desirable to have very low noise to improve the quality and contrast of low level radiation passing through bone, for example. One approach to this issue has been to apply a conditional reset which can be done a number of times in a measuring period to accommodate larger signals and even less than one per measuring period to reduce noise at lower signals. One such approach is disclosed in U.S. Pat. No. 6,660,991, Brombacher et al. However, in that approach the input charge is dissipated during reset making the output less accurate and during reset the noise form the amplifier is communicated to the feedback capacitor. Brombacher et al. for one, attempts to mitigate these problems by interpolation and filtering of delta values but this is inherently inexact and information will be lost.
It is therefore an object of this invention to provide an improved more accurate low noise analog to digital converter system.
It is a further object of this invention to provide such an improved more accurate low noise analog to digital converter system which isolates the input from the feedback capacitor and integrator circuit amplifier to preserve charge and reduce reset noise.
It is a further object of this invention to provide an improved more accurate low noise analog to digital converter system which isolates the integrator circuit amplifier from the feedback capacitor to reduce noise.
It is a further object of this invention to provide an improved more accurate low noise analog to digital converter system which decouples the resetting from the analog to digital converter (ADC) avoiding ADC latency in the reset path and providing faster reset response.
It is a further object of this invention to provide an improved more accurate low noise analog to digital converter system which with decoupling of the resetting enables the ADC to be multiplexed with many integrator channels.
It is a further object of this invention to provide an improved more accurate low noise analog to digital converter system which provides better estimation of the average input over the measuring period.
The invention results from the realization that a more accurate, lower noise conditional resetting integrator circuit in an analog to digital converter system can be achieved by sampling with an analog to digital converter the output of an integrating circuit a number of times during a measuring period; isolating the input from the integrating circuit during a sample event; generating a reset signal in response to the integrating circuit output reaching a predetermined level; and resetting the feedback capacitor of the integrating circuit by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.
The subject invention, however, in other embodiments, need not achieve all these objectives and the claims hereof should not be limited to structures or methods capable of achieving these objectives.
This invention features an improved accurate, low noise analog to digital converter system including an integrator circuit having an amplifier circuit and a feedback capacitor and an analog to digital converter with its input coupled to the integrator circuit output for sampling the integrator circuit output at least once each measuring period. A conditional reset circuit resets the feedback capacitor after a predetermined integrator circuit output voltage has been reached; and the switching system selectively isolates the feedback capacitor during sampling and reset.
In a preferred embodiment there may be a sample reconstruction circuit responsive to the output of the analog to digital converter for reconstructing the output of the integrator circuit. The sample reconstruction circuit may include a digital computation circuit for determining the difference between the values of each sample occurring during a measuring period and adding the value of any sample event at which the feedback capacitor has been reset for reconstructing the output of the integrator circuit. The sample reconstruction circuit may include a reset event correction circuit and a slope estimation computation circuit. The switching system may include an input hold switching circuit for isolating the integrator circuit from the input during a sampling event. The conditional reset circuit may include a reset switching circuit for connecting the feedback capacitor to a reference voltage source during a conditional reset. The switching system may include an isolation switching circuit for isolating the amplifier circuit from the feedback capacitor during a conditional reset. The digital computation circuit may include a storage device for storing values of samples at sampling events and values of samples at which the feedback capacitor has been reset. The digital computation circuit may include a summing circuit for differencing sample values at sampling events and adding values of samples at which the feedback capacitor has been reset. The conditional reset circuit may include a reference voltage source. The conditional reset circuit may include a comparator for determining whether the integrator circuit output has reached a predetermined integrator circuit output voltage. The conditional reset circuit may include a reference charge source and a reset switching circuit for connecting the reference charge source to the feedback capacitor. Resetting may occur at the next sample event after a predetermined integrator circuit output voltage has been reached. The integrator circuit may receive its input from a photodiode.
The invention also features an accurate low noise method of conditionally resetting an integrator circuit in an analog to digital system including sampling, with an analog to digital converter, the output of an integrating circuit a number of times during a measuring period and isolating the input from the integrating circuit during a sample event. A reset signal is generated in response to the integrating circuit output reaching a predetermined level, and the feedback capacitor of the integrating circuit is reset by isolating it from the amplifier circuit of the integrating circuit and connecting it to a reference source during a sample event.
In a preferred embodiment the difference between the values of each sample occurring during a measuring period may be determined and the value of any sample at which the feedback capacitor has been reset may be added for reconstructing the output of the integrator circuit. The values of samples at sampling events and the values of samples at which the feedback capacitor has been reset may be stored. The reference source may include a voltage reference source or a charge reference source. The resetting may occur at the next sample event after a predetermined integrator circuit output voltage has been reached. The integrating circuit may receive an input from a photodiode.
Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:
Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings. If only one embodiment is described herein, the claims hereof are not to be limited to that embodiment. Moreover, the claims hereof are not to be read restrictively unless there is clear and convincing evidence manifesting a certain exclusion, restriction, or disclaimer.
There is shown in
In operation, integrating circuit 12 receives a charge from photodiode 50 with intrinsic capacitance 52, and it provides an output to analog to digital converter 18. An output of integrator circuit 12 is also provided to comparator 22. Analog to digital converter 18 may take any number of samples during a predetermined measuring period, for example, four samples per measuring period. A measuring period may be determined by a manufacturers specifications or other criteria. A typical measuring period for a photodiode may be 300 microseconds, for example. Each time analog to digital converter 18 samples the output of amplifier 14 input hold switch 28 is enabled by timing signal tH to open and isolate photodiode 50 with capacitance 52 from amplifier 14 and feedback capacitor 16. This accomplishes two things, first it prevents the normal capacitor noise kT/C from being communicated to feedback capacitor 16 thereby reducing noise in the system. It also prevents the loss of charge from photodiode 50 to feedback capacitor 16 and amplifier 14 during the sampling period. Instead the charge is stored on the intrinsic capacitance 52 and is submitted to amplifier 14 and feedback capacitor 16 after the sample event is over, the timing signal tH has ended and input hold switch 28 is once again closed. Comparator 22 monitors the output of amplifier 14 of integrating circuit 12. If that output voltage exceeds a predetermined voltage level indicating that the signal is large enough that it may soon exceed the limits of analog to digital converter 18, comparator 22 at the next sampling event represented by tC produces a reset signal at tR to open isolating switch 32 and close reset switches 36 and 38. This disconnects feedback capacitor 16 from amplifier 14, thereby eliminating any communication of noise from amplifier 14 to feedback capacitor 16 and applies the reference voltage from reference source 24 to reset feedback capacitor 16 to zero. This operation is explained in more detail which respect to
Typically when photodiode 50 is one of a multiplicity of photodiodes in a computer tomography scanner, the components shown in dashed line in
The operation of the conditional resetting can be seen more clearly with reference to
The actual switching effected by tH, tC and tR can be seen in
One implementation of a sample reconstruction circuit 40,
Result=Final−Initial+Intermediate reset samples. (1)
Thus summing circuit 142 receives one input at 152 from storage S0 and receives the second input from storage S0 on line 154 if there has been a reset. Similarly summing circuit 144, 146, and 148 will receive an input from the previous summing circuit and, if there has been a reset it will also receive an input 156, 158, 160 from the associated storage, S1, S2, S3. The final summer 150 receives an input from the previous summer 148 and an input from storage S4.
Instead of employing the difference or delta to reconstruct the output of the integrator circuit, the sample reconstruction circuit 40 b,
Although thus far the system has been shown using a reference source 24,
In the implementation of the system of
Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments.
In addition, any amendment presented during the prosecution of the patent application for this patent is not a disclaimer of any claim element presented in the application as filed: those skilled in the art cannot reasonably be expected to draft a claim that would literally encompass all possible equivalents, many equivalents will be unforeseeable at the time of the amendment and are beyond a fair interpretation of what is to be surrendered (if anything), the rationale underlying the amendment may bear no more than a tangential relation to many equivalents, and/or there are many other reasons the applicant can not be expected to describe certain insubstantial substitutes for any claim element amended.
Other embodiments will occur to those skilled in the art and are within the following claims.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7623053||Sep 26, 2007||Nov 24, 2009||Medtronic, Inc.||Implantable medical device with low power delta-sigma analog-to-digital converter|
|US7714757||Sep 26, 2007||May 11, 2010||Medtronic, Inc.||Chopper-stabilized analog-to-digital converter|
|US8035538 *||Dec 16, 2009||Oct 11, 2011||Analog Devices, Inc.||Sigma-delta conversion circuit suitable for photocurrent measurement applications|
|US8265223||Jul 14, 2009||Sep 11, 2012||Koninklijke Philips Electronics N.V.||Data acquisition|
|US20140197320 *||Jan 15, 2013||Jul 17, 2014||Siemens Medical Solutions Usa, Inc.||Multiple Timing Measurements for Positron Emission Tomography|
|WO2009042012A1 *||Jul 25, 2008||Apr 2, 2009||Medtronic Inc||Capacitive digital-to-analog converter reset in an implantable medical device analog-to digital converter|
|Cooperative Classification||H03M1/122, H03M1/08|
|Jan 10, 2006||AS||Assignment|
Owner name: ANALOG DEVICES, INC., MASSACHUSETTS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LYDEN, COLIN G.;COLN, MICHAEL C.;BREWER, ROBERT;REEL/FRAME:017177/0162;SIGNING DATES FROM 20050616 TO 20050920
|May 14, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Apr 16, 2014||FPAY||Fee payment|
Year of fee payment: 8