US 20060289946 A1
A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer such as a floating gate. A dummy stack ring is formed around the memory array. An insulating layer is formed over the memory array. The dummy stack ring has a composition and height substantially the same as a composition and height of the gate stack to insure that a CMP of the insulating layer is uniform across the memory array.
1. A semiconductor device comprising:
an active area formed in a semiconductor substrate;
a plurality of non-volatile memory cells formed in the active area, each of the plurality of non-volatile memory cells having a source, a drain, and a gate stack, the gate stack comprising:
a first oxide layer formed over the active area;
a discrete charge storage layer formed over the first oxide layer;
an second oxide layer formed over the discrete charge storage layer; and
a control gate formed over the second oxide layer; and
a ring formed around the plurality of memory cells, the ring having a composition and height substantially the same as a composition and height of the gate stack.
2. The semiconductor device of
3. The semiconductor device of
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11. A semiconductor device comprising:
a memory array having a plurality of non-volatile memory cells, each non-volatile memory cell of the plurality of non-volatile memory cells having a gate stack, the gate stack including a control gate and a discrete charge storage layer; and
a dummy stack ring formed around the memory array, the dummy stack ring having a composition and height substantially the same as a composition and height of the gate stack.
12. The semiconductor device of
13. The semiconductor device of
14. The semiconductor device of
15. The semiconductor device of
16. A method of forming a semiconductor device comprising:
defining a plurality of active areas on a semiconductor substrate;
forming a plurality of gate stacks on the plurality of active areas;
forming a ring over the substrate and around the plurality of gate stacks, the ring having a composition and height substantially the same as a composition and height of the plurality of gate stacks;
depositing an insulating layer over the plurality of gate stacks and the ring; and
planarizing the insulating layer.
17. The method of
18. The method of
19. The method of
20. The method of
This invention relates in general to semiconductor devices, and more particularly, to a semiconductor device and a process for maintaining topographical uniformity of a memory array during chemical mechanical polishing.
During the manufacture of a semiconductor device, it may be necessary to planarize the surface of the semiconductor device as one or more of the manufacturing steps. Chemical Mechanical Polishing (CMP) is one such process used to planarize surfaces of semiconductor devices. However, it is difficult to guarantee uniformity of the planarization because of varying layouts on the semiconductor device.
A memory array is typically one of the more dense areas of an integrated circuit layout. As part of a manufacturing process of the memory array, an interlevel dielectric (ILD) is deposited over the memory cells to insulate the memory cells from the first metal layer. Deposition of the dielectric material typically results in an uneven surface. The uneven surface is typically planarized using a CMP process before the metal layer is formed. Because the array layout is typically denser and may be higher than the adjacent peripheral circuit layout, more dielectric material may be removed from the edges of the array than from the center of the array as the CMP transitions to the lower peripheral circuit layout, resulting in less dielectric material over the edge or the array than the center of the array. The non-uniformity in thickness, caused by interactions between the memory array layout and the polishing process, can result in reliability issues such as electrical opens, high resistance contacts, electrical shorts, or other leakage paths in the array.
Traditionally, tiling has been used in the manufacture of semiconductor devices to help solve the varying height problem of the dielectric material. Tiles are printed dummy features used to fill in the low areas or less dense areas of the layout to insure a uniform surface during CMP. However, because of the greater layout density of the memory array, tiles generally cannot be used within the memory array.
Therefore, a need exists for a way to provide for better topographical uniformity of the ILD over a semiconductor memory array.
The present invention is illustrated by way of example and not limited in the accompanying figures, in which like references indicate similar elements, and in which:
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
Generally, the present invention provides a semiconductor device and method for insuring more uniform planarization of an ILD over a semiconductor substrate having an active area with relatively densely spaced non-volatile memory cells. The non-volatile memory cells are surrounded by a dummy ring. The dummy ring insures that there is uniform planarization of the ILD during CMP so that the thickness of the ILD at an edge of the array is the same as the thickness at a central portion of the array. In the illustrated embodiment, the dummy ring has a height and composition that matches the height and composition of the gate stack. In one embodiment, the gate stack includes a floating gate. In other embodiments, the gate stack may include another type of discrete charge storage layer such as a layer comprising nanocrystals or a nitride. Also, in another embodiment, the dummy ring may be discontinuous and still provide topographical uniformity between the edge and center portions of the plurality of memory cells. The present invention is defined by the claims and is better understood after reading the rest of the detailed description.
Memory array 12 includes a plurality of parallel longitudinal active areas 16 formed in a semiconductor substrate, and a plurality of word lines 18 formed perpendicular to the active areas 16. In the illustrated embodiment, memory array 12 includes a plurality of conventional floating gate non-volatile memory cells. A memory cell is formed at the intersection of each word line 18 and active area 16. Contacts, such as contacts 25, 26, and 27, are formed to couple the current electrodes of the memory cells to bit lines implemented in a metal layer above the memory array 12 (not shown). In
Each of the plurality of longitudinal active areas 16 is surrounded and isolated from each other by trenches 19. The trenches 19 may be formed by any of several known techniques. For example, in one technique, a resist layer mask is deposited followed by an etch step. The depth of the trenches can vary and are filled with a dielectric material.
An active boundary 14 surrounds the memory array 12. The active boundary 14 is formed by etching a trench around the array 12 resulting in a structure similar to active areas 16. In one embodiment, the active boundary 14 may be approximately 2 microns wide and has the same height as the active areas in the array 12. The active boundary 14 width may be different in other embodiments. The active boundary 14 provides support for the edge of the array during a CMP of the dielectric material filling the trenches to insure a uniform topography of the dielectric material.
A dummy stack ring 20 is formed on active boundary 14. The dummy stack ring 20 has a width smaller than the width of the active boundary 14, and may be between about 0.5 and 2 microns wide. The dummy stack ring 20 has the same composition and height as a gate stack of the memory array 12. However, the dummy stack ring 20 will not have etched shapes like the gate stacks of the memory array 12 and will be self-aligned. Also, the dummy stack ring 20 is electrically isolated from the active areas 16; however, in other embodiments, the dummy stack ring 20 may be coupled to a power supply voltage terminal such as ground. After the gate stacks and the dummy stack ring 20 are formed, a relatively thick ILD layer (see
The dummy stack ring 20 has the same composition as gate stacks 15 and 17 and is formed at the same time that gate stacks 15 and 17 are formed using the same process steps. Dummy stack ring 20 includes a tunnel oxide 34, a floating gate 26, an ONO layer 30, and a polysilicon layer 21. Providing a dummy stack ring with the same composition as the gate stacks 15 and 17 insures that the dummy stack ring will have the same height as the gate stacks, labeled “H” in
Nitride sidewall spacers, such as sidewall spacers 36 are formed on the sides of the gate stacks and the active boundary 20. The nitride sidewall spacers are illustrated on the sides of gate stacks in
An ILD layer 24 is deposited over the semiconductor device 10. In the illustrated embodiment, ILD layer 24 is high density plasma (HDP) undoped silicate glass (USG). In other embodiments the ILD layer 24 may be another conventional deposited oxide such as TEOS. The ILD layer 24 is planarized using a conventional CMP process and conventional CMP slurry. After being planarized the ILD 24 slopes down on the side of active boundary 20 opposite the array 12 because the double-polysilicon gate stacks of array 12 are higher than the single-polysilicon circuitry on semiconductor device 10. As can be seen in
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.