US 20060289976 A1
An embedded passive structure, its method of formation, and its intergration onto a substrate during fabrication are disclosed, In one embodiment the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower electrode layers are patterned in such a way as to reduce damage and improve cycle time. In one embodiment, the capacitor dielectric has a high dielectric constant and the substrate is an organic packaging substrate.
1. An embedded passive device in a substrate comprising:
a first conductive layer overlying a polymer build-up layer;
a dielectric layer overlying the first conductive layer;
a second conductive layer overlying the dielectric layer; and
a via that extends from the second conductive layer through the polymer build-up layer and electrically couples to an underlying interconnect, wherein the via extends through an opening patterned in the dielectric layer.
2. The embedded passive device of
the first conductive layer is further characterized as a first electrode layer;
the dielectric layer is further characterized as a capacitor dielectric layer;
the second conductive layer is further characterized a second electrode layer; and
a combination of the first electrode layer, the capacitor dielectric layer, and the second electrode layer forms an embedded capacitor structure in the substrate.
3. The embedded passive device of
4. The embedded passive device of
5. The embedded passive device of
6. The embedded passive device of
7. The embedded passive device of
8. The embedded passive device of
9. The embedded passive device of
10. An embedded passive laminate for applying to a substrate comprising:
a patterned electrode layer;
a patterned capacitor dielectric layer; and
an unpatterned electrode layer.
11. The embedded passive laminate of
12. The embedded passive laminate of
13. The embedded passive laminate of
14. The embedded passive laminate of
15. The embedded passive laminate of
16. A method for forming embedded passive structures in an organic packaging substrate comprising affixing an embedded passive laminate on the organic packaging substrate, wherein the embedded passive laminate includes a pre-patterned capacitor dielectric layer.
17. The method of
18. The method of
19. The method of
20. A method for forming an embedded thin film capacitor comprising:
depositing a ceramic dielectric layer over a base layer of conductive material;
patterning the ceramic dielectric layer to form first openings that expose portions of the base layer;
depositing a lower electrode layer over the ceramic dielectric layer; and
patterning the lower electrode layer to form second openings that expose portions of the base layer.
21. The method of
22. The method of
mounting the thin film capacitor laminate over a dielectric layer on a substrate, wherein the patterned lower electrode layer is positioned between the base layer and the dielectric layer;
removing portions of the base layer;
forming via openings that pass through the first opening and the second opening and that extend through the dielectric layer to an underlying conductive structure;
filling the via openings with a conductive material; and
patterning the conductive material to form a conductive structure.
23. The method of
24. The method of
25. The method of
26. The method of
27. The method of
28. The method of
29. A method for packaging a semiconductor die comprising mounting the semiconductor die to an organic packaging substrate, wherein the organic packaging substrate includes embedded thin film capacitors that have been formed by applying a laminate that includes a pre-patterned capacitor dielectric layer over build-up layers of the packaging substrate.
30. The method of
Embodiments of the present invention relate generally to semiconductor technology and more specifically to semiconductor packaging.
The demand for increased mobility in consumer electronics is pressuring manufacturers to scale electronic technologies (e.g., semiconductor devices) to ever smaller dimensions. At the same time, the demand for increased functionality, speed, noise elimination, etc., is forcing manufactures to increase the number of passive components (e.g., capacitors and resistors) used by consumer electronic devices. Passive component integration has traditionally been accomplished by mounting them onto package and/or printed circuit board (PCB) substrate surfaces. Restricting the location of the passive components to the substrate's surface however can limit the passive components' operational capabilities (due to their inherent distance from the semiconductor device) and the substrate's scalability.
One way manufacturers are attempting to address this is by embedding the passive components in the substrate, a technique referred to as embedded passive technology. This frees up surface real estate and facilitates substrate miniaturization. Speed and signal integrity also improves because embedded components provide a more direct path through which the IC signals propagate.
One particular area of interest with respect to embedded passive technology has been the incorporation of thin film capacitors (TFCs) into organic packaging (e.g., bismaleimide triazine resin, etc.) substrates. Among the various materials being considered for use as capacitor dielectrics are high-k ceramic materials. However, high-k ceramic materials can require processing at high temperatures (e.g., furnace annealing at 600-800 degrees Celsius) in order to achieve their high dielectric constant properties. At these temperatures, organic packaging substrates can melt.
One technique for addressing this involves mounting a pre-fabricated TFC laminate that has already been annealed onto the organic substrate. Shown in
The use of this integration scheme however is not without its problems. More specifically, any one of the processes used to pattern the lower electrodes 110, the upper electrode portions 121, and/or the via openings 122 can damage the hi-k ceramic dielectric 108 and thereby impact the functionality of the TFC.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.
In the following detailed description, an embedded passive structure and its method of formation are disclosed. Reference is made to the accompanying drawings within which are shown, by way of illustration, specific embodiments by which the present invention may be practiced. It is to be understood that other embodiments may exist and that other structural changes may be made without departing from the scope and spirit of the present invention.
The terms on, above, below, and adjacent as used herein refer to the position of one layer or element relative to other layers or elements. As such, a first element disposed on, above, or below a second element may be directly in contact with the second element or it may include one or more intervening elements. In addition, a first element disposed next to or adjacent a second element may be directly in contact with the second element or it may include one or more intervening elements.
In one embodiment, a thin film laminate for use in the fabrication of embedded passives and its method of formation are disclosed. In one embodiment, the formation of embedded passive structures using a prepared thin film laminate mounted on a substrate is disclosed. Aspects of these and other embodiments will be discussed herein with respect to
The conductive film 702 will subsequently be used to form a TFC capacitor electrode layer. The conductive film 702 is also used as the base material for forming the TFC's capacitor dielectric and opposing capacitor electrodes (not shown in
Turning now to
Any number of materials can be used to form the dielectric film 804, 802. For example, it can include high dielectric constant (high-k) materials such as barium titinate (BaTiO3), strontium titinate (SrTiO3), barium strontium titinate (BaSrTiO3), or the like. For the purposes of this specification and as used by one of ordinary skill, barium titinate and barium strontium titinate are commonly also referred to as BT and BST, respectively. The dielectric film 804, 802 can be deposited using conventional physical vapor deposition (PVD)(i.e., evaporation, sputtering, etc.), chemical vapor deposition, spin-on processes, laser ablation, ion plating, plasma spray processes, or the like. In one embodiment, the dielectric 804,802 is a sputtered ceramic dielectric material. In one embodiment the dielectric 804,802 is a sputtered BST layer having a thickness in a range of approximately 0.1 microns to approximately 1.0 microns and deposited at a temperature less than approximately 200 degrees Celsius.
Turning now to
Turning now to
Next, as shown in
In accordance with one embodiment, the combination of the conductive film 702, the patterned capacitor dielectric 804, and the patterned conductive regions 1102 forms a pre-fabricated, pre-patterned lower electrode and capacitor dielectric TFC laminate 1100 that can be used to define embedded passive structures over a substrate. To the extent that the TFC laminate 1100 includes a high-k ceramic dielectric layer such as BST, BT, or the like, it can now be annealed at a temperature, for instance, in a range of approximately 500-900 degrees Celsius in order to adjust the dielectric constant accordingly. Alternatively, the annealing can take place at an earlier stage of the TFC fabrication process, for example prior to formation of resist members 1006.
Turning now to
The substrate 1200 shown here includes polymer build-up layers 1202 and 1203 and a conductive build-up layer that includes interconnects 1206 and vias 1204. Polymer build-up layers can be formed, for example, using a dielectric material, such as an Ajinomoto Build-Up Film (ABF). Interconnects/vias can be formed, for example, using copper. The use and formation of build-up layers is known to one of ordinary skill. Underlying the vias 1204 and build-up dielectric film 1202 includes layer(s) 1208. Typically, layer(s) 1208 includes an organic core material as known to one of ordinary skill and/or additional dielectric and conductive build-up layers.
To improve adhesion between the TFC laminate 1100 and the substrate 1200, the TFC laminate 1100 and substrate can be joined after roughening the conductive regions 1102 and prior to curing the build-up layer 1203. The conductive region 1102 can be roughened using chemical etching, sputter etching, and/or the like processes. One of ordinary skill appreciates that the fragile nature of the TFC laminate 1100 and its relative alignment to the underlying substrate 1200 can be important considerations with respect to mounting the TFC 1100 onto the substrate 1200.
Next, referring to
Thinning facilitates patterning of upper electrode layer structures 1302 by reducing the amount of conductive material that must be removed. Thinning at this point in the processes may be advantageous because during earlier stages of TFC laminate 1100 fabrication, the thicker conductive film is stronger and less susceptible to physical/chemical damage during formation of the patterned capacitor dielectric and patterned lower electrode structures.
After thinning, the conductive film 702 is patterned with resist and then etched to define the partially formed upper electrode layer structures 1302. Etching can be accomplished using wet or dry etch processes. In one embodiment, the partially formed upper electrode layer structures 1302 are etched using a ferric chloride solution. As can be seen in
Next, shown in
As can be seen in
In addition, because the lower electrode layer 1102 has also been pre-patterned and conductive material removed from regions where via 1404 is to be formed, laser drilling process and/or etch rate and etch uniformity during formation of the via opening can be improved. That is, by removing regions of lower electrode layer 1102 from locations where via 1404 is to be formed, the type of material(s) which must be removed to form the via openings is more consistent from via-to-via across the substrate. This has the potential to reduce the amount of damage to underlying structures by reducing their overall time of exposure to the process that forms the via openings (i.e. overetch time can be reduced). In addition, it can also improve cycle time because obstructions (i.e., the portions of the lower electrode) which can impede the etch or laser ablation process have been removed.
Next, referring to
For the purpose of simplicity of illustration of understanding, the structure of
Embodiments of the present invention are not necessarily limited to only the formation of structures such as 1602, 1604, and 1606. Any number of other interconnect features associated with the formation of build-up layer technology can be accommodated using one or more of the integration schemes disclosed herein. In other words, using one or more of the embodiments disclosed herein, any one of the conductive structures 1602, 1604, 1606 can be incorporated into processes used to form conductive build-up layer interconnects. So for example, in those regions of the TFC laminate corresponding to regions where only conductive build-up layer interconnects and/or vias are to be formed, pre-patterning processes can be used to remove capacitor dielectric and lower electrode layer materials. And then, after the laminate is mounted, portions of conductive film 702 can be cleared away from interconnect and/or via regions during the etch process to form the openings 1304 (
Subsequent processing is considered conventional to one of ordinary skill. So, for example, referring to
In at least one of the embodiments disclosed herein, a TFC laminate's capacitor dielectric and its method of formation are disclosed. The capacitor dielectric is pre-patterned in such a way that makes it less susceptible to damage from etch and/or laser ablation processes used to define the capacitor structure. In an alternative embodiment, a TFC laminate's capacitor electrode and its method of formation are disclosed. The capacitor electrode is pre-patterned in such as way that improves etch/laser ablation uniformity during processes used to form via openings. In an alternative embodiment, the integration of a TFC laminate having pre-patterned capacitor dielectric structures and/or pre-patterned electrode layer structures onto a substrate is disclosed. In an alternative embodiment, the formation of thin film capacitors in build-up layers of a packaging substrate is disclosed
The various embodiments described above have been presented by way of example and not by way of limitation. Thus, for example, while embodiments disclosed herein teach the formation of embedded capacitors in build-up layer of a packaging substrate. Other passive structures, such as for example inductors, resistors, etc., can similarly be formed and/or accommodated using one or more of the embodiments disclosed herin. Also, these passive components can be formed in any number of substrate types that can accommodate the incorporation TFC laminates.
Having thus described in detail embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.