|Publication number||US20060294510 A1|
|Application number||US 11/168,111|
|Publication date||Dec 28, 2006|
|Filing date||Jun 27, 2005|
|Priority date||Jun 27, 2005|
|Also published as||US7594223|
|Publication number||11168111, 168111, US 2006/0294510 A1, US 2006/294510 A1, US 20060294510 A1, US 20060294510A1, US 2006294510 A1, US 2006294510A1, US-A1-20060294510, US-A1-2006294510, US2006/0294510A1, US2006/294510A1, US20060294510 A1, US20060294510A1, US2006294510 A1, US2006294510A1|
|Inventors||Richard Hank, Le-Chun Wu|
|Original Assignee||Hank Richard E, Le-Chun Wu|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (3), Classifications (6), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The base register autoincrement addressing mode is implemented in modern processors and architectures, such as in the Intel Itanium™ family of processors and the HP PA-RISC™ architecture, to reduce the address computation overhead The reduction in overhead is achieved by arranging for a memory access instruction to modify its address register operand (through post-increment addressing mode) so that the modified address register value corresponds to the memory address used by a subsequent memory access instruction. By having the subsequent memory access instruction directly sourcing the post-incremented address register, an ALU (arithmetic logic unit) instruction that would otherwise be employed to set up the address for the memory access instruction is eliminated. Besides reducing resource contention, the base register autoincrement addressing mode has also proved to reduce potential instruction cache misses.
To facilitate discussion,
Notice, however, that instructions 102, 106, and 110 all compute their respective operands from a base register t. By converting instructions 102, 104, 106, 108, 110, and 112 to instructions conforming to the base register autoincrement addressing mode, the number of instructions employed to accomplish the operations specified by the sequence of instructions 102, 104, 106, 108, 110, and 112 is reduced, leading to improved execution efficiency.
Note that instruction 116 accomplishes the same result as instructions 104 and 106 of
Similarly, note that instruction 118 accomplishes the same result as instructions 108 and 110 of
Load instruction 120 also conforms to the base register autoincrement addressing mode. However, since there are no subsequent memory access instructions that employ base register t in the calculation of the address operand, there is no need to autoincrement the value x after loading into register c. To put it another way, instruction 120 autoincrements the value x by zero.
Thus, the six instructions of
The above-discussed optimization may be performed by a human programmer when working with processors and architectures that support the base register autoincrement addressing mode. Such manual optimization is, however, tedious, time-consuming, error-prone, and susceptible to missed optimization opportunities whereby the programmer simply overlooks possible candidate instructions for optimization. In the software engineering process, automated code optimization (i.e., optimization performed by the computer) is therefore desirable. Such automated code optimization employs computer-implemented techniques capable of identifying candidate codes for optimization, as well as computer-implemented techniques for performing the optimization.
The inventors are aware that U.S. Pat. No. 6,151,705 issued to Santhanam on Nov. 21, 2000 (hereinafter “the '705 patent”) discloses techniques for optimizing addressing instructions that occur in loops, e.g., for (i=1; i<8; i++), which memory address instructions specify an address that is a linear function of a loop induction variable (e.g., i). Further details may be obtained by reference to the '705 patent, which is publicly available.
To the inventors' best knowledge, however, there are no prior art techniques for automatically optimizing straight-line, non-inductive code such as those discussed in the example of
The invention relates, in an embodiment, to a computer-implemented method for performing compiler straight-line post-increment (SLPI) optimization for memory access instructions of a computer program. The method includes performing SLPI preparation on candidate memory access instructions to obtain an intermediate stream of code containing pseudo-memory instructions. Each of the candidate memory access instructions represents a non-loop memory access instruction and employs an address that is computed based on the same base register shared by another instruction of the candidate memory access instructions. The computer-implemented method further includes performing SLPI synthesis on the intermediate stream of code to obtain architected memory instructions conforming to a base register auto-incrementing addressing mode.
In another embodiment, the invention relates to an article of manufacture comprising a program storage medium having computer readable code embodied therein, the computer readable code being configured for performing compiler straight-line post-increment (SLPI) optimization for memory access instructions of a computer program. The article of manufacture includes computer readable code for performing SLPI preparation on candidate memory access instructions to obtain an intermediate stream of code containing pseudo-memory instructions, each of the candidate memory access instructions representing a non-loop memory access instruction and employing an address that is computed based on the same base register shared by another instruction of the candidate memory access instructions. The article of manufacture also includes computer readable code for performing SLPI synthesis on the intermediate stream of code to obtain architected memory instructions conforming to a base register auto-incrementing addressing mode.
In yet another embodiment, the invention relates to a compiler configured for optimizing non-loop memory access instructions of a computer program to form architected memory instructions conforming to a base register auto-incrementing addressing mode. The compiler includes code for obtaining an intermediate stream of code containing pseudo-memory instructions from the non-loop memory access instructions. Each of the pseudo-memory instructions sources a different base than a respective base of a respective non-loop memory access instruction of the non-loop memory access instructions. The intermediate stream of code includes at least one place holder instruction preserving a value associated with a base of a first non-loop memory access instruction even after the first non-loop memory instruction is converted to one of the pseudo-memory instructions. The compiler includes code for converting the intermediate stream of code using the intermediate stream of code and the at least one place holder instruction to obtain the architected memory instructions.
These and other features of the present invention will be described in more detail below in the detailed description of the invention and in conjunction with the following figures.
The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
FIGS. 5C1, 5C2, 5C3, and 5C4 show the chains that are created from
The present invention will now be described in detail with reference to a few embodiments thereof as illustrated in the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without some or all of these specific details. In other instances, well known process steps and/or structures have not been described in detail in order to not unnecessarily obscure the present invention.
Various embodiments are described herein below, including methods and techniques. It should be kept in mind that the invention also covers articles of manufacture that includes a computer readable medium on which computer-readable instructions for carrying out embodiments of the inventive technique are stored. The computer readable medium may include, for example, semiconductor, magnetic, opto-magnetic, optical, or other forms of computer readable medium for storing computer readable code. Further, the invention also covers apparatuses for practicing embodiments of the invention. Such apparatus may include circuits, dedicated and/or programmable, to carry out tasks pertaining to embodiments of the invention. Examples of such apparatus include a general purpose computer and/or a dedicated computing device when appropriately programmed and may include a combination of a computer/computing device and dedicated/programmable circuits adapted for the various tasks pertaining to embodiments of the invention. Examples of such apparatus may include appropriate dedicated and/or programmable circuitry in one or more integrated circuits configured to carry out the computer-implemented techniques disclosed herein.
As discussed, embodiments of the invention perform the straight-line post-increment (SLPI) optimization in two steps: a SLPI preparation step and a SLPI synthesis step.
In step 202, scalar optimization is performed. Compiler scalar optimization is well known to those skilled in the art. In step 206, loop optimization, such as that described in the '705 patent, is performed. As discussed, the '705 patent optimizes instructions computing memory addresses that occur in loops when the computed memory address is a linear function of a loop induction variable.
The instruction scheduling phase occur in step 208. Thereafter, register allocation is performed in step 214. Re-scheduling is then performed in step 216. Although the phases of prior art
Thus, in step 302, the address of the memory access instruction under examination is analyzed to determine whether it is in the form of “address=base+n” (where n is some arbitrary value representing, for example, an offset or an index). With reference to
If the address of the straight-line memory access instruction is not in the form of “address=base+n”, optimization is not possible, and the examination of the preparation phase moves on to the next straight-line memory access instruction (step 320). On the other hand, if the address of the straight-line memory access instruction is in the form of “address=base+n”, an inquiry is made in step 304 to ascertain whether the current base has been previously encountered in a previously examined straight-line memory access instruction. In performing step 304, recognizing that a base may be defined in term of other intermediate bases, back substitution may be made for a base until no more back substitution is possible.
With reference to
Algorithmically speaking, back substitution may be performed in an embodiment by first identifying whether the current instruction is in the “add-immediate” form. The “add-immediate” operation is an arithmetic operation that adds a constant to a register. Starting from the instruction that defines the address, if the instruction is an add-immediate instruction (e.g., x=c1+y) and the instruction that defines the register (e.g., y) is also an add-immediate instruction (e.g., y=c2+z), where both c1 and c2 are constants, the substitution involves replacing y with z and adding c2 to c1. Thus, the back-substituted instruction becomes x=c1+c2+z. The process continues until no more substitution is possible. When no more substitution is possible, the “immediate” part of the back-substituted address (e.g., c1+c2) becomes the new offset of the address while the register becomes the base register (e.g., z).
If the base has not been encountered previously, this first occurrence is remembered (step 306) in case another straight-line memory access instruction later references the same base. On the other hand, if this base has already been encountered at least once (as ascertained in step 304), an inquiry is made to ascertain whether a place holder instruction has been inserted into the intermediate stream of code for this base.
As will be made clear later in the examples of
If the place holder instruction has not been inserted for the current base, the value of the old base is copied onto a new base, which copy operation is inserted into the intermediate stream of code as the place holder instruction (310). Furthermore, the first occurrence of the memory instruction that sources this base is converted to a pseudo-memory instruction that has the format of “new_base+displacement”. Thereafter, the process proceeds from step 310 to step 316 wherein the current instruction is converted to the pseudo-memory instruction format. Thereafter, the next instruction is examined (322).
On the other hand, if the place holder instruction has already been inserted for the current base (step 308), the process proceeds to step 316 wherein the current instruction is converted to the pseudo-memory instruction format. Thereafter, the next instruction is examined (322).
Thus, the effect of steps 308 and 310 is to ensure that if the current memory access instruction shares, either directly or indirectly, the same base register as a previously encountered memory access instruction, a place holder instruction is inserted (step 310) into the intermediate stream of code (which contains the pseudo-memory instructions to be forwarded to the SLPI synthesis phase), and the first occurrence of the memory instruction that shares the same base register is converted (step 310) into a pseudo-memory instruction. Once these operations occur, the current memory instruction is then converted into a pseudo-memory instruction. This sequence of steps ensures that unless a second memory instruction that shares the same base register is encountered, the first memory instruction is not converted to a pseudo-memory instruction unnecessarily (since no optimization is possible unless at least two instructions share the same base register).
To illustrate with reference to
The next memory instruction is memory instruction 340 of
The next memory instruction is memory instruction 344 of
The inquiry at step 308 will be a negative (since no place holder instruction for base t has been placed into the intermediate stream of code). Thus, the method proceeds to insert (according to step 310) the place holder instruction “copy u=t” into the intermediate stream of code, where u is the new base for the pseudo-memory instruction and t is the old base. Further, the first occurrence of the memory instruction that references base t, i.e., memory instruction 340 of
Memory instructions 340 and 344 share a base register t, as discussed above. Accordingly, a place holder instruction 352 is inserted into the intermediate stream of code. The first occurrence of the memory instruction that references base t is converted first into a pseudo-memory instruction, resulting in instruction 354 (load the content of the memory location that is referenced by the value u+12 into w). Then memory instruction 344 is converted pseudo-memory instruction 356 (load the content of the memory location that is referenced by the value u+8 into e).
After the preparation phase, SLPI synthesis takes place. In SLPI synthesis, each pseudo-memory instruction is examined and then placed on a list (referred to herein as “post-increment chain”) based on whether any previously examined pseudo-memory instruction that shares the same base register can set up its address through post-increment. It is desirable to create as few chains as possible for all the pseudo-memory instructions since each new chain requires computation overhead in addressing setup.
Once all the pseudo-memory instructions are examined, they are then converted to architected memory instructions (i.e., optimized instructions conforming to instruction specifications for the processor architecture and/or platform) such that each of them would post-increment its address register to set up the address for the subsequent instruction in the chain. The instructions on the same chain would share the same address register after SLPI synthesis is completed. During SLPI synthesis, instructions to initialize the address registers of the chains may be created.
In discussing the SLPI synthesis step, the following definitions are employed. A post-increment chain refers to a list of pseudo-memory instructions that share the same base register. Each instruction on a chain sets up the address for its immediate succeeding instruction through post-increment after synthesis is done. As can be seen in the examples later herein, it is not required that all memory access instructions that share the same base register in a given program belong to a single post-increment chain. A post-increment tree refers to a collection of post-increment chains that share the same final address register. A post-increment chain may be thought of as a degenerate tree, i.e., a chain with no branches. An address calculation that initializes the final address register is performed for each tree. A chain tail refers to the last instruction of a post-increment chain.
SLPI synthesis involves building post-increment chains and transforming the pseudo-memory instructions in the chains to architected memory instructions employing the base register autoincrementing addressing mode. In building post-increment chains, each pseudo-memory instruction is examined to determined whether that memory instruction can 1) mate with an existing chain, or 2) mate with two or more existing chains, or 3) branch out of an existing chain. If no chain can be found to mate with the pseudo-memory instruction under examination and no branching is possible, a new post-increment chain is created. If the newly created chain cannot branch out of an existing chain, a new post-increment tree is then created.
For each pseudo-memory instruction examined, existing post-increment chains with the same base register as the pseudo-memory instruction under examination are analyzed to determine whether any of them can “mate” with the pseudo-memory instruction under examination (step 402).
A post-increment chain is said to be able to “mate” with a given pseudo-memory instruction if the chain tail dominates (i.e., executes before) the memory instruction and the cycle count distance between these two instructions (in the instruction schedule) is greater than the architected latency time specification (as there would be a dependency between the two instructions due to post-incremented address register after transformation). If an existing chain is able to mate with the pseudo-memory instruction being examined, mating occurs (416). If no existing chain can be found to mate with the pseudo-memory instruction under examination, a branch occurs (412), resulting in a post-increment tree, or a new chain is created (418).
However, before a new chain is created, an inquiry is made as to whether there is a post-increment tree in which all chain tails that can reach the pseudo-memory instruction dominate the memory instruction collectively. If there is a post-increment tree in which all chain tails that can reach the pseudo-memory instruction dominate the memory instruction collectively, the pseudo-memory instruction would “mate” with all the reaching chains (404). When a pseudo-memory instruction mates with more than one chain, all but one of the chains would be closed so that they will not be considered for future mating (406). By allowing only one chain to remain open, the potentially troublesome situation wherein the pseudo-memory instruction (now becoming the chain tails of the multiple chains it mated with) mate with two (or more) subsequent instructions that have different offsets is advantageously avoided.
In creating a new chain for the pseudo-memory instruction, efforts are made to ascertain if the new chain can branch out of an existing chain with the same base register (410). The benefit of doing so is that address initialization may be unnecessary for a chain that branches out of an existing chain. When a newly-created chain branches out of an existing chain, both the new chain and the existing chain are in the same post-increment tree, which means the instructions on both chains share the same address register (once SLPI synthesis is completed) and no address initialization instruction is created for the branched chain. On the other hand, if the new chain cannot grow out of an existing chain, a new chain may be created and an additional address calculation instruction is employed.
To determine if branching out of an existing chain is possible, and if so, to identify the branching point, instructions on the chain (except for the tail) are visited in reverse order (i.e., starting from the tail). If an instruction in the chain that is visited satisfies the following conditions: a) it dominates the pseudo-memory instruction, b) it is not post-dominated by its immediate successor on the chain, and c) its immediate successor has the same offset as the pseudo-memory instruction. If all three conditions are satisfied, the new chain is created branching out of this instruction (412).
If no chain can be found to mate with the pseudo-memory instruction under examination and no branching is possible, a new post-increment chain is created (step 418).
Once the post-increment chains are created, the pseudo-memory instructions are transformed into architected memory instructions employing the base register autoincrementing addressing mode with proper post-increment amounts. Except for the chain tails, each pseudo-memory instruction is converted to an architected memory instruction with a post-increment amount that is the difference between its offset and the offset of its immediately succeeding instruction in the chain. The post-increment amount for the chain tail is zero. For each post-increment tree, an address calculation instruction is created to initialize the address register of the first memory instruction in the tree.
As mentioned earlier, in the SLPI preparation phase, a place holder instruction such as the copy instruction is inserted for each base register. The copy instruction is then used in the SLPI synthesis step to initialize the address register for a tree by being converted to an add instruction. The target register of the copy instruction would become the address register for the instructions for the tree.
For example, if the place holder instruction is “a=t”, and the post-increment chain contains the following pseudo-memory instructions: “1d x=8[a]” and “1d y=16[a]” and “1d z=24[a]”, the transformation would result in “add a=t+8” and “1d x=[a], 8”, “1d y=[a], 8” and “1d z=[a]”. The place holder instruction is converted into an add instruction that sets up the address for the next load instruction. Subsequent instructions are in the example architected memory instructions conforming to the base register autoincrementing addressing mode.
However, when there is more than one tree that shares the same base register, only the tree that was processed first gets to use the palace holder instruction. Address calculation instructions may be created to initialize the address registers of other trees. In an embodiment, for a tree in which all of its pseudo memory instructions have the same offset, if the initial address is available in some register and the definition of that register dominates the first memory instruction of the tree, the register may be employed as the address register for the tree without having to create an address initialization instruction. Even though there may be other consumers of this particular register, since all pseudo-memory instructions in the tree have the same offset, no post-increment will happen among these memory instructions and therefore the register value will not be destroyed.
For each chain sharing the same base register as the base register of the pseudo-memory instruction currently being examined, the analysis of steps 504A and 504B are undertaken. In step 504A, an inquiry is made regarding whether the instruction currently at the tail of the chain dominates (executes before) the pseudo-memory instruction currently being examined. If the answer is in the negative, then that chain fails as a candidate chain for mating and the next chain is examined (504D). This is because if the instruction at the tail of the chain can be bypassed during execution, that instruction cannot be relied upon to set up the operand for the address in the instruction currently under examination.
On the other hand, if the instruction currently at the tail of the chain dominates the pseudo-memory instruction currently being examined, a further inquiry is made in step 504B to determine whether the instruction currently at the tail of the chain precedes the pseudo-memory instruction by at least n cycles, whereby n is the minimum number of cycles required for the post-incremented value of the instruction at the tail of the chain to be ready for use as the address operand in the current instruction. This value n is dependent upon processor design and may vary between 1 and any positive integer. If the instruction currently at the tail of the chain does not precede the pseudo-memory instruction by at least n cycles, that chain fails as a candidate chain for mating and the process moves on to the next chain. In an embodiment where the synthesis phase is performed prior to instruction scheduling, the condition of step 504B may not be necessary.
On the other hand, if the instruction currently at the tail of the chain precedes the pseudo-memory instruction by at least n cycles, the instruction is placed at the end of that chain as the new chain tail and the process of substep 504 ends (i.e., the process of examining all chains for possible mating ends).
In step 506, an inquiry is made whether a chain is found for mating. If a chain has been found for mating, the pseudo-memory instruction has been successfully mated with an existing chain and the method proceeds to examine the next pseudo-memory instruction (step 518).
If no chain is found for mating (e.g., there exist no chains that share the same base register or there exist no chains that satisfy both tests of steps 504A and 504B), the process next proceeds to step 508 to ascertain whether there exists a tree (i.e., multiple chains) that collectively dominate the pseudo-memory instruction currently under examination. For example, two chain tails may execute two alternative conditions of an if-then-else statement. Since neither of these chain tails satisfies the test of step 504A, neither can alone satisfies all conditions to allow it to mate with the current instruction. However, since both chain tails cover all alternatives of the if-then-else instruction and dominate the current pseudo-memory instruction in this case, both can mate with the current pseudo-memory instruction.
In this case, one of the chains that collectively dominate the current pseudo-memory instruction is mated (step 510) with the current pseudo-memory instruction, and all other chains that collectively dominate it are closed (i.e., not allowed to mate in the future). In other words, after this mating is completed, only one chain from all the chains that collectively dominate the current pseudo-memory instruction remains open for mating.
If there exists no collection of chains that dominate the pseudo-memory instruction, another inquiry may be made in step 512 to ascertain whether branching is possible. To determine if branching out of an existing chain is possible, and if so, to identify the branching point, instructions on the chain (except for the tail) are visited in reverse order (i.e., starting from the tail). If an instruction of the chain that is visited satisfies the following conditions: a) it dominates the pseudo-memory instruction, b) it is not post-dominated by its immediate successor on the chain, and c) its immediate successor has the same offset as the pseudo-memory instruction. If all three conditions are satisfied, the new chain is created branching out of this instruction (514).
Consider for example a chain having the following four memory access instructions in a chain “1d w=d0[b]”, “1d x=d1[b]”, “1d z=d2[b]”, “1d u=d3[b]”, where d0, d1, d2, and d3 are integers. In examining an pseudo-memory instruction “1d y=d2[b]”, it is noted that by looking at the instructions of the chain in reverse order, the pseudo-memory instruction “1d x=d1[b]” satisfies all conditions: it dominates the current instruction, it is not post-dominated by its immediate successor in the chain “1d z=d2[b]”, and the immediate post successor in the chain “1d z=d2[b] has the same offset as the current instruction (i.e., d2). In this case, the new chain can branch from the existing chain, and instruction “1d x=d1[b]” can post-increment its address registers to set up the address for both instructions “1d y=d2[b]” and “1d z=d2[b]” after SLPI synthesis is completed.
If branching is not possible (per step 512), a new chain is created (step 516).
FIGS. 5C1, 5C2, 5C3, and 5C4 show the chains that are created from
The next pseudo-instruction 542 “1d b=8[u]” is then examined. For this instruction 542, the tests of 504A results in the affirmative since there exists chain 1 sharing the base u, and instruction 540 trivially dominates instruction 542 in the chain of straight-line instructions. Assuming for the purpose of discussing
The test of step 506 results in an affirmative, and the method proceeds to step 518 to examine the next instruction 544 (“1d c=12[u]”). The result after step 518 is shown in
For instruction 544, there exists chain 1 that shares the same base register u. The test of step 504B results in the affirmative (due to the trivial dominating nature of these straight-line instructions). However, the test of step 504B results in a negative since instruction 544 is scheduled to execute in the same cycle as instruction 542 (i.e., the current chain tail), and the processor specification requires that there be at least one cycle that separates these two instructions. Accordingly, chain 1 fails as a candidate for mating, and the method proceeds to examine the next chain (of which there is none).
Since there are no more chains to examine, step 504 is finished and in the next step 506, the test results in a negative response since no chain for mating has been found. Thus, the method proceeds to step 508, wherein the answer is also negative (i.e., there are no multiple chains that collectively dominate the current instruction). Test 512 also fails (i.e., no branching off an existing chain is possible). Accordingly, instruction 544 is placed on a new chain, as shown in
For the next instruction to be examined 546 (“1d=16[u]”), there are two chains that share the base register u and are possible candidate chains for mating with the current instruction. An examination of chain 1 in step 504 yields affirmative responses in both steps 504 a and 504 b. Accordingly, the method proceeds to step 504 c, wherein the current instruction 546 is placed at the end of chain 1. This placement of the current instruction at the end of chain 1 concludes step 504, i.e., the examination of all existing chains that share the same base register for possible mating.
The test of step 506 results in an affirmative, and the method proceeds to step 518 to examine the next instruction (of which there is none in the current example). The result of the chain building process is shown in
Using the example of
The offset of the next instruction 624 to be formed is obtained by taking the displacement of its counterpart pseudo-memory instruction 540 and subtracting that from the displacement of the next pseudo-memory instruction in the chain (i.e., instruction 542). The result is instruction 624. Instructions 626 and 628 are formed similarly.
For chain 2, since there is no place holder but both chains share the same base register u, a new address materialization instruction is employed. The new address materialization instruction initializes the new register ul by adding to t the displacement of the next pseudo-memory instruction in chain 2 (i.e., the offset of instruction 544 or 12). Thus, the result is the address materialization instruction 630. Since there are no instructions in chain 2 after instruction 632, instruction 632 does not post-increment its address.
As can be appreciated from the foregoing, embodiments of the invention automatically generate memory access instructions to post-increment address registers for subsequent memory access instructions without imposing undue constraints on instruction scheduling. Besides reducing the overhead of address computations, this technique also provides a potential reduction in instruction cache misses. Compared to the loop-based solution of the '705 patent, embodiments of the invention are capable of handling general base registers without being limited to handling only memory addresses that are linear functions of loop induction variables. Furthermore, since the '705 patent requires that all potential post-increment candidate dominate the back edge, programs with complex control flows cannot be efficiently handled. Embodiments of the present invention are capable of synthesizing post-increment memory instructions which set up the address for other memory instructions across control flow splits and joint points since the only test required for mating each chain (in addition to the timing-related question of step 504 b) is whether the tail of the chain dominates the pseudo-memory instruction being examined.
Furthermore, embodiments of the invention may also be employed to transform a program to an intermediate representation (IR) that can help the compiler easily determine the address difference of two memory locations accessed. This ability provides for opportunities for further optimization, as can be appreciated by those skilled in the art.
While this invention has been described in terms of several embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and apparatuses of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7493481 *||May 17, 2004||Feb 17, 2009||Netxen, Inc.||Direct hardware processing of internal data structure fields|
|US8387026 *||Dec 24, 2008||Feb 26, 2013||Google Inc.||Compile-time feedback-directed optimizations using estimated edge profiles from hardware-event sampling|
|US20140201449 *||Jan 15, 2013||Jul 17, 2014||Qualcomm Incorporated||Data cache way prediction|
|U.S. Classification||717/151, 717/140|
|Cooperative Classification||G06F8/441, G06F8/443|
|Oct 14, 2005||AS||Assignment|
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HANK, RICHARD E.;WU, LE-CHUN;REEL/FRAME:016890/0084;SIGNING DATES FROM 20050913 TO 20050914
|Jun 15, 2010||CC||Certificate of correction|
|Feb 26, 2013||FPAY||Fee payment|
Year of fee payment: 4