US 20070011592 A1 Abstract A Reed Solomon decoder architecture. The architecture uses a modified version of the error-evaluator polynomial form proposed by Horiguchi, and later improved by Feng. The architecture is an improvement over Feng in that the area of the dominant PDU unit has been significantly reduced, while maintaining nearly the same iteration time, in novel slice circuitry which rotates terms to share a common multiplier and other circuitry. In addition, a novel implementation of storage of the B polynomial and associated overflow flags allows its storage to be minimized and provides equivalent functioning of the Chien search unit using a proprietary dual-multiplier arrangement in place of random multipliers used by Feng.
Claims(2) 1. A decoder for error correcting codes, comprising:
a syndrome calculation circuit; and a polynomial determining unit for calculating polynomials from an output of said syndrome calculation circuit, said polynomials including at least one polynomial that is rotated if said at least one polynomial overflows. 2-18. (canceled)Description 1. Field of the Invention The invention relates to an architecture for a Reed Soloman decoder with improved efficiency. 2. Background Reed Soloman codes are error-correcting codes used to improve the robustness of communication and storage systems. A data stream, consisting of k m-bit symbols, is typically protected against errors by appending r m-bit redundant symbols, so that the concatenated stream of n=k+r m-bit symbols forms a Reed Solomon codeword. Some symbols of the transmitted or stored codeword may be erroneous when recovered, and if the number of erroneous symbols is small enough, they can be found and corrected by a Reed Solomon decoder. In some systems, the recovery circuitry generates a measure of each symbol's reliability as the recovered symbols are produced. If a symbol is regarded as unreliable, an erasure flag is generated to indicate its location to the Reed Solomon decoder. If s flagged and t unflagged erroneous symbols are recovered, a Reed Solomon decoder designed to process these erasure flags is capable of correcting the errors if 2t+s<=r . We refer to such a decoder as an error-and-erasure decoder. In other systems the recovery circuitry does not process erasure flags, and such a decoder is therefore referred to as an error-only decoder. If t erroneous symbols (i.e., t errors) are recovered, an error-only Reed Solomon decoder is capable of correcting the errors if 2t<=r. A typical Reed-Solomon error-correction system utilizes an encoder and decoder. The encoder inputs the k data symbols and appends the r redundant symbols in such a manner that the n symbols of a Reed-Solomon codeword can be regarded a the coefficients of a polynomial of degree n−1, which is a multiple of a generator polynomial of degree r−1. The roots of the generator polynomial are consecutive powers of a so-called primitive element, as it is commonly known in the literature, which is commonly referred to as α. These roots are
A typical decoder architecture consists of three processing units. The first is referred to here as a syndromer, whose purpose is to calculate the so-called syndromes, as they are known in the literature, from the received vector. The syndromes are the coefficients of the Fourier transform of an error vector that the syndromer computes from the received vector. The syndromer typically requires one clock cycle per recovered symbol. The second is referred to here as a polynomial determining unit (PDU), and typically dominates the VLSI area of the decoder. The PDU determines various polynomials from the syndromes, depending upon the algorithm employed, including an error locator polynomial. The third processing unit is referred to here as a Chien searcher, which also typically requires one clock cycle per recovered symbol. The function of the Chien searcher is to find roots of the error locator polynomial, in order to locate the errors. For high throughput, a PDU architecture is desired which can process a Reed Solomon codeword within a number of clock cycles equal to the number of symbols in a codeword, n. Early Reed-Solomon decoders utilized a single centralized Galois Field multiplier as part of a specialized arithmetic logic unit to perform the PDU functions. In this case, the problem of determining the polynomials from the syndromes is proportional in multiplications to the square of t, denoted O(t2), where t is the number of errors to be corrected. However, as the maximum number of errors, tmax, to be corrected has grown, the number of clock cycles to perform the PDU functions in these early implementations has exceeded n. Therefore, the focus today is on PDU architectures which utilize O(t) parallel multipliers and require O(t) clock cycles to determine the polynomials. Berlekamp and Massey described algorithms for decoding Reed Solomon codes by determining certain polynomials. Although these algorithms have been slightly refined over time, they are still generally referred to in the literature as the Berlekamp-Massey algorithm. Typical implementations of the Berlekamp-Massey algorithm use the syndromes to determine an error locator polynomial, Λ(z) , and an error evaluator polynomial, Ω(z). As described by Berlekamp, the calculation of these two polynomials uses two additional scratch polynomials, A(z) and B(z). Each of the polynomials is approximately of degree t. Later, Blahut described a method of determining Λ(z) from the syndromes using only the scratch polynomial B(z). Ω(z) was then determined in an additional step, convolving the syndrome polynomial S(z) with the locator polynomial, i.e., Ω(z) =S(z)·Λ(z). Further, Horiguchi showed that it is not necessary to determine the polynomial Ω(z); the errors can be directly determined from Λ(z) and one of the scratch polynomials used to produce it, B(z). Berlekamp's storage of two polynomials or Blahut's additional convolution can be eliminated to increase efficiency. Feng revised Horiguchi's algorithm to make it more regular and suitable for VLSI implementation. To achieve this, Feng reformulated the algorithm and used a special circuit to calculate a scaling factor, Bp. This was done to prevent an overflow in the scratch polynomial B(z). An advantage of Feng's architecture is that the storage for iterative development of various polynomials is minimized, where the total storage is r m-bit registers used to hold the syndromes, t m-bit registers used to hold iterative solutions for Λ(z), and t m-bit registers used to hold iterative solutions for B(z), for a total of approximately 4tm registers in the polynomial determination unit. A disadvantage of Feng's architecture is that it uses 3t multipliers, and these multipliers dominate the VLSI area of the PDU. Fredrickson described a PDU architecture which used approximately 2t multipliers in a shared fashion for reduced area while retaining approximately the same iteration time as Feng. The overall area and hence efficiency was improved, but the storage requirements for polynomials was larger than in Feng's architecture. In accordance with the principles of the present invention, a decoder for error correcting codes comprises a syndrome calculation circuit. A polynomial determining unit calculates polynomials from an output of the syndrome calculation circuit. The polynomials include at least one polynomial that is rotated if the one polynomial overflows. A correction circuit for a decoder for error correcting codes in accordance with another aspect of the present invention comprises a correction circuit to evaluate an error evaluation polynomial. The correction circuit comprises a first multiplier employed when a scratch polynomial has overflowed, and a second multiplier different from the first multiplier employed when the scratch polynomial has not overflowed. A method of decoding error correcting codes in accordance with yet another aspect of the present invention comprises calculating a plurality of syndromes. A plurality of polynomials are calculated from the calculated plurality of syndromes. At least one of the calculated plurality of polynomials is rotated if the polynomial overflows. A method of correcting errors for decoding error correcting codes in accordance with still another aspect of the present invention comprises calculating an error evaluation polynomial comprising a plurality of coefficients. Each of the plurality of coefficients of the error evaluation polynomial is multiplied by a first factor if each coefficient has overflowed. Each of the plurality of coefficients of the error evaluation polynomial is multiplied by a second factor different from the first factor if each coefficient has not overflowed, whereby the error evaluation polynomial is evaluated. Features and advantages of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings, in which: In accordance with the principles of the present invention, a highly efficient PDU architecture is provided which uses a total of t multipliers in a shared fashion for reduced area while retaining approximately the same iteration time and polynomial storage efficiency of Feng. This is achieved by sharing a single multiplier in each 'slice of the circuit and employing it three times in successive clock cycles. In addition, a proprietary alternative to Feng's scaling factor circuitry is disclosed which incorporates rotation of the scratch polynomial B(z) when B(z) overflows, and employs a modified Chien searcher with specialized dual constant multipliers to multiply by two different factors according to whether or not B(z) has overflowed, to eliminate the determination of the scaling factor Bp. In a preferred embodiment of the invention, the described architecture does not process erasure flags, and is therefore an error-only decoder. If t erroneous symbols (i.e., t errors) are recovered, the disclosed Reed Solomon decoder is capable of correcting the errors if 2t<=r. However, the architecture disclosed here is easily extended to an error-and-erasure decoder with improved efficiency, combining the methods of the disclosed architecture with erasure locator polynomial pre-processing methods that are well-known in the art. The Berlekamp-Massey algorithm, as discussed in the Background of the Invention, for determining polynomials Λ(z) and B(z) from the syndromes is shown as a flowchart here for reference in In In step The result of step The results of step In step The roots of the polynomial Λ(z) yield the error locations in that
A shortcoming of the algorithm as shown in The algorithm of In When Λ(α Feng's circuit implementation is shown in The partial view of Feng's BMA block in The remaining circuitry in Feng's BMA block is shown in A preferred algorithm according to the invention is shown in In In general, at the beginning of an iteration (at the start of step At the start of decoding, the signal init is asserted, which loads registers At the start of iteration step At the start of iteration step Register If m3sel is deasserted, the value of register At the start of iteration step Since m3sel is deasserted, register In this manner, the updated polynomial terms B, A and U have returned to their original positions at the end of the three steps A unique feature of the slice shown in To compare implementations, Feng's circuitry was sliced to contain one term of the equivalent Λ, A, and U and their associated logic. Table 1 compares the efficiency of the slice shown in
Outputs The present invention also eliminates Feng's special circuit for calculating the numerator of the error value expression. To do this, the Applicants make a judicious choice of Ir0 to use the simplified version of the error value expression, i.e., with numerator 1, and handle storage of the B polynomial in a proprietary fashion. The polynomials B(z) and o(z) here are of the special form,
A non-zero coefficient in the polynomial o(z) indicates that the corresponding term of the resulting polynomial B(z) is the result of overflowing the allotted storage. Assuming that at most t errors have occurred, the resulting polynomial Λ(z) is identical to that of In a Chien search unit, the polynomial B(z) is typically evaluated in a circuit as shown on the left hand side of In a preferred embodiment of the invention as shown in While the invention has been described with reference to the exemplary embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention.
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