Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20070013044 A9
Publication typeApplication
Application numberUS 10/451,564
PCT numberPCT/IL2001/001183
Publication dateJan 18, 2007
Filing dateDec 19, 2001
Priority dateFeb 6, 1998
Also published asEP1356718A2, EP1356718A4, US7408249, US20040183185, WO2002051217A2, WO2002051217A3
Publication number10451564, 451564, PCT/2001/1183, PCT/IL/1/001183, PCT/IL/1/01183, PCT/IL/2001/001183, PCT/IL/2001/01183, PCT/IL1/001183, PCT/IL1/01183, PCT/IL1001183, PCT/IL101183, PCT/IL2001/001183, PCT/IL2001/01183, PCT/IL2001001183, PCT/IL200101183, US 2007/0013044 A9, US 2007/013044 A9, US 20070013044 A9, US 20070013044A9, US 2007013044 A9, US 2007013044A9, US-A9-20070013044, US-A9-2007013044, US2007/0013044A9, US2007/013044A9, US20070013044 A9, US20070013044A9, US2007013044 A9, US2007013044A9
InventorsAvner Badihi
Original AssigneeAvner Badihi
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Packaged integrated circuits and methods of producing thereof
US 20070013044 A9
Abstract
A packaged integrated circuit and method for producing thereof, including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
Images(13)
Previous page
Next page
Claims(33)
1. A packaged integrated circuit comprising:
an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane; and
a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface.
2. A packaged integrated circuit according to claim 1 and wherein said package is a chip-scale package.
3. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
4. A packaged integrated circuit according to claim 1 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
5. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
6. A packaged integrated circuit according to claim 2 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
7. A packaged integrated circuit assembly comprising:
a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane and a plurality of electrical contacts, each connected to said electrical circuitry at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and
at least one additional electrical circuit element mounted onto and supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.
8. A packaged integrated circuit assembly according to claim 7 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
9. A packaged integrated circuit according to claim 7 and wherein said package is a chip-scale package.
10. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
11. A packaged integrated circuit according to claim 7 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
12. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
13. A packaged integrated circuit according to claim 9 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
14. A method for producing packaged integrated circuits comprising:
producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry at said substrate plane, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface; and
separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.
15. A method for producing packaged integrated circuits according to claim 14 and wherein said plurality of individual chip packages are chip scale packages.
16. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
17. A method according to claim 14 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
18. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
19. A method according to claim 15 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
20. A method for producing packaged integrated circuit assemblies, the method comprising:
producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;
separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages; and
mounting onto said at second planar surface of at least one of said plurality of individual chip packages, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong.
21. A method of forming a packaged integrated circuit assembly according to claim 20 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
22. A method for producing packaged integrated circuits according to claim 20 and wherein said plurality of individual chip packages are chip scale packages.
23. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
24. A packaged integrated circuit according to claim 20 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
25. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
26. A packaged integrated circuit according to claim 22 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
27. A method for producing packaged integrated circuit assemblies, the method comprising:
producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon;
providing wafer scale packaging enclosing said integrated circuit substrate and defining first and second planar surfaces generally parallel to said substrate plane;
forming on said wafer scale packaging a plurality of electrical contacts, each connected to said electrical circuitry, at least some of said plurality of electrical contacts extending onto said first planar surface and at least some of said plurality of electrical contacts extending onto said second planar surface;
mounting onto said at second planar surface of said wafer scale packaging, at least one additional electrical circuit element, said at least one additional electrical circuit element being supported by said second planar surface and electrically coupled to at least one of said plurality of electrical contacts extending therealong; and
separating said integrated circuit substrate in said wafer scale packaging into a plurality of individual chip packages.
28. A method of forming a packaged integrated circuit assembly according to claim 27 and wherein said at least one additional electrical circuit element comprises an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
29. A method for producing packaged integrated circuits according to claim 27 and wherein said plurality of individual chip packages are chip scale packages.
30. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
31. A packaged integrated circuit according to claim 27 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
32. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to visible radiation.
33. A packaged integrated circuit according to claim 29 and wherein said package includes at least one portion which is at least partially transparent to infra-red radiation.
Description
    FIELD OF THE INVENTION
  • [0001]
    The present invention relates to integrated packaging, packaged integrated circuits and methods of producing packaged integrated circuits.
  • REFERENCE TO CO-PENDING APPLICATIONS
  • [0002]
    Applicants hereby claim priority of Israel Patent Application No. 140,482, filed Dec. 21, 2001, entitled “Packaged Integrated Circuits and Methods of Producing Thereof”, and U.S. patent application Ser. No. 09/758,906 filed Jan. 11, 2001, entitled “Packaged Integrated Circuits and Methods of Producing Thereof”.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Various types of packaged integrated circuits are known in the prior art. The following patents and published patent applications of the present inventor and the references cited therein are believed to represent the state of the art: U.S. Pat. Nos. 4,551,629; 4,764,846; 4,794,092; 4,862,249; 4,984,358; 5,104,820; 5,126,286; 5,266,833; 5,546,654; 5,567,657; 5,612,570; 5,657,206; 5,661,087; 5,675,180; 5,703,400; 5,837,566; 5,849,623; 5,857,858; 5,859,475; 5,869,353; 5,888,884; 5,891,761; 5,900,674; 5,938,45; 5,985,695; 6,002,163; 6,046,410; 6,080,596; 6,092,280; 6,098,278; 6,124,637; 6,134,118. EP 490739 A1; JP 63-166710 WO 85/02283; WO 89/04113; WO 95/19645
  • [0004]
    The disclosures in the following publications:
  • [0005]
    “Three Dimensional Hybrid Wafer Scale Integration Using the GE High Density Interconnect Technology” by R. J. Wojnarowski, R. A. Filliion, B. Gorowitz and R. Sala of General Electric Company, Corporate Research & Development, P.O. Box 8, Schenectady, N.Y. 12301, USA, International Conference on Wafer Scale Integration, 1993.
  • [0006]
    “M-DENSUS”, Dense-Pac Microsystems, Inc., Semiconductor International, December 1997, p. 50;
  • [0007]
    “Introduction to Cubic Memory, Inc.” Cubic Memory Incorporated, 27 Janis Way, Scotts Valley, Calif. 95066, USA;
  • [0008]
    “A Highly Integrated Memory Subsystem for the Smaller Wireless Devices” Intel(r) Stacked-CSP, Intel Corporation, January 2000;
  • [0009]
    “Product Construction Analysis (Stack CSP)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
  • [0010]
    “Four Semiconductor Manufacturers Agree to Unified Specifications for Stacked Chip Scale Packages”, Mitsubishi Semiconductors, Mitsubishi Electronics America, Inc., 1050 East Arques Avenue, Sunnyvale, Calif. 94086, USA;
  • [0011]
    “Assembly & Packaging, John Baliga, Technology News, Semiconductor International, December 1999;
  • [0012]
    “<6 mils Wafer Thickness Solution (DBG Technology)”, Sung-Fei Wang, ASE, R & D Group, Taiwan, 1999;
  • [0013]
    “Memory Modules Increase Density”, DensePac Micro Systems, Garden Grove, Calif., USA, Electronics Packaging and Production, p. 24, Nov. 1994;
  • [0014]
    “First Three-Chip Staked CSP Developed”, Semiconductor International, January 2000, p. 22;
  • [0015]
    “High-Density Packaging: The Next Interconnect Challenge”, Semiconductor International, February 2000, pp. 91-100;
  • [0016]
    “3-D IC Packaging”, Semiconductor International, p. 20, May 1998;
  • [0017]
    “High Density Pixel Detector Module Using Flip Chip and Thin Film Technology” J. Wolf, P. Gerlach, E. Beyne, M. Topper, L. Dietrich, K. H. Becks, N. Wermes, O. Ehrmann and H. Reichl, International System Packaging Symposium, January 1999, San Diego;
  • [0018]
    “Copper Wafer Bonding”, A. Fan, A. Rahman and R. Rief, Electrochemical and Solid State Letters, 2(10), pp. 534-536, 1999;
  • [0019]
    “Front-End 3-D Packaging”, J. Baliga, Semiconductor International, December 1999, p 52, are also believed to represent the state of the art.
  • SUMMARY OF THE INVENTION
  • [0020]
    The present invention seeks to provide improved packaged integrated circuits and methods for producing same.
  • [0021]
    There is thus provided in accordance with a preferred embodiment of the present invention a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface.
  • [0022]
    Further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
  • [0023]
    Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is partially transparent to infra-red radiation.
  • [0024]
    There is also provided in accordance with another preferred embodiment of the present invention a packaged integrated circuit assembly including a packaged integrated circuit including an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, a package enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane and a plurality of electrical contacts, each connected to the electrical circuitry at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and at least one additional electrical circuit element mounted onto and supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
  • [0025]
    Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
  • [0026]
    Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • [0027]
    Still further in accordance with a preferred embodiment of the present invention the package is a chip-scale package.
  • [0028]
    There is further provided in accordance with a preferred embodiment of the present invention a method for producing packaged integrated circuits. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry at the substrate plane, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
  • [0029]
    Further in accordance with a preferred embodiment of the present invention the plurality of individual chip packages are chip scale packages.
  • [0030]
    Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • [0031]
    There is also provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages and mounting onto the at second planar surface of at least one of the plurality of individual chip packages, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong.
  • [0032]
    Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
  • [0033]
    Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • [0034]
    There is further provided in accordance with yet another preferred embodiment of the present invention a method for producing packaged integrated circuit assemblies. The method includes producing, on a wafer scale, an integrated circuit substrate lying in a substrate plane and having electrical circuitry formed thereon, providing wafer scale packaging enclosing the integrated circuit substrate and defining first and second planar surfaces generally parallel to the substrate plane, forming on the wafer scale packaging a plurality of electrical contacts, each connected to the electrical circuitry, at least some of the plurality of electrical contacts extending onto the first planar surface and at least some of the plurality of electrical contacts extending onto the second planar surface, mounting onto the at second planar surface of the wafer scale packaging, at least one additional electrical circuit element, the at least one additional electrical circuit element being supported by the second planar surface and electrically coupled to at least one of the plurality of electrical contacts extending therealong and separating the integrated circuit substrate in the wafer scale packaging into a plurality of individual chip packages.
  • [0035]
    Further in accordance with a preferred embodiment of the present invention the additional electrical circuit element includes an electrical component selected from the group consisting of: passive electrical elements, light generating elements, heat generating elements, light detecting elements, integrated circuits, hybrid circuits, environmental sensors, radiation sensors, micromechanical sensors, mechanical actuators and force sensors.
  • [0036]
    Additionally in accordance with a preferred embodiment of the present invention the package includes at least one portion which is at least partially transparent to visible radiation. Alternatively the package includes at least one portion which is at least partially transparent to infra-red radiation.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0037]
    The present invention will be understood and appreciated more fully from the following detailed description, taken in conjunction with the drawings in which:
  • [0038]
    FIG. 1 is a simplified pictorial illustration of a chip-scale packaged integrated circuit constructed and operative in accordance with a preferred embodiment of the present invention;
  • [0039]
    FIGS. 2A, 2B and 2C are simplified pictorial illustrations of three examples of packaged integrated circuit assemblies constructed and operative in accordance with a preferred embodiment of the present invention;
  • [0040]
    FIGS. 3A and 3B are simplified illustrations of a first series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention;
  • [0041]
    FIGS. 3C, 3D, 3E and 3F, are simplified sectional illustrations of a first series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention;
  • [0042]
    FIG. 4A is a simplified pictorial illustration of an in-production packaged wafer following the stage illustrated in FIG. 3F and following a first grooving stage;
  • [0043]
    FIG. 4B is a simplified pictorial illustration of an in-production packaged wafer following the stages illustrated in FIGS. 3F and 4A and following a second grooving stage;
  • [0044]
    FIGS. 5A, 5B, 5C, 5D and 5E are simplified sectional illustrations taken along lines VI-VI in FIG. 4A of a second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention;
  • [0045]
    FIGS. 6A, 6B, 6C, 6D and 6E are simplified sectional illustrations taken along lines V-V in FIG. 4B of the second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention; and
  • [0046]
    FIGS. 7A and 7B taken together illustrate apparatus and methodologies for producing integrated circuit devices in accordance with a preferred embodiment of the present invention.
  • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • [0047]
    Reference is now made to FIG. 1, which is a simplified pictorial illustration of a chip-scale packaged integrated circuit constructed and operative in accordance with a preferred embodiment of the present invention. FIG. 1 illustrates a preferred embodiment of integrated circuit device constructed and operative in accordance with a preferred embodiment of the present invention and includes a relatively thin and compact, environmentally protected and mechanically strengthened packaged integrated circuit 10, having a multiplicity of electrical contacts plated along edge surfaces and planar surfaces thereof.
  • [0048]
    In contrast with prior art devices, such as those described in applicant's published PCT application WO 95/19645, the packaged integrated circuit shown in FIG. 1 is characterized in that it has electrical contacts 12 extending along a first planar surface 14 thereof and also has electrical contacts 16 extending along an oppositely facing second planar surface 18 thereof This arrangement enables the packaged integrated circuit to be conveniently mounted in a stacked arrangement.
  • [0049]
    As seen in FIG. 1, the packaged integrated circuit 10 includes a plurality of generally planar edge surfaces which extend non-perpendicularly with respect to planar surfaces 14 and 18. These edge surfaces include first and second edge surfaces 20 and 22, each of which intersects the plane of a silicon substrate 24 on which is formed an integrated circuit 26 and extends from a location slightly beyond that plane to planar surface 14.
  • [0050]
    There are also provided third and fourth edge surfaces 30 and 32, each of which intersects the plane of silicon substrate 24 and extends from a location slightly beyond that plane to planar surface 18. There are also provided fifth and sixth edge surfaces 40 and 42, neither of which intersects the plane of silicon substrate 24. Each of edge surfaces 40 and 42 intersects a respective one of surfaces 30 and 32 and extends therefrom to planar surface 14. There are additionally provided seventh and eighth edge surfaces 50 and 52, neither of which intersects the plane of silicon substrate 24. Each of edge surfaces 50 and 52 intersects a respective one of surfaces 20 and 22 and extends therefrom to planar surface 18.
  • [0051]
    It is seen that contacts 12 extend along respective edge surfaces 20 and 22 and onto planar surface 14 and are in electrical contact with edges of pads 60 extending from silicon substrate 24 in the plane thereof It is also seen that contacts 16 extend along respective edge surfaces 30 and 32 and onto planar surface 18 and are in electrical contact with edges of pads 62 extending from silicon substrate 24 in the plane thereof.
  • [0052]
    Reference is now made to FIGS. 2A, 2B and 2C, which are simplified pictorial illustrations of three examples of packaged integrated circuit assemblies constructed and operative in accordance with a preferred embodiment of the present invention.
  • [0053]
    FIG. 2A illustrates a packaged integrated circuit 70 having mounted onto a planar surface 72 thereof, a plurality of other electrical devices, such as integrated circuits 78 and 74. It is seen that, for example, integrated circuit 74 electrically engages a pair of contacts 76 formed on planar surface 72, while integrated circuit 78 electrically engages six contacts 76 formed on planar surface 72.
  • [0054]
    FIG. 2B illustrates a packaged integrated circuit 80 having mounted onto a planar surface 82 thereof, a plurality of other electrical devices, such as four integrated circuits 84. It is seen that, for example, integrated circuits 84 each electrically engage a pair of contacts 86 formed on planar surface 82.
  • [0055]
    FIG. 2C illustrates a pair of packaged integrated circuits 90 and 92 mounted in a stacked arrangement, wherein contacts 94 of integrated circuit 92 are in electrical contact with corresponding contacts 96 of integrated circuit 90. It is appreciated that stacks having more than two integrated circuits of this type may be provided and that the integrated circuits need not be stacked in registration with each other, thus providing branched stacks.
  • [0056]
    Reference is now made to FIGS. 3A, 3B, 3C, 3D, 3E and 3F, which are simplified pictorial and sectional illustrations of a first series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention.
  • [0057]
    In accordance with a preferred embodiment of the present invention, and as illustrated in FIGS. 3A, 3B and 3C a complete silicon wafer 120 having a plurality of finished dies 122 formed thereon by conventional techniques, is bonded at its active surface 124 to a protective insulating cover plate 126 via a layer 128 of epoxy. The insulating cover plate 126 typically comprises glass, quartz, sapphire or any other suitable insulative substrate. FIG. 3A illustrates the initial mutual arrangement of cover plate 126 and wafer 120, FIG. 3B illustrates the final placement and FIG. 3C shows the bonding in a sectional illustration.
  • [0058]
    The cover plate 126 may be opaque or transparent or may be colored or tinted in order to operate as a spectral filter. Alternatively, a dichroic or colored spectral filter may be formed on at least one surface of the cover plate 126.
  • [0059]
    It is appreciated that certain steps in the conventional fabrication of silicon wafer 120 may be eliminated when the wafer is used in accordance with the present invention. These steps include the provision of via openings above pads, wafer back grinding and wafer back metal coating.
  • [0060]
    The complete silicon wafer 120 may be formed with an integral color filter array by conventional lithography techniques at any suitable location therein. Prior to the bonding step of FIGS. 3A, 3B & 3C, a filter may be formed and configured by conventional techniques over the cover plate 126, such that the filter plane lies between cover plate 126 and the epoxy layer 128.
  • [0061]
    Following the bonding step described hereinabove, the silicon wafer 120 is preferably ground down to a decreased thickness, typically 100 microns, as shown in FIG. 3D. This reduction in wafer thickness is enabled by the additional mechanical strength provided by the bonding thereof of the insulating cover plate 126.
  • [0062]
    Following the reduction in thickness of the wafer, which is optional, the wafer is etched, using a photolithography process, along its back surface along predetermined dice lines which separate the individual dies. Etched channels 130 are thus produced, which extend entirely through the thickness of the silicon substrate, typically 100 microns thick. The etched wafer is shown in FIG. 3E.
  • [0063]
    The aforementioned etching typically takes place in conventional silicon etching solution, such as a combination of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water, so as to etch the silicon down to the field oxide layer, as shown in FIG. 3E.
  • [0064]
    The result of the silicon etching is a plurality of separated dies 140, each of which includes silicon of thickness of about 100 microns.
  • [0065]
    As seen in FIG. 3F, following the silicon etching, a second insulating packaging layer 142 is bonded over the dies 140 on the side thereof opposite to insulating packaging layer 126. A layer 144 of epoxy lies between the dies 140 and the layer 142 and epoxy also fills the interstices defined by etched channels 130 between dies 140. In certain applications, the packaging layer 142 and the epoxy layer 144 are both transparent in the relevant spectral wavebands, such as, the visible waveband or the infrared waveband.
  • [0066]
    The sandwich of the etched wafer 120 and the first and second insulating packaging layers 126 and 142 is then partially cut along lines 150, lying along the interstices between adjacent dies 140 to define notches along the outlines of a plurality of pre-packaged integrated circuits. It is noted that lines 150 are selected such that the edges of the dies along the notches are distanced from the outer extent of the silicon 140 by at least a distance d, as shown in FIG. 3F.
  • [0067]
    It is noted that partial cutting of the sandwich of FIG. 3F along lines 150 exposes edges of a multiplicity of pads on the silicon wafer 120, which pad edges, when so exposed, define contact surfaces on dies 140. These contact surfaces are in electrical contact with the contacts, such as contacts 12 or 16 shown in FIG. 1 and are designated in FIG. 1 by reference numerals 60 or 62 respectively.
  • [0068]
    It is a particular feature of the present invention that notches are formed in the sandwich of FIG. 3F in a grid pattern, wherein notches in a first direction are formed inwardly from a first planar surface of the sandwich and cut through the plane of the active surface of silicon substrate 120 and notches in a second direction, orthogonal to the first direction are formed inwardly from a second planar surface of the sandwich, parallel to the first planar surface and opposite thereto, and also cut through the plane of the active surface of silicon substrate 120.
  • [0069]
    FIG. 4A illustrates notching of the sandwich of FIG. 3F, producing notches 180 which extend typically inwardly from substrate 142 and engaging a plane 160 of the active surface of silicon substrate 120. FIG. 4B illustrates notching of the sandwich of FIG. 4A, producing notches 181 inwardly from substrate 126. It is seen that the notches 181 of FIG. 4B extend perpendicularly to notches 180 of FIGS. 4A & 4B and that both notches 180 and 181 pass through plane 160.
  • [0070]
    Reference is now made to FIGS. 5A, 5B, 5C, 5D & 5E which are simplified sectional illustrations taken along lines V-V in FIG. 4A and lines VI-VI in FIG. 4B of a second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention.
  • [0071]
    FIG. 5A is a sectional illustration of the sandwich of FIG. 3F, which illustrates more clearly than in FIG. 3F, the dies 140 and pads 172 extending outwardly thereof in the plane 160 (FIGS. 4A and 4B). The remaining structural elements shown in FIG. 3F are identified by the same reference numerals in FIG. 5A.
  • [0072]
    FIG. 5B shows the notches 180 illustrated in FIG. 4A.
  • [0073]
    FIG. 5C illustrates a preferred cross sectional configuration of a notch 180 produced by partially cutting as described hereinabove in connection with FIG. 4A. Vertical lines 182 indicate the intersection of the notch 180 with the pads 172, defining exposed sectional pad surfaces 62 (FIG. 1). Vertical lines 184 indicate the location of a subsequent final cut which separates the dies into individual integrated circuits at a later stage.
  • [0074]
    FIG. 5D illustrates the formation of metal contacts 16 (FIG. 1) along the edges 30 and 32 and part of the surface 18 (FIG. 1). These contacts, which may be formed by any suitable metal deposition technique, are seen to extend inside notch 180, thus establishing electrical contact with surfaces 62 of pads 172.
  • [0075]
    It is noted that metal contacts are formed onto the dies in electrical contact with surfaces 62 of pads 172 without first separating the dies into individual chips.
  • [0076]
    FIG. 5E illustrates subsequent dicing of the individual dies on the wafer, along the lines 184, subsequent to metal contact formation thereon, into individual pre-packaged integrated circuit devices.
  • [0077]
    Reference is now made to FIGS. 6A, 6B, 6C, 6D and 6E, which are simplified sectional illustrations taken along lines V-V in FIG. 4B of the second series of stages in the production of chip-scale packaged integrated circuits in accordance with a preferred embodiment of the present invention.
  • [0078]
    FIG. 6A is a sectional illustration of the sandwich of FIG. 3F, which illustrates more clearly than in FIG. 3F, the dies 140 and the pads 272 extending outwardly thereof in the plane 160 (FIGS. 4A and 4B) in directions perpendicular to the directions along which extend pads 172. The remaining structural elements shown in FIG. 3F are identified by the same reference numerals in FIG. 6A.
  • [0079]
    FIG. 6B shows the notches 181 illustrated in FIG. 4B.
  • [0080]
    FIG. 6C illustrates a preferred cross sectional configuration of a notch 181 produced by partially cutting as described hereinabove in connection with FIG. 4B. Vertical lines 282 indicate the intersection of the notch 181 with pads 272, defining exposed sectional pad surfaces 60 (FIG. 1). Vertical lines 284 indicate the location of a subsequent final cut which separates the dies into individual integrated circuits at a later stage.
  • [0081]
    FIG. 6D illustrates the formation of metal contacts 12 (FIG. 1) along the edges 20 and 22 and part of the surface 14 (FIG. 1). These contacts, which may be formed by any suitable metal deposition technique, are seen to extend inside notch 181, thus establishing electrical contact with surfaces 60 of pads 272.
  • [0082]
    It is noted that metal contacts are formed onto the dies in electrical contact with surfaces 60 of pads 272 without first separating the dies into individual chips.
  • [0083]
    FIG. 6E illustrates subsequent dicing of the individual dies on the wafer, subsequent to metal contact formation thereon, into individual pre-packaged integrated circuit devices.
  • [0084]
    Reference is now made to FIGS. 7A and 7B, which together illustrate apparatus and methodologies for producing integrated circuit devices in accordance with a preferred embodiment of the present invention. A conventional wafer fabrication facility 380 provides complete wafers 120 (FIG. 3A). Individual wafers 120 are bonded on their active surfaces to protective layers, such as glass layers 126 (FIG. 3A), using epoxy 128 (FIG. 3C), by bonding apparatus 382, preferably having facilities for rotation of the wafer 120, the layer 126 and the epoxy 128 so as to obtain even distribution of the epoxy.
  • [0085]
    The bonded wafer 121 (FIG. 3C) is thinned (FIG. 3D) at its non-active surface as by grinding apparatus 384, such as Model 32BTGW using 12.5A abrasive, which is commercially available from Speedfam Machines Co. Ltd. of England.
  • [0086]
    The wafer 121 is then etched at its non-active surface, preferably by photolithography, such as by using conventional spin-coated photoresist, which is commercially available from Hoechst, under the brand designation AZ 4562.
  • [0087]
    The photoresist is preferably mask exposed by a suitable UV exposure system 385, such as a Karl Suss Model KSMA6, through a lithography mask 386 to define etched channels 130 (FIG. 3E).
  • [0088]
    The photoresist is then developed in a development bath (not shown), baked and then etched in a silicon etch solution 388 located in a temperature controlled bath 390. Commercially available equipment for this purpose include a Chemkleen bath and an WHRV circulator both of which are manufactured by Wafab Inc. of the U.S.A.. A suitable conventional silicon etching solution is Isoform Silicon etch, which is commercially available from Micro-Image Technology Ltd. of England. The wafer is conventionally rinsed after etching. The resulting etched wafer is shown in FIG. 3E.
  • [0089]
    Alternatively, the foregoing wet chemical etching step may be replaced by dry plasma etching.
  • [0090]
    The etched wafer is bonded on the non-active side to another protective layer. 142 by bonding apparatus 392, which may be essentially the same as apparatus 382, to produce a doubly bonded wafer sandwich 393 as shown in FIG. 3F.
  • [0091]
    Notching apparatus 394 initially partially cuts the bonded wafer sandwich 393 of FIG. 3F inwardly from layer 142 to a configuration shown in FIG. 4A including notches 180 (FIG. 4A).
  • [0092]
    Notching apparatus 394 thereafter partially cuts the bonded wafer sandwich 393 of FIG. 3F inwardly from layer 126 to a configuration shown in FIG. 4B including notches 180 and 181 (FIG. 4B) and cuts the bonded wafer sandwich 393 of FIG. 3F inwardly from layer 142 a configuration shown in FIG. 4B including notches 180 and 181 (FIG. 4B), extending mutually non-collinear and normally mutually perpendicular to each other.
  • [0093]
    The notched wafer 393 is then subjected to anti-corrosion treatment in a bath 396, containing a chromating solution 398, such as described in any of the following U.S. Pat. Nos. 2,507,956; 2,851,385 and 2,796,370, the disclosure of which is hereby incorporated by reference.
  • [0094]
    Conductive layer deposition apparatus 400, which operates by vacuum deposition techniques, such as a Model 903M sputtering machine manufactured by Material Research Corporation of the U.S.A., is employed to produce a conductive layer initially on surfaces 30, 32 and 18 of each die of the wafer as shown in FIG. 1 and thereafter on surfaces 20, 22 and 14 of each die of the wafer as shown in FIG. 1.
  • [0095]
    Configuration of contact strips 12 and 16 as shown in FIG. 1, is carried out preferably by using conventional electro-deposited photoresist, which is commercially available from DuPont under the brand name Primecoat or from Shipley, under the brand name Eagle. The photoresist is applied to the wafers in a photoresist bath assembly 402 which is commercially available from DuPont or Shipley.
  • [0096]
    The photoresist is preferably light configured by a UV exposure system 404, which may be identical to system 385, using masks 405 and 406 to define suitable etching patterns. The photoresist is then developed in a development bath 407, and then etched in a metal etch solution 408 located in an etching bath 410, thus providing a conductor configuration such as that shown in FIG. 1.
  • [0097]
    The exposed conductive strips 12 and 16 shown in FIG. 1 are then plated, preferably by electroless plating apparatus 412, which is commercially available from Okuno of Japan.
  • [0098]
    The wafer is then diced into individual pre-packaged integrated circuit devices. Preferably the dicing blade 414 is a diamond resinoid blade of thickness 4-12 mils. The resulting dies appear as illustrated generally in FIG. 1.
  • [0099]
    It will be appreciated by persons skilled in the art that the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove as well as variations and modifications which would occur to persons skilled in the art upon reading the specification and which are not in the prior art.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US2507956 *Nov 1, 1947May 16, 1950Lithographic Technical FoundatProcess of coating aluminum
US2796370 *Mar 4, 1955Jun 18, 1957Ostrander Charles WComposition and method for producing corrosion resistant protective coating on aluminum and aluminum alloys
US2851385 *Apr 3, 1952Sep 9, 1958Amchem ProdProcess and composition for coating aluminum surfaces
US3971065 *Mar 5, 1975Jul 20, 1976Eastman Kodak CompanyColor imaging array
US3981023 *Sep 16, 1974Sep 14, 1976Northern Electric Company LimitedIntegral lens light emitting diode
US4259679 *Apr 13, 1979Mar 31, 1981Plessey Handel Und Investments A.G.Display devices
US4279690 *Sep 19, 1977Jul 21, 1981Texas Instruments IncorporatedHigh-radiance emitters with integral microlens
US4339689 *Jan 21, 1980Jul 13, 1982Matsushita Electric Industrial Co., Ltd.Light emitting diode and method of making the same
US4551629 *Jan 23, 1984Nov 5, 1985Irvine Sensors CorporationDetector array module-structure and fabrication
US4764846 *Jan 5, 1987Aug 16, 1988Irvine Sensors CorporationHigh density electronic package comprising stacked sub-modules
US4794092 *Nov 18, 1987Dec 27, 1988Grumman Aerospace CorporationSingle wafer moated process
US4797179 *Jun 9, 1987Jan 10, 1989Lytel CorporationFabrication of integral lenses on LED devices
US4862249 *Apr 17, 1987Aug 29, 1989Xoc Devices, Inc.Packaging system for stacking integrated circuits
US4933601 *Dec 9, 1988Jun 12, 1990Hitachi Cable LimitedLight emitting diode array chip and method of fabricating same
US4984358 *Jun 18, 1990Jan 15, 1991Microelectronics And Computer Technology CorporationMethod of assembling stacks of integrated circuit dies
US5037779 *May 16, 1990Aug 6, 1991Whalley Peter DMethod of encapsulating a sensor device using capillary action and the device so encapsulated
US5104820 *Jun 24, 1991Apr 14, 1992Irvine Sensors CorporationMethod of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting
US5118924 *Oct 1, 1990Jun 2, 1992Eastman Kodak CompanyStatic control overlayers on opto-electronic devices
US5124543 *Aug 8, 1990Jun 23, 1992Ricoh Company, Ltd.Light emitting element, image sensor and light receiving element with linearly varying waveguide index
US5126286 *Oct 5, 1990Jun 30, 1992Micron Technology, Inc.Method of manufacturing edge connected semiconductor die
US5177753 *Jun 14, 1991Jan 5, 1993Rohm Co., Ltd.Semi-conductor laser unit
US5250462 *Aug 26, 1991Oct 5, 1993Nec CorporationMethod for fabricating an optical semiconductor device
US5266501 *May 6, 1992Nov 30, 1993Kabushiki Kaisha ToshibaMethod for manufacturing a solid state image sensing device using transparent thermosetting resin layers
US5266833 *Mar 30, 1992Nov 30, 1993Capps David FIntegrated circuit bus structure
US5321303 *Apr 17, 1992Jun 14, 1994Seiko Instruments Inc.Semiconductor device having linearly arranged semiconductor chips
US5455386 *Jan 14, 1994Oct 3, 1995Olin CorporationChamfered electronic package component
US5455455 *Sep 14, 1992Oct 3, 1995Badehi; PeirreMethods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US5500540 *Apr 15, 1994Mar 19, 1996Photonics Research IncorporatedWafer scale optoelectronic package
US5526449 *Jul 14, 1994Jun 11, 1996Massachusetts Institute Of TechnologyOptoelectronic integrated circuits and method of fabricating and reducing losses using same
US5546654 *Aug 29, 1994Aug 20, 1996General Electric CompanyVacuum fixture and method for fabricating electronic assemblies
US5567657 *Dec 4, 1995Oct 22, 1996General Electric CompanyFabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5595930 *Jul 26, 1995Jan 21, 1997Lg Semicon Co., Ltd.Method of manufacturing CCD image sensor by use of recesses
US5612570 *Apr 13, 1995Mar 18, 1997Dense-Pac Microsystems, Inc.Chip stack and method of making same
US5657206 *Jan 19, 1995Aug 12, 1997Cubic Memory, Inc.Conductive epoxy flip-chip package and method
US5661087 *Jun 7, 1995Aug 26, 1997Cubic Memory, Inc.Vertical interconnect process for silicon segments
US5672519 *Jun 6, 1995Sep 30, 1997Lg Semicon Co., Ltd.Method of fabricating solid state image sensing elements
US5675180 *Jun 23, 1994Oct 7, 1997Cubic Memory, Inc.Vertical interconnect process for silicon segments
US5677200 *May 17, 1995Oct 14, 1997Lg Semicond Co., Ltd.Color charge-coupled device and method of manufacturing the same
US5703400 *Jul 22, 1996Dec 30, 1997General Electric CompanyFabrication and structures of two-sided molded circuit modules with flexible interconnect layers
US5814894 *Apr 4, 1996Sep 29, 1998Nitto Denko CorporationSemiconductor device, production method thereof, and tape carrier for semiconductor device used for producing the semiconductor device
US5817541 *Mar 20, 1997Oct 6, 1998Raytheon CompanyMethods of fabricating an HDMI decal chip scale package
US5837566 *Apr 24, 1997Nov 17, 1998Cubic Memory, Inc.Vertical interconnect process for silicon segments
US5849623 *May 23, 1997Dec 15, 1998General Electric CompanyMethod of forming thin film resistors on organic surfaces
US5857858 *Dec 23, 1996Jan 12, 1999General Electric CompanyDemountable and repairable low pitch interconnect for stacked multichip modules
US5859475 *Apr 24, 1996Jan 12, 1999Amkor Technology, Inc.Carrier strip and molded flex circuit ball grid array
US5869353 *Nov 17, 1997Feb 9, 1999Dense-Pac Microsystems, Inc.Modular panel stacking process
US5888884 *Jan 2, 1998Mar 30, 1999General Electric CompanyElectronic device pad relocation, precision placement, and packaging in arrays
US5891761 *Aug 22, 1997Apr 6, 1999Cubic Memory, Inc.Method for forming vertical interconnect process for silicon segments with thermally conductive epoxy preform
US5900674 *Dec 23, 1996May 4, 1999General Electric CompanyInterface structures for electronic devices
US5909052 *May 24, 1995Jun 1, 1999Hitachi, Ltd.Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane
US5938452 *Sep 2, 1997Aug 17, 1999General Electric CompanyFlexible interface structures for electronic devices
US5952712 *Jul 16, 1997Sep 14, 1999Nec CorporationPackaged semiconductor device and method of manufacturing the same
US5965933 *May 28, 1996Oct 12, 1999Young; William R.Semiconductor packaging apparatus
US5985695 *Aug 28, 1998Nov 16, 1999Amkor Technology, Inc.Method of making a molded flex circuit ball grid array
US5986746 *Mar 26, 1997Nov 16, 1999Imedge Technology Inc.Topographical object detection system
US5993981 *Apr 18, 1997Nov 30, 1999Raytheon CompanyBroadband protective optical window coating
US6002163 *Dec 21, 1998Dec 14, 1999General Electric CompanyElectronic device pad relocation, precision placement, and packaging in arrays
US6020217 *Feb 20, 1998Feb 1, 2000Daimler-Benz AktiengesellschaftSemiconductor devices with CSP packages and method for making them
US6046410 *Aug 24, 1998Apr 4, 2000General Electric CompanyInterface structures for electronic devices
US6072236 *Mar 7, 1996Jun 6, 2000Micron Technology, Inc.Micromachined chip scale package
US6080596 *Aug 22, 1997Jun 27, 2000Cubic Memory Inc.Method for forming vertical interconnect process for silicon segments with dielectric isolation
US6083766 *Sep 20, 1999Jul 4, 2000Viking Tech CorporationPackaging method of thin film passive components on silicon chip
US6087586 *Apr 7, 1998Jul 11, 2000Caesar Technology, Inc.Chip scale package
US6092280 *May 26, 1999Jul 25, 2000General Electric Co.Flexible interface structures for electronic devices
US6098278 *Aug 22, 1997Aug 8, 2000Cubic Memory, Inc.Method for forming conductive epoxy flip-chip on chip
US6106735 *Jan 12, 1998Aug 22, 2000Robert Bosch GmbhWafer stack and method of producing sensors
US6124637 *Sep 25, 1998Sep 26, 2000Amkor Technology, Inc.Carrier strip and molded flex circuit ball grid array and method of making
US6134118 *Apr 3, 1997Oct 17, 2000Cubic Memory Inc.Conductive epoxy flip-chip package and method
US6235141 *Jan 8, 1999May 22, 2001Digital Optics CorporationMethod of mass producing and packaging integrated optical subsystems
US6265763 *Mar 14, 2000Jul 24, 2001Siliconware Precision Industries Co., Ltd.Multi-chip integrated circuit package structure for central pad chip
US6307261 *May 26, 1993Oct 23, 2001Thomson CsfMethod for the manufacturing of a semiconductor device which comprises at least one chip and corresponding device
US6329708 *Mar 28, 2000Dec 11, 2001Oki Electric Industry Co. Ltd.Micro ball grid array semiconductor device and semiconductor module
US6548911 *Aug 3, 2001Apr 15, 2003Siliconware Precision Industries Co., Ltd.Multimedia chip package
US6590291 *Jan 25, 2001Jul 8, 2003Shinko Electric Industries Co., Ltd.Semiconductor device and manufacturing method therefor
US6624505 *Jan 11, 2001Sep 23, 2003Shellcase, Ltd.Packaged integrated circuits and methods of producing thereof
US6646289 *Feb 3, 1999Nov 11, 2003Shellcase Ltd.Integrated circuit device
US6768190 *Apr 23, 2002Jul 27, 2004Advanced Semiconductor Engineering, Inc.Stack type flip-chip package
US6891256 *Oct 15, 2002May 10, 2005Fairchild Semiconductor CorporationThin, thermally enhanced flip chip in a leaded molded package
US6977431 *Nov 5, 2003Dec 20, 2005Amkor Technology, Inc.Stackable semiconductor package and manufacturing method thereof
US7033664 *Oct 22, 2002Apr 25, 2006Tessera Technologies Hungary KftMethods for producing packaged integrated circuit devices and packaged integrated circuit devices produced thereby
US20050074954 *Oct 7, 2003Apr 7, 2005Hideo YamanakaMethod and apparatus for producing ultra-thin semiconductor chip and method and apparatus for producing ultra-thin back-illuminated solid-state image pickup device
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7781240 *Oct 26, 2006Aug 24, 2010Tessera Technologies Hungary Kft.Integrated circuit device
US8592831Oct 26, 2006Nov 26, 2013Invensas Corp.Integrated circuit device
US9530945Nov 25, 2013Dec 27, 2016Invensas CorporationIntegrated circuit device
US20070042562 *Oct 26, 2006Feb 22, 2007Tessera Technologies Hungary Kft.Integrated circuit device
Legal Events
DateCodeEventDescription
May 3, 2004ASAssignment
Owner name: SHELLCASE LTD., ISRAEL
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:BADIHI, AVNER;REEL/FRAME:016040/0729
Effective date: 20040328
Apr 27, 2006ASAssignment
Owner name: TESSERA TECHNOLOGIES HUNGARY KFT., HUNGARY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHELLCASE LTD., ALSO SOMETIMES KNOWN AS SHELLCASE, LTD.;REEL/FRAME:017552/0170
Effective date: 20060330
Oct 27, 2009CCCertificate of correction
Dec 17, 2010ASAssignment
Owner name: TESSERA TECHNOLOGIES IRELAND LIMITED, IRELAND
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TESSERA TECHNOLOGIES HUNGARY HOLDING LIMITED LIABILITY COMPANY;REEL/FRAME:025592/0734
Effective date: 20101119
Aug 11, 2011ASAssignment
Owner name: DIGITALOPTICS CORPORATION EUROPE LIMITED, CALIFOR
Free format text: CHANGE OF NAME;ASSIGNOR:TESSERA TECHNOLOGIES IRELAND LIMITED;REEL/FRAME:026739/0875
Effective date: 20110713
Oct 26, 2011ASAssignment
Owner name: DIGITALOPTICS CORPORATION EUROPE LIMITED, IRELAND
Free format text: CORRECTION TO REEL 026739 FRAME 0875 TO CORRECTION THE ADDRESS OF RECEIVING PARTY;ASSIGNOR:TESSERA TECHNOLOGIES IRELAND LIMITED;REEL/FRAME:027137/0397
Effective date: 20110713
Feb 2, 2012FPAYFee payment
Year of fee payment: 4
Mar 20, 2013ASAssignment
Owner name: INVENSAS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DIGITAL OPTICS CORPORATION EUROPE LIMITED;REEL/FRAME:030065/0817
Effective date: 20130318
Owner name: INVENSAS CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DIGITALOPTICS CORPORATION EUROPE LIMITED;REEL/FRAME:030065/0817
Effective date: 20130318
Feb 5, 2016FPAYFee payment
Year of fee payment: 8
Dec 2, 2016ASAssignment
Owner name: ROYAL BANK OF CANADA, AS COLLATERAL AGENT, CANADA
Free format text: SECURITY INTEREST;ASSIGNORS:INVENSAS CORPORATION;TESSERA, INC.;TESSERA ADVANCED TECHNOLOGIES, INC.;AND OTHERS;REEL/FRAME:040797/0001
Effective date: 20161201