|Publication number||US20070014154 A1|
|Application number||US 11/179,570|
|Publication date||Jan 18, 2007|
|Filing date||Jul 13, 2005|
|Priority date||Jul 16, 2004|
|Also published as||US7154765|
|Publication number||11179570, 179570, US 2007/0014154 A1, US 2007/014154 A1, US 20070014154 A1, US 20070014154A1, US 2007014154 A1, US 2007014154A1, US-A1-20070014154, US-A1-2007014154, US2007/0014154A1, US2007/014154A1, US20070014154 A1, US20070014154A1, US2007014154 A1, US2007014154A1|
|Original Assignee||Hsu-Shun Chen|
|Export Citation||BiBTeX, EndNote, RefMan|
|Classifications (9), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention is related generally to a read-only memory (ROM) and more particularly to a flat-cell ROM.
Recently, ROM has almost become requisite part in electronic products.
To increase the memory density, there have been proposed various approaches to reduce the ROM area, for example in the flat-cell ROM disclosed in U.S. Pat. No. 5,117,389 to Yiu, less block select transistors is proposed to increase the memory density. As shown in
One object of the present invention is to provide a smaller area flat-cell ROM.
Another object of the present invention is to provide a flat-cell ROM using a common row of contacts shared by two memory banks.
In a flat-cell ROM including a plurality of memory banks, according to the present invention, each of the memory banks comprises a memory array, a plurality of bit lines, a plurality of virtual ground lines, three select lines, and a common row of contacts shared with an adjacent memory bank. In the flat-cell ROM, each of the bit lines is capable of being connected to the memory array through a first and a second switches, each of the virtual ground lines is capable of being connected to the memory array through a third and a fourth switches, the common row of contacts are used for connecting the bit lines and virtual ground lines to bit signal lines and virtual ground lines, respectively, and the select lines are used for selecting a memory bank, switching the first and second switches, and switching the third and fourth switches, respectively. In a flat-cell ROM according to the present invention, two adjacent memory banks share a common row of contacts, and thus the number of rows of contacts is reduced, thereby decreasing the ROM area.
These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:
By sharing a common row of contacts by two adjacent memory banks in a flat-cell ROM, the ROM area is reduced.
While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set fourth in the appended claims.
|U.S. Classification||365/185.16, 257/E27.102|
|International Classification||G11C16/04, G11C16/08, H01L27/112|
|Cooperative Classification||H01L27/112, G11C16/0491|
|European Classification||H01L27/112, G11C16/04V|
|Jul 22, 2005||AS||Assignment|
Owner name: ELAN MICROELECTRONICS CORPORATION, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, HSU-SHUN;REEL/FRAME:016562/0793
Effective date: 20050610
|Jun 14, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Mar 21, 2014||FPAY||Fee payment|
Year of fee payment: 8
|Apr 21, 2014||SULP||Surcharge for late payment|