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Publication numberUS20070023857 A1
Publication typeApplication
Application numberUS 11/193,952
Publication dateFeb 1, 2007
Filing dateJul 29, 2005
Priority dateJul 29, 2005
Also published asUS7754516, US8067260, US20090142927
Publication number11193952, 193952, US 2007/0023857 A1, US 2007/023857 A1, US 20070023857 A1, US 20070023857A1, US 2007023857 A1, US 2007023857A1, US-A1-20070023857, US-A1-2007023857, US2007/0023857A1, US2007/023857A1, US20070023857 A1, US20070023857A1, US2007023857 A1, US2007023857A1
InventorsMing Jin, Ilya Karpov, Jinwook Lee, Narahari Ramanuja
Original AssigneeMing Jin, Karpov Ilya V, Jinwook Lee, Narahari Ramanuja
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Fabricating sub-lithographic contacts
US 20070023857 A1
Abstract
A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to provide reduced critical dimension elements.
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Claims(27)
1. A method comprising:
forming a first sidewall spacer within a pore; and
forming a second sidewall spacer within said pore over the first sidewall spacer.
2. The method of claim 1 including anisotropically etching a spacer material to form said first sidewall spacer.
3. The method of claim 2 including forming a bread loaf portion in said spacer material and reducing the extent of said bread loaf portion by etching.
4. The method of claim 1 including forming said first sidewall spacer of nitride.
5. The method of claim 1 including forming said second sidewall spacer by depositing a second material over said first sidewall spacer and anisotropically etching said second material.
6. The method of claim 5 including forming a bread loaf portion on said second material and etching to reduce the extent of said bread loaf portion.
7. The method of claim 1 including anisotropically etching to form said first sidewall spacer before forming said second sidewall spacer.
8. The method of claim 1 including forming a heater in said pore after forming said first and second sidewall spacers and forming a chalcogenide layer over said heater.
9. The method of claim 1 including forming said pore with a sub-lithographic dimension after forming said first and second sidewall spacers.
10. The method of claim 9 including forming said pore with a dimension of about 60 nanometers or less.
11. A semiconductor structure comprising:
an insulating layer;
a pore formed in said insulating layer; and
a pair of sidewall spacers formed on top of one another within said pore.
12. The structure of claim 11 wherein said sidewall spacers are separated by a sub-lithographic distance.
13. The structure of claim 12 wherein said distance is about 60 nanometers or less.
14. The structure of claim 11 including a heater in said pore and a chalcogenide layer over said heater.
15. The structure of claim 11 including a conductor under said pore, and said pore is open through said sidewall spacers down to said conductor.
16. A method comprising:
forming a first and second sidewall spacer one over the other within a pore;
forming a heater within said pore; and
forming a chalcogenide layer over said heater.
17. The method of claim 16 including forming the first sidewall spacer within said pore by anisotropically etching a first spacer material.
18. The method of claim 17 including forming a bread loaf portion in said first spacer material and reducing the extent of said bread loaf portion by etching.
19. The method of claim 18 including depositing a second spacer material to form said second sidewall spacer, said second spacer material including a bread loaf portion and etching to reduce the extent of said bread loaf portion.
20. A phase change memory comprising:
an insulating layer;
a pore formed in said insulating layer;
a first and second sidewall spacer formed on top of one another within said pore;
a heater formed within said pore; and
a chalcogenide material over said heater.
21. The memory of claim 20 wherein said pore opening is reduced to a sub-lithographic dimension by said spacers.
22. The memory of claim 21 wherein said pore is reduced to 60 nanometers or less by said spacers.
23. The memory of claim 20 including a conductor, under said insulating layer, said heater electrically coupled to said conductor.
24. A system comprising:
a controller;
a battery coupled to said controller; and
a memory coupled to said controller, said memory including an insulating layer, a pore formed in said insulating layer, first and second sidewall spacers formed within said pore, a heater formed within said pore, and a chalcogenide material over said heater.
25. The system of claim 24 wherein said heater has a dimension that is sub-lithographic.
26. The system of claim 25 wherein said heater has a dimension less than 60 nanometers.
27. The system of claim 26 wherein the width of said heater is less than or equal to 60 nanometers.
Description
    BACKGROUND
  • [0001]
    This invention relates generally to semiconductor technologies and to semiconductor manufacturing processes.
  • [0002]
    In a number of applications, it is desirable to manufacture relatively small contacts. These contacts may be formed within vias or within pores.
  • [0003]
    For example, in connection with phase change memories, it may be desirable to form a pore into which a contact is formed. Over the contact may be defined a heater which resides within the pore. The heater is then covered by a phase change material so that the heater is capable, when passing electrical current, to heat the chalcogenide and to cause it to change phase. These different phases may be associated with different measurable resistivities. As a result, a phase change memory may be formed. Since it is desirable to reduce the programming current, it may also be desirable to reduce the size of the heater.
  • [0004]
    In a number of instances, making relatively small critical dimension parts is limited by the dimensions achievable with lithographic techniques. Today, lithographic techniques limit feature size to about 180 nanometers.
  • [0005]
    Thus, it would be desirable to form features that are smaller than 180 nanometers.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0006]
    FIG. 1 is an enlarged, cross-sectional view at an early stage of manufacture of one embodiment of the present invention;
  • [0007]
    FIG. 2 is an enlarged, cross-sectional view of the embodiment of FIG. 1 at subsequent stage of manufacture;
  • [0008]
    FIG. 3 is an enlarged, cross-sectional view of the embodiment shown in FIG. 2 at a subsequent stage of manufacture in accordance with one embodiment of the present invention;
  • [0009]
    FIG. 4 is an enlarged, cross-sectional view of the embodiment shown in FIG. 3 after further processing in accordance with one embodiment of the present invention;
  • [0010]
    FIG. 5 is an enlarged, cross-sectional view of the embodiment of FIG. 4 after additional processing in accordance with one embodiment of the present invention;
  • [0011]
    FIG. 6 is an enlarged, cross-sectional view of the finished device in accordance with one embodiment of the present invention; and
  • [0012]
    FIG. 7 is a system depiction of one embodiment of the present invention.
  • DETAILED DESCRIPTION
  • [0013]
    In order to overcome the limits of lithographic processes, a spacer technology may be utilized. In a spacer technology, a pore may be formed within an insulator and sidewall spacers formed on the sidewalls of that pore. As a result, the sidewall spacers enable the pore size to be reduced to a sub-lithographic dimension. However, there is a limit to how small the pore may be formed in some cases because of what is called bread loafing. Bread loafing occurs when the opposed upper edges of the deposited sidewall spacer forming material becomes enlarged, extends into the pore and eventually closes off the pore and cuts off access to the interior of the pore.
  • [0014]
    In order to make a critical dimension smaller than that possible with lithographic technologies and smaller than that permitted by the bread loafing limitation, a two-phase process may be utilized wherein, in a first phase a first sidewall spacer is formed, any bread loafing is reduced or cleared and then a second sidewall spacer is formed over the first sidewall spacer, followed by bread loaf reduction. As a result of the repeated processes, relatively smaller critical dimensions may be formed. For example, in some embodiments, critical dimensions of at least as small as 60 nanometers can be formed. The critical dimension limitation with lithographic technology may be about 180 nanometers and with a single spacer technology the limitation may be around 80 nanometers in some embodiments.
  • [0015]
    Referring to FIG. 1, an embodiment is illustrated that is used to form a semiconductor phase change or ovonic unified memory (OUM). However, the present application has applicability to a wide range of semiconductor technologies in which contacts or other features are formed at sub-lithographic dimensions.
  • [0016]
    In FIG. 1, an interlayer dielectric 10 may be positioned over a substrate (not shown). The interlayer dielectric 10 may be formed of any dielectric insulating material, including oxide. Defined within the interlayer dielectric 10 is an electrical address line 12 which may be considered a row line in some embodiments of the present invention. The formation of copper row lines is well known to those skilled in the art.
  • [0017]
    Over the dielectric 10 may be formed another insulating layer 14 which, in one embodiment, may be nitride, and another insulating layer 16, which may be thicker than the layer 14. The layer 16 may be formed of oxide for example. A pore 22 may be defined using conventional lithographic techniques. The pore 22 may have a critical dimension, limited by lithographic capabilities, such that the width of the pore 22 is limited to be about 180 nanometers or larger in some embodiments.
  • [0018]
    A sidewall spacer may be formed in the pore 22 as shown in FIG. 2. The sidewall spacer may be formed of nitride spacer material 18. The nitride spacer material 18 may be deposited using conventional techniques and bread loafing may begin to occur as indicated at 20. Again, the bread loafing is the extension of the upper edges of the coating into the pore 22. Eventually, the bread loafed portions 20 could touch, if a thicker sidewall spacer was attempted, cutting off access to the pore 22. Once contact occurs between the two opposed, bread loafed portions 20, it is no longer possible to etch out the sidewall spacer.
  • [0019]
    The spacer material 18 may then be exposed to an anisotropic plasma etch. The etch parameters may be optimized to remove the bread loafed portions 20. As a result, in the sidewall spacers 18 shown in FIG. 3, the size of the critical dimension of the pore 22 may be reduced, for example, to about 80 nanometers. In addition, the bread loafed portion 20 may be substantially removed. While an embodiment using a nitride spacer is disclosed, other sidewall spacers may be utilized as well.
  • [0020]
    Then, referring to FIG. 4, a second sidewall spacer material 24 may be deposited over the first formed sidewall spacer 18. The material 24 may again be nitride. The sidewall spacer 24 may exhibit some bread loafing, but, again, the process may be stopped before the bread loafing closes off the pore 22.
  • [0021]
    Then, as indicated in FIG. 5, the sidewall spacer 24 may, again, be defined by a plasma based anisotropic etch. The etch may have its power and etch time optimized to reduce the bread loafed shoulder 25 and to open the pore 22 to the bottom contact which, in this case, is the electrical line 12. In some embodiments, the critical dimension of the pore 22 may be reduced to 60 nanometers or less.
  • [0022]
    Then, in an embodiment in which an ovonic unified memory is formed, the pore 22 may be filled with a layer of heater material 38. The heater material 38 may, in one embodiment, be formed of titanium silicon nitride, which may be deposited by chemical vapor deposition. The resulting product is then planarized.
  • [0023]
    Over the planarized surface may be formed a layer 36 of a chalcogenide material, in turn covered by a layer 34 that forms a top electrode. The chalcogenide material may be 225 GST (Ge2Sb2Te5) in one embodiment. The layers 34 and 36 may be patterned and etched into stripes or dots in some embodiments.
  • [0024]
    Then, the top electrode 34 may be covered by an encapsulation layer 30 in some embodiments. The encapsulation layer 30 protects the sidewalls of the chalcogenide material 36 and provides passivation. In one embodiment, the encapsulation layer 30 may be formed of low temperature nitride.
  • [0025]
    Next, a top passivating layer 28 may be applied which, in some embodiments, may be an oxide interlayer dielectric. Another address line 32 may be formed in the dielectric 28. The address line 32 may extend transversely to the address line 12. Thus, in some embodiments, the address line 32 may be considered a column line.
  • [0026]
    Thus, in some embodiments, relatively small critical dimension features may be formed which have dimensions smaller than lithographic dimensions and which are smaller than the limitations imposed by bread loafing in sidewall spacer technology. In some embodiments, more than two successive sidewall spacers may be formed. Successive sidewall spacers may be formed of the same or different materials.
  • [0027]
    The chalcogenide layer 36 may be a phase change, programmable material capable of being programmed into one of at least two memory states by applying a current to alter the phase of memory material between a more crystalline state and a more amorphous state, wherein the resistance of memory material in the substantially amorphous state is greater than the resistance of memory material in the substantially crystalline state.
  • [0028]
    Programming of the layer 36 to alter the state or phase of the material may be accomplished by applying voltage potentials to electrodes or lines 12 and 32, thereby generating a voltage potential across the layer 36. An electrical current may flow through the layer 36 in response to the applied voltage potentials, and may result in heating of the layer 36.
  • [0029]
    This heating may alter the state or phase of chalcogenide. Altering the phase or state of layer 18 may alter the electrical characteristic of memory material, e.g., the resistance of the material may be altered by altering the phase of the memory material.
  • [0030]
    In the “reset” state, memory material may be in an amorphous or semi-amorphous state and in the “set” state, memory material may be in a crystalline or semi-crystalline state. The resistance of memory material in the amorphous or semi-amorphous state may be greater than the resistance of memory material in the crystalline or semi-crystalline state. It is to be appreciated that the association of “reset” and “set” with amorphous and crystalline states, respectively, is a convention and that at least an opposite convention may be adopted.
  • [0031]
    Using electrical current, the memory material may be heated to a relatively higher temperature to amorphosize memory material and “reset” memory material (e.g., program memory material to a logic “0” value). Heating the volume of memory material to a relatively lower crystallization temperature may crystallize memory material and “set” memory material (e.g., program memory material to a logic “1” value). Various resistances of memory material may be achieved to store information by varying the amount of current flow and duration through the volume of memory material.
  • [0032]
    Turning to FIG. 7, a portion of a system 500, in accordance with an embodiment of the present invention, is described. System 500 may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System 500 may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect.
  • [0033]
    System 500 may include a controller 510, an input/output (I/O) device 520 (e.g. a keypad, display), a memory 530, and a wireless interface 540 coupled to each other via a bus 550. The system 500 may be powered by a battery 580 in one embodiment. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components or to battery-powered or wireless embodiments.
  • [0034]
    Controller 510 may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory 530 may be used to store messages transmitted to or by system 500. Memory 530 may also optionally be used to store instructions that are executed by controller 510 during the operation of system 500, and may be used to store user data. Memory 530 may be provided by one or more different types of memory. For example, memory 530 may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory such as memory discussed herein.
  • [0035]
    I/O device 520 may be used by a user to generate a message. System 500 may use wireless interface 540 to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of wireless interface 540 may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect. A static random access memory (SRAM) 560 may also be coupled to bus 550.
  • [0036]
    While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7671360 *Sep 4, 2007Mar 2, 2010Elpida Memory, Inc.Semiconductor device and method of producing the same
US8076664 *Dec 20, 2007Dec 13, 2011Intel CorporationPhase change memory with layered insulator
US8101456Oct 1, 2008Jan 24, 2012International Business Machines CorporationMethod to reduce a via area in a phase change memory cell
US8404514 *Jul 20, 2012Mar 26, 2013Intel CorporationFabricating current-confining structures in phase change memory switch cells
US8933430 *Oct 2, 2013Jan 13, 2015SK Hynix Inc.Variable resistance memory device and method of manufacturing the same
US9190613 *Nov 26, 2014Nov 17, 2015SK Hynix Inc.Variable resistance memory device including phase change area defined by spacers
US20080061282 *Sep 4, 2007Mar 13, 2008Elpida Memory, Inc.Semiconductor device and method of producing the same
US20090159867 *Dec 20, 2007Jun 25, 2009Savransky Semyon DPhase change memory with layered insulator
US20100078617 *Apr 1, 2010Breitwisch Matthew JMethod to reduce a via area in a phase change memory cell
US20150014621 *Oct 2, 2013Jan 15, 2015SK Hynix Inc.Variable resistance memory device and method of manufacturing the same
US20150076441 *Nov 26, 2014Mar 19, 2015SK Hynix Inc.Variable resistance memory device and method of manufacturing the same
Classifications
U.S. Classification257/510, 257/E45.002
International ClassificationH01L29/00
Cooperative ClassificationH01L45/126, H01L45/06, H01L45/144, H01L45/1233, H01L45/16
European ClassificationH01L45/12E2, H01L45/16, H01L45/06, H01L45/14B6, H01L45/12D4
Legal Events
DateCodeEventDescription
Jul 29, 2005ASAssignment
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JIN, MING;KARPOV, ILYA V.;LEE, JINWOOK;AND OTHERS;REEL/FRAME:016834/0254;SIGNING DATES FROM 20050726 TO 20050728
Apr 17, 2012ASAssignment
Owner name: NUMONYX B.V., SWITZERLAND
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEL CORPORATION;REEL/FRAME:028055/0625
Effective date: 20080325