|Publication number||US20070030019 A1|
|Application number||US 11/196,948|
|Publication date||Feb 8, 2007|
|Filing date||Aug 4, 2005|
|Priority date||Aug 4, 2005|
|Also published as||US8030952, US8692568, US20070030020, US20120019274, US20140210498|
|Publication number||11196948, 196948, US 2007/0030019 A1, US 2007/030019 A1, US 20070030019 A1, US 20070030019A1, US 2007030019 A1, US 2007030019A1, US-A1-20070030019, US-A1-2007030019, US2007/0030019A1, US2007/030019A1, US20070030019 A1, US20070030019A1, US2007030019 A1, US2007030019A1|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (9), Classifications (6), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application relates generally to semiconductor devices and device fabrication and, more particularly, to preheating circuits to a desired temperature prior to functional testing.
The semiconductor device industry has a market driven need to reduce the time and cost of testing electronic devices such as integrated circuits (ICs), assembled printed circuit boards (PCBs) having various IC and other electronic devices connected together on a ceramic or plastic board, and Micro electro-mechanical (MEM) devices, which may have electronic devices integrated on sensor or actuator substrates. Such testing may include function testing to determine which IC die are properly manufactured, burn in testing to determine if a functional die has what are known as infant mortality problems, hot sort testing to determine the operational speed limits of particular die so that they may be sorted into fast and slow devices, and basic reliability testing where a representative sample of manufactured die are life tested in accelerated environments to determine the expected overall failure rate. In many of these testing cases, the electronic device may have to be heated to a predetermined temperature, such as a normal long term operating temperature, prior to commencement of testing. Thus, one of the factors affecting the amount of time an IC electrical test may consume, and thus the overall cost of testing, is the need to have the IC raised, and perhaps maintained at a predetermined temperature.
It is known to use heated vacuum chucks to hold and heat IC wafers during initial function testing, and to use environmental ovens to control the temperature of packaged IC die and assembled PCBs, but such methods increase the equipment cost, tester space requirements and testing time. What is needed is a method to rapidly and accurately heat an electronic device for electrical testing.
Certain electronic devices may have a normal operating electrical current usage rate, or duty cycle, that changes greatly over relatively short periods of time, with a result that the amount of heating that may occur on the device also changes substantially. Such a device may experience what is known as thermal stress due to the constantly changing device temperature. Thermal stress may cause device package cracking with resultant exposure of the IC to environmental contaminants, and thus an accelerated failure rate. The constant flexing of joints between portions of the electronic device having different coefficients of thermal expansion (CTE) during the thermal changes may result in die to package substrate delamination and thus die failure. The CTE differences between the IC and plastic encapsulant materials during thermal changes may result in ruptured wire bond to IC connections and thus device failure. There are numerous other electronic device failure modes that may be accelerated by thermal changes, resulting in reduced device lifetime. While it is known that higher operating temperatures may cause decreased device reliability and reduced lifetime, a reduction in the amount of thermal cycling a device experiences may result in a greater improvement in the device reliability and lifetime than is lost due to the increase operation temperature. It is known to improve device reliability in high temperature cycle situations by the use of an environmental temperature controller to maintain the electronic device at a more constant temperature, but such devices consume space and electrical power.
As an illustrative example, it is known to test DRAM devices at an elevated temperature to accelerate and expose device failures which may not otherwise have been identified. One known method to preheat a DRAM prior to a test without the need for additional equipment and time, such as a environmental oven, is to use the DRAM circuitry in what may be known as a heat up mode, by repeatedly running the DRAM in auto refresh mode until the desired temperature is obtained. However, DRAMs have been forced in recent years to become lower power users by consumer demand, due to the increased number of DRAMs use in various low power products such as laptop computers, cellular telephones and personal digital assistants, all of which have power limitations since they are battery driven devices. As a result, even if a DRAM is heated up using the auto refresh mode operation prior to a burn in test, the low power consumption of the DRAM may mean that the device temperature may fall during the burn in test, thus invalidating the test.
Thus there exists a need in the art for a simple, fast and accurate method for pre-heating and/or maintaining a desired temperature or temperature profile in an electronic device for both testing and certain operational situations.
The abovementioned issues are addressed by the present invention and will be understood by reading and studying the following specification.
A method of heating a circuit for function testing, burn in testing, reliability testing, or in normal operation to reduce circuit temperature fluctuations, includes determining a current temperature of the circuit and comparing the current temperature to a desired temperature. If the desired temperature of the circuit is greater than the current temperature of the circuit, then enabling a power dissipation portion of the circuit at a predetermined operating rate and voltage, and then redetermining a new current temperature of the circuit after a predetermined time period has expired. The power dissipation portion of the circuit may be an additional circuit that is electrically isolated from the remaining circuit, and may use different input/output (IO) pads to avoid interference. The power dissipation portion of the circuit may be beneficially placed in a central region of the circuit so that the heating is uniformly spread throughout the functional portions of the circuit. In an embodiment, the power dissipation portion may be distributed around the entire periphery of the circuit. In an embodiment, the power dissipation portion may be distributed around the periphery of the circuit as well as in selected functional portions of the circuit. The power dissipation circuit may be a resistive element connected between two external IO contact pads that are not used by any other portion of the circuit, or the power dissipation may be a portion of the circuit that is not currently being used in circuit operations, such as during function testing of the circuit. The total power dissipation may be controlled by voltage across the resistive element, or by the clock rate of the circuit portion used.
The desired temperature may a burn in temperature, or a ramped hot sort temperature profile to determine the operating range of the circuit. The current temperature of the circuit may be obtained from a temperature sensor integrated as part of the circuit, such as using an isolated diode junction as a thermometer. The desired temperature of the circuit does not have to be a constant temperature, as in the example of a ramped temperature profile for operation limit testing, or in long term reliability testing of thermal cycling resistance. In normally operating IC devices or assembled PCB devices the desired temperature may depend upon whether the device is in a sleep mode, or whether it is in a ready state. In micro electromechanical devices (MEMs) the desired temperature for a portion of the device, such as the region surrounding an oscillator, may have a different desired temperature than regions of the MEM that have integrated circuits.
These and other aspects, embodiments, advantages, and features will become apparent from the following description and the referenced drawings.
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC) structure or a micro electro-mechanical (MEM) structure. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to generally include n-type and p-type semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors or as semiconductors.
The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
The circuitry in heater region 126 may be any form of heat dissipating circuitry, including ring oscillators, DRAM cells operated in auto refresh mode continuously as long as heating is required, or any of many other well known circuits which may be controllably operated in either an on/off mode, or operated in a more continuously variable heat generating mode, such as changing the clock rate on a logic, clock or oscillator circuit. It should be noted that the location of heater 126 on the edge of the IC 100 is not intended as a limitation on the embodiment, and alternative locations may be considered, for example with the heater 126 located between the memory array 122 and the logic 124 to provide more even heat distribution across the IC 100. Locating the heater 126 near the logic region 124 and distant from the memory 122 may be useful in normal operations if the logic region 124 is frequently left in an idle mode while waiting for information to be retrieved from the memory 122, and thus may suffer increased thermal cycling, which may cause decreased reliability. Alternatively, placing the heater section 126 next to the memory section 122 may be useful for preheating the memory 122 to an operating temperature prior to electrically testing the IC 100 for what may be known as burn in failures or infancy failures prior to shipping the IC 100 from the manufacturer. An illustrative example of a temperature range used for infancy failure testing of DRAMs is from 85 to 125° C.
The heater region 126 may not be formed as a compact region as shown in this illustrative embodiment, but may rather be a series of transistor circuits scattered around in the IC 100 to provide a more even heat distribution. The heater region 126 may also be a virtual region formed of portions of the operating circuitry of IC 100 that happen not to be used during a particular operation, such as the burn in testing of the memory arrays 122. In such an arrangement there is no lost or wasted area of the IC 100 used for the heater 126 and then not used for the normal operation of the IC 100. Such an arrangement may be useful if the IC 100 is only going to need the heater 126 during function and reliability electrical testing of the IC 100, and if space is a problem with the design of IC 100. An illustrative example of a temperature range used for burn in testing of DRAMs is 50 to 60° C.
The heater 126 may be controlled externally by applying a voltage to pads 102 and 112, or may be controlled by internal circuitry on the IC 100, using an integrated temperature sensor on the IC 100. Such a temperature sensor may be located in the region 126, and may be formed by measuring the forward bias of a diffused diode and comparing the value to either an input value provided externally through an IO pad (not shown for simplicity), or to a single value or time dependent temperature profile stored in either the memory array 122, or in another memory array (not shown for simplicity) in heater 126, or a different location on the IC 100. The applied voltage will depend upon the particular technology level of the IC 100, and may range from 0.5 to 2.2 volts on typical IC devices.
The assembled PCB 300 will likely have had each of the ICs 302 to 320 tested numerous times prior to the final assembly. Typically each of the ICs 302 to 320 will have been electrically tested while still part of the wafer in which they were fabricated, then the good die will have been sawn from the wafer and assembled in the final package, and then tested again at full speed to eliminate ICs that have become faulty since being tested in the wafer, defects introduced in the packaging process, and ICs that are functional but not fast enough to meet specifications. Some of the ICs may have been operated at elevated temperatures for time periods long enough to eliminate ICs that have hidden failures likely to cause failures early in the operating life of the device, which may be called infancy failures. Such elevated temperature tests may be called a burn in. Even though essentially all of the ICs 302 to 320 have been tested numerous times previously, there is still a need to test the entire assembly on the PCB 300 to determine if there have been failures introduced in the soldering process used to assemble the board, or if there are other IC related problems, such as speed and timing interactions, that can only be revealed when used in conjunction with the other ICs. Since chip temperature affects the IC operating speed, and thus the timing interaction between the various ICs, a proper PCB electrical function test may require that some or all of the ICs 302 to 320 be heated to a normal operating temperature range before the PCB test commences. One method to obtain an operating temperature for the ICs 302 to 320 might be to place the PCB 300 in an environmental oven along with the testing fixture. This requires special equipment and takes additional time and handling. Thus some or all of the ICs 302 to 320 may beneficially be designed with the built in heater on the IC as disclosed previously.
Structures such as shown in
An embodiment of the invention includes a module level tester that exercises a DRAM at an elevated die temperature without use of an external heated air supply or the consequent increased test time involved in using external heaters. An exemplary DRAM device such as the 1 Gb DDR2 SDRAM by Micron Technology, Inc., operating at 1.8 volts at 4,300 MB/sec uses so little current that during a heated function test at 55° C., the die temperature may return to 35° C. as quickly as 30 seconds after the heater is turned off. Thus, due to the low power consumption of such devices as the DDR2 SDRAMs, or high speed low latency cache memories such as the 576 Mb RLDRAM by Micron Technology, Inc., operating at 1.5 volts, or many future memory and logic devices, testing the devices at a temperature the devices are likely to see when part of a larger electroscopic system, will require the use of expensive and time consuming external heat systems.
An embodiment of the invention includes designing a circuit with at least one alternate current path on either the silicon device (such as a DRAM) or on the printed circuit board that when enabled by means of signals on selected input output pads or pins will consume power either in addition to that being consumed by normal or test operation of the circuit, or will consume power prior, during or after the circuit being operated to bring or maintain the total power dissipation, and consequently the overall circuit temperature to a desired point. The amount of power consumed may be adjusted by either controlling the number of alternate current paths, or by adjusting the operational rate of the current paths. The method of enabling the alternate current paths may be performed by setting a mode register and issuing a unique sequence of commands, or it could be initiated by toggling an external device pin not used by the normal circuit operation. In this fashion the built in heater circuitry may be operated during test procedures, or during normal device operation for either startup mode operation, or for long term temperature stability in devices having variable duty cycles.
In either the test case, or the normal operation case, the embodiment has a two bit input 520 to a heater function used as a power sink for thermal control of the DRAM 500. The input 520 may be separate external input pads that are toggled on and off to control the amount of heating as shown, or may be internal inputs from controllers on DRAM 500. There may be only a single input pad on the input 520 in the case of a simple resistance heater or a single stage heater circuit, but the invention is not so limited. The input 520 may be a clock to drive an oscillator circuit with a rate determined by the amount of heating desired.
The illustrated embodiment has two bits that may be set in accordance with well known methods to drive a selected one of the four illustrative heat generating circuits 526 to 532. Heat generating circuit 526 may be taken to represent a 100 ohm power sink, with circuit 528 being a 200 ohm power sink, with circuit 530 being a 300 ohm power sink, and with circuit 532 being a 400 ohm power sink. With such an arrangement it is possible to generate different desired heat sources with the use of two extra input pins. Alternatively, the number of input pins used may be increased to allow greater heat generation flexibility by allowing two or more of the heat generating circuits 526 to 532 to be operated in parallel, thus providing up to 1000 ohm power sinking with the previously described circuits.
Alternatively, the heater function input 520 may be controlled by an onboard mode register as may be found on memory products having what may be known as on die termination control, such as the DDR2 SDRAMs available from Micron Technology, Inc. Such a thermal heat function system may thus be used in either a test mode, or in a non test mode by using a unique command sequence, and the low impedance thermal power sink circuits may be formed using similar resistor and transistor circuits as those already found in the on die termination circuits.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of embodiments of the present invention, including but not limited to burn in testing, reliability testing, hot sort device maximum operating speed sorting, and normal device operation with temperature variation reduction. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description. The scope of the present invention includes any other applications in which embodiments of the above structures and fabrication methods are used. The scope of the embodiments of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7888951 *||Feb 10, 2009||Feb 15, 2011||Qualitau, Inc.||Integrated unit for electrical/reliability testing with improved thermal control|
|US7965094||Jul 14, 2008||Jun 21, 2011||Honeywell International Inc.||Packaged die heater|
|US8016482 *||Jul 20, 2007||Sep 13, 2011||International Business Machines Corporation||Method and systems of powering on integrated circuit|
|US8030952||Jul 28, 2006||Oct 4, 2011||Micron Technology, Inc.||Power sink for IC temperature control|
|US8118483 *||Jun 21, 2006||Feb 21, 2012||Intel Corporation||Thermal sensor having toggle control|
|US8358145 *||Jun 19, 2009||Jan 22, 2013||Western Digital Technologies, Inc.||Self-heating integrated circuit|
|US8684597||Feb 21, 2012||Apr 1, 2014||Intel Corporation||Thermal sensor having toggle control|
|US8692568||Oct 3, 2011||Apr 8, 2014||Micron Technology, Inc.||Electronic apparatus having IC temperature control|
|EP2146214A1||May 1, 2009||Jan 20, 2010||Honeywell International||Packaged die heater|
|U.S. Classification||324/750.07, 324/762.02|
|Cooperative Classification||G01R31/2856, G01R31/2851|
|Aug 4, 2005||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KINSLEY, TOM;REEL/FRAME:016863/0550
Effective date: 20050727