US 20070035716 A1
An exposure method for exposing a pattern of a reticle onto a plate using a light from a light source and an optical system includes the steps of obtaining a relationship between an exposure parameter that determines a mode to expose a plate, and an electrical characteristic of a device derived from the device, determining whether the device obtained from the set exposure parameter has a predetermined electrical characteristic, and adjusting the set exposure parameter based on the relationship between the exposure parameter and the electrical characteristic, if the determining step determines that the device does not have the predetermined electrical characteristic.
1. An exposure method for exposing a pattern of a reticle onto a plate using a light from a light source and an optical system, said exposure method comprising the steps of:
obtaining a relationship between an exposure parameter that determines a mode to expose a plate, and an electrical characteristic of a device derived from the device;
determining whether the device obtained from the set exposure parameter has a predetermined electrical characteristic; and
adjusting the set exposure parameter based on the relationship between the exposure parameter and the electrical characteristic, if said determining step determines that the device does not have the predetermined electrical characteristic.
2. An exposure method according to
3. An exposure method according to
4. An exposure method according to
5. An exposure method according to
6. An exposure method according to
7. An exposure method according to
adjusting a first exposure parameter that depends upon the optical system, by using an optical simulation; and
adjusting a second exposure parameter that does not depend upon the optical system, without an optical simulation.
8. A database that stores a relationship used for an exposure method according to
9. A program for enabling a computer to implement an exposure method according to
The present invention relates generally to an exposure method, and more particularly to an optimization of an exposure condition.
A conventional projection exposure apparatus uses a projection optical system to expose a reticle (or mask) pattern onto a plate, such as a single crystal substrate for a semiconductor wafer, and a glass plate for a liquid crystal display. In order to meet a demand for inexpensively supplying many electronic apparatuses, a method for manufacturing a device, such as a semiconductor chip (e.g., an LSI, a VLSI), a CCD, an LCD, a magnetic sensor, and a thin-film magnetic head), needs to improve the yield rate. This device manufacturing method includes various processes, such as exposure, development, and etching. In exposure, a conventional exposure apparatus considers not only the resolution at which the reticle pattern precisely resolve on a plate to be exposed, but also the influence on the other processes in the device manufacturing method.
The optimizations of both the exposure condition and the reticle pattern are important for improved resolution. See, for example, Japanese Patent Applications, Publication Nos. 2005-26701 and 2002-319539. A reticle pattern is optimized, for example, through an optical proximity correction (OPC). A critical dimension (CD) uniformity is known as a general conventional evaluation index of the resolution. See, for example, Japanese Patent Applications, Publication Nos. 2003-257819 and 2005-094015. Japanese Patent Application, Publication No. 9-319067 proposes a technology, called a process proximity control (PPC), which adds an etching error caused by the pattern density, to a reticle design in advance so as to correct the etching error. A simulation or a simulator may be used instead of actually exposing the plate for effective optimizations.
Other prior art include, for example, SPIE 5379-15 Design rule optimization for 65-nm-node (CMOS5) BEOL using process and layout decomposition methodology and Evert Seevinck, Frans J. List, and Jan Lohstroh, Static-Noise Margin Analysis of MOS SRAM Cells, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October (1987). The above SPIE reference discloses a via chain as a test pattern under various design rules, measures the resistance, and determines whether the design rules and the OPC are properly set.
As finer processing advances, an interaction between processes in the device manufacturing method becomes non-negligible, and the yield rate control over exposure only using the CD uniformity cannot necessarily improve the yield rate. Whether or not the device is defective as an electronic component depends upon the electrical characteristic of the device. A typical example of the electrical characteristic is a power supply voltage characteristic that is defined as a voltage change of the device to the power supply, but the electrical characteristic may be durability, resistance, electric capacity, etc.
For a static RAM (SRAM), an illustrative electrical characteristic includes a static noise margin (SNM) (see the above IEEE reference), VTH difference in a transistor gate, etc. The electrical characteristic to be verified differs according to device types.
However, the evaluation index relating to the resolution does not always correspond to the electrical characteristic. For example, even when the CD uniformity is bad, the device is not defective in view of the electrical characteristic, and even when satisfying a predetermined CD uniformity, the device is defective in view of the electrical characteristic.
The present invention is directed to an exposure method that can manufacture a device as a final product with a good yield rate.
An exposure method according to one aspect of the present invention for exposing a pattern of a reticle onto a plate using a light from a light source and an optical system includes the steps of obtaining a relationship between an exposure parameter that determines a mode to expose a plate, and an electrical characteristic of a device derived from the device, determining whether the device obtained from the set exposure parameter has a predetermined electrical characteristic, and adjusting the set exposure parameter based on the relationship between the exposure parameter and the electrical characteristic, if said determining step determines that the device does not have the predetermined electrical characteristic. A database that stores a relationship used for the above exposure method, and a program for enabling a computer to implement the exposure method also constitute one aspect of the present invention.
Other objects and further features of the present invention will become readily apparent from the following description of the preferred embodiments with reference to the accompanying drawings.
Referring now to the accompanying drawings, a description will be given of the preferred embodiments of the present invention.
The processing system 10 obtains reticle data and exposure condition from the input parts 20 a to 20 c, and selects an appropriate one of the exposure apparatuses 40 a to 40 d. The exposure apparatuses 40 a to 40 d have different characteristic data and specifications, such as a light source (ArF, KrF, EUV etc.), an exposure method (scanner, stepper, etc.), an illumination condition (polarization illumination, effective light source, etc.), and a projection optical system (dioptric, catadioptric, immersion system, etc.). In addition to these data, the processing system 10 has difference data among the same type of exposure apparatuses. The processing system 10 previously obtains the characteristic data of the exposure apparatuses 40 a to 40 d, and stores them in a memory. The operating system 30 is a computer that executes the optimization algorithm shown in
The exposure parameter includes, for example, a numerical aperture (NA) of a projection optical system, an exposure dose, a focus, a Zernike coefficient, a pupil transmittance, an effective light source distribution, a telecentricity, a polarization degree, a polarization degree difference among image heights, a slit profile, a spectrum distribution of the light source, a longitudinal magnification, a lateral magnification, a shot rotation, and a decentering distortion.
The electrical characteristic can be evaluated by utilizing a Monte Carlo simulation and sensitivity analysis (MCSS) as described later, without actually completing the device. The device's electrical characteristic is likely to dramatically affect the yield rate as a memory cell size reduces in the future fine processing. The following primary causes are influential to the electrical characteristic: Firstly, a difference amount due to the manufacturing factor can increase relative to the design size of the gate width and the gate length. Secondly, an ion implantation dose difference cannot be negligible as the gate size reduces. Thirdly, a difference of the gate film thickness and the gate film dielectric constant cannot be negligible.
On the other hand, it is known that a certain electrical characteristic relates to a specific evaluation index. For example, according to the above SPIE reference, the line end shorting (LES), etc. deteriorate the yield rate. The LES is a phenomenon of a non-resolution of a tip of a line pattern due to the focusing fluctuation. The LES occurs with an insufficient OPC due to the device layout limitation. A relationship between the LES and the electrical characteristic is, for example, such that the LES in the gate layer changes the electrical characteristic, such as resistance, due to the gate length. Other factors for this type of phenomenon are a line edge roughness (LER) and a sidewall angle (SWA) relating to the SNM, and commonly influential on the electrical characteristic because they are likely to change the circuit shape.
Step 1002 obtains the above relationship, for example, by measuring the electrical characteristic after producing the actual device with various different exposure parameters. Referring to
Next, an initial state of the exposure parameter is set (step 1004). The initial state of the exposure parameter may be set such that a large exposure margin is secured.
Then, it is determined whether the device obtained from the exposure parameter has a predetermined electrical characteristic (step 1006). For this determination, a test chip may be actually manufactured and its electrical characteristic may be measured. The simulation may use, for example, the MCSS for each layer of the device.
A description will now be given of the SNM in the SRAM. The SRAM is used for a cash memory that connects the CPU to the DRAM, accelerating the processing speed, and enhancing the high speed and efficiency of the entire system. The DRAM needs refreshing at regular time periods, whereas the SRAM uses an electronic circuit called flip-flop. As long as the power is supplied, the data can be statically stored without refreshing.
In storing data in the SRAM, the state of the word line WL is turned to L, and thereby Qn3 and Qn4 are turned off. The write information is maintained as long as Vcc (or the power) is maintained, because the SRAM cell serves as a capacitor and charges accumulate.
In reading data from the SRAM, the state of the word line WL is again turned to H, and thereby Qn3 and Qn4 are turned on. When the left node is in the state of 1 and the right note is in the state of 0, the voltage is applied to BL1. A detection of the voltage enables the data to be read out. A sensing amplifier detects this voltage. The sensing amplifier is a circuit that amplifies the voltage from the memory cell. Although
Data is thus written in, held in, and read from the SRAM. However, a noise occurs in reading the data from the SRAM when the state of the word line WL turns to H, and Qn3 and Qn4 are switched on. The noise causes 1 of the left node and 0 in the right node to be erroneously detected as 0 of the left node and 1 in the right node.
The SNM is an index of robustness to the reading noise.
Assume that the voltage of ND1 is VA and the voltage of ND2 is VB in
While the data is being held, a node's voltage characteristic is at one of the stable points. When the state of the stable point is turned from L to H in the word line WL, the voltage VA of the node 1 and the voltage VB of the node 2 are instantly transferring to the state of the stable 2, and return to the state of the stable point 1. With a large SNM, the state is likely to return to the stable point 1, whereas with a small SNM, the state is less likely to return to the stable point 1. With a small SNM, the sensing amplifier is likely to erroneously detect a change of the stage from the stable point 1 to the stable point 2 due to unexpected charged particle's influence. Therefore, the SRAM having a large SNM is preferable.
The above IEEE reference discloses the SNM model equation in detail. According to the above IEEE reference, the SNM in the SRAM that has a noise equivalent circuit as shown in
r in Equation 1 represents a cell ratio expressed by βd that is (gate width)/(gate length) in a driver transistor, divided by βa that is (gate width)/(gate length) in an access transistor. The driver transistor corresponds to Qn1 and Qn2 in
Another example of the electrical characteristic is difference of VTH. VTH is a gate threshold voltage, and when the voltage applied to the gate exceeds a threshold voltage, the source and drain are electrically connected to each other. The different VTH values in the cell influence the yield rate of the device. Control over VTH would improve the yield rate of the device, but VTH varies due to various manufacturing process factors. By way of example of the SRAM cell circuit shown in
Turning back to
This embodiment adjusts the exposure parameter (or condition) instead of the reticle pattern as in step 1008. As discussed above, since each device has its own electrical characteristic to be verified, it is preferable to optimize exposure of the plate such that the electrical characteristic to be verified improves in each device. It is conceivable as in the above SPIE reference that the reticle pattern is optimized based on the device's electrical characteristic. However, this SPIE reference merely optimizes the reticle pattern through the OPC and PPC, and does not weigh the exposure apparatus's characteristics or the reticle's manufacturing errors. Thus, the method proposed in this reference is insufficient in improving the yield rate of the device. In addition, even though the reticle pattern is optimized for a specific exposure apparatus difference, it is difficult to apply the reticle pattern to another exposure apparatus different from the specific exposure apparatuses and the flexible application to any exposure application is lost. Therefore, in optimizing the exposure condition, it is necessary that the former seek the yield rate improvement and the latter improve the flexible application.
For example, in adjusting the exposure parameter of the gate layer so as to minimize a difference of VTH in the SRAM cell, one of the electrical characteristics to be controlled for the device is the gate threshold voltage VTH. In particular, in the same type of transistor in the same cell, different VTH causes failure of the cell. The exposure process controls VTH by taking into account a size effect, such as a gate length, a gate width, a gate area, and a junction area between the source/drain layer, and needs such an exposure condition as reduces differences among them. An illustrative exposure condition that reduces a different size effect is to restrain the LES caused by the defocus by adjusting the NA of the projection optical system, and the effective light source shape in the modified illumination.
In general, a high NA is used for a critical layer to improve the pattern transferring characteristic. Here,
Another embodiment optimizes the exposure condition of the gate layer such that the SNM becomes maximum in the SRAM cell structure. It is known that the cell ratio r and VTH influence the SNM in Equation 1. A designed value sets a parameter, such as VDD, and the exposure process must weigh values of the cell ratio r and transistor's VTH so as to improve the SNM. Since the SNM improvement in the exposure process weighs the VTH and r values, a reset of the exposure condition is necessary by weighing the size effect of the driver transistor. The cell ratio r is a ratio between the β value of the driver transistor Qn2 and the β value of the access transistor Qn4.
A description will be given of one illustrative exposure condition that weighs the gate size effect to improve the SNM. An adjustment of the exposure dose leads to an adjustment of the driver transistor's gate length.
The gate length can be shortened, as shown in
Still another embodiment resets the exposure condition for the SRAM cell so as to improve two electrical characteristics, such as SNM and a VTH difference. In that case, even when the exposure dose is made small and the cell ratio is made large in view of the LES amount as discussed above, the device may be still defective when the VTH difference is large. It is therefore necessary to set the exposure dose by weighing a difference amount of the size effect in the driver transistor.
When plural exposure parameters relate to the electrical characteristic, step 1008 selects the most influential exposure parameter on the predetermined electrical characteristic (or the exposure parameter that varies the predetermined electrical characteristic most significantly when changed) among the plural exposure parameter. For example, the exposure parameter is slightly varied and the electrical characteristic deterioration is verified through the MCSS of VTH. Step 1002 stores, as the relationship, the influence of the exposure parameter on the electrical characteristic. The electrical characteristic is effectively corrected with the exposure parameters in order of influence.
Assume that the distortion is the most influential exposure parameter. The qualitative reason of the distortion's influence on VTH is that any overlay error between the source/drain layer and the gate layer cause a difference of ion dose in the active area and thus would scatter VTH.
The SRAM cell structure shown in
A diffraction optical element (DOE) is effective to form a desired effective light source shape. Use of the DOE would contain an error caused by the manufacturing error of the DOE. In that case, another DOE would improve the electrical characteristic. The electrical characteristic improves when an optimal DOE is selected to a combination of the mask data and the exposure apparatus.
In that case, as shown in
When plural electrical characteristic exit, step 1006 selects the most influential electrical characteristic on the device yield rate in the plural electrical characteristics. In other words, each electrical characteristic is weighed based on a contribution degree to the final yield rate. For example, in determining the outer σ as the largest radius in the effective light source, the optimal outer σ to SNM improvement and the optimal outer σ to the VTH improvement exist. A relationship between the SRAM device structure in
Assume that SNM is more influential on the device's yield rate than VTH. In that case, step 1008 adjusts the exposure parameter such that SNM improves most.
An embodiment that weighs the electrical characteristics based on the contribution degree to the final yield rate can weigh the electrical characteristics based on the fraction defective of the electrical characteristics of the transistors Qn1 and Qn2 in the SRAM cell.
When the plural exposure parameters relate to the predetermined electrical characteristic, the most influential exposure parameter is selected among the plural exposure parameters. More specifically, step 1008 selects one of the plural exposure parameters, which one has the largest value when the set exposure parameter is substituted for a differential function of the function.
Assume that the electrical characteristic is SNM, and the NA, and annular ratio in the annular illumination (outer σ) and spherical aberration are involved in step 1002. In that case, the NA is varied, and a relationship between the NA and SNM, or a function SNM=f(NA) is simulated. Similarly, the annular ratio and the spherical aberration are varied, and a relationship between the annular ratio and SNM, i.e., SNM=f(outer σ), and a relationship between the spherical aberration and SNM, i.e., SNM=f(outer σ), are simulated.
Next, these three functions are differentiated by the NA, annular ratio, and the spherical aberration, into the three differential functions are obtained, such as d(SNM)/d(NA), d(SNM)/d(outer σ), and d(SNM)/d(spherical aberration). Next, values of the NA, outer σ, and the spherical aberration set in step 1004 are substituted in these differential functions and the largest differentiated values are obtained. If the differentiated values are arranged in order of NA>outer σ>spherical aberration, the NA is selected as an exposure parameter for optimization. Even when the NA is optimized, fed back step 1006 determines that SNM is still outside the predetermined range, the outer σ is optimized while the optimal value of the NA is maintained. Even when the outer σ is optimized, fed back step 1006 determines that SNM is still outside the predetermined range, the spherical aberration is optimized while the optimal value of the NA and outer σ are maintained. The exposure parameters can be effectively optimized by adjusting the parameters in order of higher influence on SNM.
Step 1008 may include the step of adjusting an exposure parameter that depends upon an optical system (e.g., an illumination optical system and a projection optical system by using an optical simulation, and the step of adjusting an exposure parameter that does not depend upon the optical system without an optical simulation. The optical simulation is one necessary type of simulation in simulating the device's electrical characteristic from the plate to be exposed.
In general, the optical simulation has a heavy calculational load. Therefore, the simulation that varies the NA, effective light source shape, and the aberrational parameter to verify the electrical characteristic needs a long calculation time period. On the other hand, relative to the optical image calculation, a parameter/exposure condition, such as scanning directions and rotations of wafer and reticle stages, is a parameter relating to slicing level setting, a focus position, and overlay, and involves after the optical image is determined. Once the optical image is calculated, and the optical image is processed and reused, a relationship between the electrical characteristic and a parameter, such as an exposure dose, an overlay, and a light source's wavelength, can be easily obtained.
The exposure apparatus parameter that does not depend upon the optical system includes an exposure apparatus parameter that can approximately calculate an optical image using an overlay of the optical image. For example, the parameters include a light source's spectrum distribution, a chromatic aberration, and a stage vibration (MSDz). When the light source has a spectrum distribution, the best focus position shifts among the respective wavelengths. An optical image can be formed by superposing defocus images of a reference wavelength, when the light source has a spectrum distribution. Since the optical image superposition has a small calculational load, the parameter adjustment in case of the spectrum distribution etc., may be adjusted after the optical simulation that determines the parameter that depends upon the optical system, such as an illumination shape and the aberration.
After the exposure parameter depending upon the optical system, such as an NA, an illumination shape, and an aberration, is optimized using a simulation that improves the SNM, the exposure parameter that does not depend upon the optical system, such as an exposure dose and a focus position, is optimized for effective parameter setting.
Turning back to
Further, the present invention is not limited to these preferred embodiments, and various variations and modifications may be made without departing from the scope of the present invention. For example, it is possible to set an exposure apparatus parameter based on a factor implicated with the electrical characteristic, such as LES, SWA, and LER.
This application claims a foreign priority based on Japanese Patent Application No. 2005-220529, filed on Jul. 29, 2005, and which is hereby incorporated by reference herein.