|Publication number||US20070090416 A1|
|Application number||US 11/238,447|
|Publication date||Apr 26, 2007|
|Filing date||Sep 28, 2005|
|Priority date||Sep 28, 2005|
|Also published as||US7902014, US8294180, US20070111419, US20110180851|
|Publication number||11238447, 238447, US 2007/0090416 A1, US 2007/090416 A1, US 20070090416 A1, US 20070090416A1, US 2007090416 A1, US 2007090416A1, US-A1-20070090416, US-A1-2007090416, US2007/0090416A1, US2007/090416A1, US20070090416 A1, US20070090416A1, US2007090416 A1, US2007090416A1|
|Inventors||Brian Doyle, Been-Yih Jin, Jack Kavalieros, Suman Datta, Justin Brask, Robert Chau|
|Original Assignee||Doyle Brian S, Been-Yih Jin, Kavalieros Jack T, Suman Datta, Brask Justin K, Chau Robert S|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (42), Classifications (20), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application relates to the application entitled “Method of Fabricating CMOS Devices Having a Single Work Function Gate Electrode by Band Gap Engineering and Article Made Thereby,” filed on Sep. 28, 2005.
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly to CMOS (complementary metal oxide semiconductor) devices having gate electrodes with a single work function.
2. Discussion of Related Art
During the past two decades, the physical dimensions of MOSFETs have been aggressively scaled for low-power, high-performance CMOS applications. In order to continue scaling future generations of CMOS, the use of metal gate electrode technology is important. For example, further gate insulator scaling will require the use of dielectric materials with a higher dielectric constant than silicon dioxide. Devices utilizing such gate insulator materials demonstrate vastly better performance when paired with metal gate electrodes rather than traditional poly-silicon gate electrodes.
Depending on the design of the transistors used in the CMOS process, the constraints placed on the metal gate material are somewhat different. For a planar, bulk or partially depleted, single-gate transistor, short-channel effects (SCE) are typically controlled through channel dopant engineering. Requirements on the transistor threshold voltages then dictate the gate work-function values must be close to the conduction and valence bands of silicon. For such devices, a “mid-gap” work function gate electrode that is located in the middle of the p and n channel work function range is inadequate. A mid-gap gate electrode typically results in a transistor having either a threshold voltage that is too high for high-performance applications, or a compromised SCE when the effective channel doping is reduced to lower the threshold voltage. For non-planar or multi-gate transistor designs, the device geometry better controls SCE and the channel may then be more lightly doped and potentially fully depleted at zero gate bias. For such devices, the threshold voltage can be determined primarily by the gate metal work function. However, even with the multi-gate transistor's improved SCE, it is typically necessary to have a gate electrode work function about 250 mV above mid-gap for an nMOS transistor and about 250 mV below mid-gap for a pMOS transistor. Therefore, a single mid-gap gate material is also incapable of achieving low threshold voltages for both pMOS (a MOSFET with a p-channel) and nMOS (a MOSFET with an n-channel) multi-gate transistors.
For these reasons, CMOS devices generally utilize two different gate electrodes, an nMOS electrode and a pMOS electrode, having two different work function values. For the traditional polysilicon gate electrode, the work function values are typically about 4.2 and 5.2 electron volts for the nMOS and pMOS electrodes respectively, and they are generally formed by doping the polysilicon material to be either n or p type. Attempts at changing the work function of metal gate materials to achieve similar threshold voltages is difficult as the metal work function must either be varied with an alloy mixture or two different metals utilized for n and p-channel devices.
One such conventional CMOS device 100 is shown in
A novel device structure and its method of fabrication are described. In the following description, numerous specific details are set forth, such as specific materials, dimensions and processes, etc. in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention.
Embodiments of the present invention include complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage. In particular embodiments, the complementary devices utilize the same material having a single work function as the gate electrode. Engineering the band gap of the semiconductor transistor channels rather than engineering the work function of the transistor gate metal for the individual pMOS and nMOS devices avoids the manufacturing difficulties associated with depositing and interconnecting two separate gate metals in a dual-metal gate process. A single metal gate stack, used for both pMOS and nMOS transistors, simplifies fabrication while engineering the band gap of the semiconductor transistor channels enables independent tuning of the pMOS and nMOS threshold voltages. In embodiments of the present invention, the threshold voltage of a device can be targeted through the use of semiconductor materials that have an appropriate valance band (pMOS) or conduction band (nMOS) offset relative to the complementary device. Therefore, embodiments of the present invention can utilize a single mid-band gap metal for both the pMOS and nMOS transistors in a CMOS device while still achieving a low threshold voltage for both the pMOS and nMOS transistors.
An example of a CMOS device 200 with a metal gate structure and an engineered band gap in accordance with an embodiment of the present invention is illustrated in
In alternate embodiments of the present invention (not shown) both the pMOS transistor and nMOS transistor comprise a semiconductor cladding material having a band offset relative to the substrate semiconductor. When the cladding material has only a valence band offset (no conduction band offset) relative to the substrate, the cladding layer on the nMOS transistor will not have any effect on the nMOS threshold voltage.
In a particular embodiment of the present invention, as shown in
In another embodiment of the invention, as shown in device 300 of
In embodiments shown in both
The semiconductor cladding 208 is ideally capable of remaining single crystalline with the semiconductor body 206 to ensure sufficient carrier lifetime and mobility, as the cladding 208 comprises the channel region of pMOS transistor 204. Semiconductor cladding 208 can be formed of any well-known semiconductor material, such as silicon germanium (SiGe), indium gallium arsenide (InxGa1-xAsy), indium antimonide (InxSby), indium gallium phosphide (InxGa1-xPy), or carbon nanotubes (CNT). In certain embodiments of the present invention where the semiconductor of bodies 206 and 207 are silicon, the semiconductor material used for the cladding 208 is SiGe. In certain other embodiments, one semiconductor body is silicon and the cladding layer is an alloy of silicon and carbon (SiC). In other embodiments of the present invention having a planar or single-gate transistor design (not shown), the cladding layer is formed directly on and adjacent to a top surface of the active semiconductor region over the substrate. In certain embodiments of the present invention having a multi-gate transistor design, as shown in
In certain embodiments of the present invention, the cladding 208, as shown in
Embodiments of the present invention include increasing the valence band energy of a pMOS transistor having a SiGe cladding region by increasing the concentration of the germanium. In this manner, it is possible to fabricate both a pMOS and nMOS multi-gate transistor having gate electrodes of the same material and threshold voltage magnitudes less than 0.7 V over a range of transistor channel doping levels. As the valence band energy increases, the threshold voltage is lowered by an amount approximately equal to the valance band voltage offset. In an embodiment of the present invention, the germanium concentration is between 5 and 50 percent, and more particularly, between 15 and 30 percent. For embodiments having about 25 percent germanium, the valence band energy is increased by about 300 mV above the valence band of silicon. Thus, a pMOS device having a SiGe channel region comprised of about 25 percent germanium will have a threshold voltage magnitude approximately 300 mV less than that of a pure silicon channel.
In embodiments of the present invention, nMOS multi-gate devices have a work function difference (the difference between the gate metal work function an the semiconductor work function or (φmetal−φsemiconductor) of about 0.4 eV while the work function difference for a pMOS multi-gate device is about 0.7 eV. In a particular embodiment of the present invention, the 0.4 eV nMOS work function difference is achieved through Fermi-level pinning a mid-gap titanium nitride metal gate material (having a work function of about 4.7 eV). In a further embodiment of the present invention, a 0.7 eV pMOS work function difference is achieved with a band-engineered SiGe channel region comprised of about 25 percent germanium. The 25 percent germanium-cladding region increases the semiconductor valance band energy and, in effect, shifts the work function difference of the mid-gap titanium nitride metal gate material by about 300 mV, from the pinned Fermi-level of 0.4 eV to the desired 0.7 eV.
Embodiments of the present invention include adjusting the germanium concentration of a pMOS SiGe cladding region to adjust the threshold voltage, enabling multiple threshold voltages on the same chip, which is a different challenge from setting a single threshold voltage to match an nMOS device. For ULSI systems, it is typically necessary to provide a menu of devices with different threshold voltages to allow for the optimization of performance and power consumption. The ability to tune the threshold voltage by about 150 mV is often required. For devices with geometries in the sub-50-nm gate-length regime, it is very difficult to achieve such a range by merely doping the transistor channel. Disadvantageous channel doping can by avoided by embodiments of the present invention where a first pMOS device has a cladding layer comprised of a first germanium concentration targeting a first threshold voltage while a second pMOS device has a cladding layer comprised of a second germanium concentration targeting a second threshold voltage.
In the embodiments depicted in
CMOS device embodiments 200 and 300 have a gate electrode 213, as shown in
As shown in
As shown in
A method of fabricating a CMOS device on an insulating substrate in accordance with an embodiment of the present invention as shown in
Although the semiconductor film 315 is ideally a silicon film, in other embodiments it can be other types of semiconductor films, such as germanium (Ge), a silicon germanium alloy (SiGe), gallium arsenide (GaAs), InSb, GaP, GaSb, or InP. In an embodiment of the present invention, semiconductor film 315 is an intrinsic (i.e., undoped) silicon film. In other embodiments, semiconductor film 315 is doped to p-type or n-type conductivity with a concentration level between 1×1016-1×1019 atoms/cm3. Semiconductor film 315 can be in-situ doped (i.e., doped while it is deposited) or doped after it is formed on substrate 202 by for example ion-implantation. Doping after formation enables complementary devices 204 and 205 to be fabricated easily on the same substrate. The doping level of the semiconductor substrate film 315 at this point can determine the doping level of the channel region of the device.
In certain embodiments of the present invention, semiconductor substrate film 315 is formed to a thickness approximately equal to the height desired for the subsequently formed semiconductor body or bodies of the fabricated transistor. In an embodiment of the present invention, semiconductor substrate film 315 has a thickness or height of less than 30 nanometers and ideally less than 20 nanometers. In certain embodiments of the present invention, semiconductor substrate region 315 is formed to a thickness enabling the fabricated transistor to be operated in a fully depleted manner for its designed gate length (Lg).
Semiconductor substrate region 315 can be formed on insulator 203 in any well-known method. In one method of forming a silicon-on-insulator substrate, known as the separation by implantation of oxygen (SIMOX) technique. Another technique currently used to form SOI substrates is an epitaxial silicon film transfer technique generally referred to as bonded SOI.
A masking layer 310 is used to define the active regions of the devices in regions 204 and 205. The masking layer can be any well-known material suitable for defining the semiconductor film 315. In an embodiment of the present invention, masking layer 310 is a lithographically defined photo resist. In another embodiment, 310 is formed of a dielectric material that has been lithographically defined and then etched. In a certain embodiment, masking layer can be a composite stack of materials, such as an oxide/nitride stack. As shown in
If desired, a masking can be formed over any regions of the substrate where there is to be no semiconductor cladding layer. As shown, in
In certain embodiments, semiconductor cladding layer 208 is selectively formed on the semiconductor body 206 of the pMOS device 204, as shown in
A gate dielectric layer 212, as shown in
As shown in
Source regions 216 and drain regions 217 for the transistor are formed in semiconductor bodies 206 and 207 on opposite sides of gate electrode 213, as shown in
A method of fabricating a CMOS device on a bulk substrate in accordance with an embodiment of the present invention as shown in
In embodiments of the present invention, well regions of semiconductor substrate 202 are doped to p-type or n-type conductivity with a concentration level between about 1×1016-1×1019 atoms/cm3. Semiconductor substrate 202 can be doped by, for example, ion-implantation enabling both pMOS and nMOS well regions to be fabricated easily on the same substrate. The doping level of the semiconductor substrate 202 at this point can determine the doping level of the channel region of the device.
As shown in
As shown in
In certain embodiments, as shown in
In certain embodiments, once the non-planar semiconductor bodies 206 and 207 are formed on the bulk substrate, the remaining fabrication operations are analogous to those previously described for the embodiments describing a non-planar transistors on an SOI substrate.
Although the invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as particularly graceful implementations of the claimed invention.
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|U.S. Classification||257/288, 257/E21.703, 257/E27.112, 257/E21.642, 257/E21.633|
|Cooperative Classification||H01L29/66795, H01L21/845, H01L21/823807, H01L27/1211, H01L29/785, H01L21/823821, H01L21/823878|
|European Classification||H01L21/84F, H01L27/12B4, H01L21/8238F, H01L29/66M6T6F16F, H01L21/8238U, H01L21/8238C, H01L29/78S|
|Dec 27, 2005||AS||Assignment|
Owner name: INTEL, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DOYLE, BRYAN S.;JIN, BEEN-YIH;KAVALIEROS, JACK T.;AND OTHERS;REEL/FRAME:017396/0581;SIGNING DATES FROM 20051210 TO 20051212