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Publication numberUS20070111376 A1
Publication typeApplication
Application numberUS 11/279,741
Publication dateMay 17, 2007
Filing dateApr 13, 2006
Priority dateApr 29, 2005
Also published asUS9054084, US20130127061
Publication number11279741, 279741, US 2007/0111376 A1, US 2007/111376 A1, US 20070111376 A1, US 20070111376A1, US 2007111376 A1, US 2007111376A1, US-A1-20070111376, US-A1-2007111376, US2007/0111376A1, US2007/111376A1, US20070111376 A1, US20070111376A1, US2007111376 A1, US2007111376A1
InventorsRajendra Pendse
Original AssigneeStats Chippac Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Integrated circuit package system
US 20070111376 A1
Abstract
An integrated circuit package system is provided forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segment of the first bond pad, forming an I/O ring having the first I/O cell, forming an integrated circuit die having the I/O ring, and connecting an external interconnect and the first bond pad.
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Claims(20)
1. An integrated circuit package system comprising:
forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segments of the first bond pad;
forming an I/O ring having the first I/O cell;
forming an integrated circuit die having the I/O ring; and
connecting an external interconnect and the first bond pad.
2. The system as claimed in claim 1 further comprising:
forming a second I/O cell having a second circuitry area and a second bond pad; and
wherein:
forming the I/O ring includes:
forming the I/O ring having the second I/O cell.
3. The system as claimed in claim 1 further comprising:
forming a second I/O cell having a second circuitry area and a second bond pad; and
wherein:
forming the I/O ring includes:
forming the I/O ring having the second I/O cell adjacent to the first I/O cell.
4. The system as claimed in claim 1 further comprising:
forming a second I/O cell having a second circuitry area and a second bond pad; and
wherein:
forming the first I/O cell having the first circuitry area and the first bond pad includes:
forming the first bond pad at a first predetermined position in the I/O ring;
forming the second I/O cell having the second circuitry area and the second bond pad further includes:
forming the second bond pad at a second predetermined position in the I/O ring; and
forming the I/O ring further includes:
forming the I/O ring having the second I/O cell adjacent to the first I/O cell with the first bond pad and the second bond pad not in contact.
5. The system as claimed in claim 1 wherein:
forming the first I/O cell includes:
forming a first tapered area of the first circuitry area; and further comprising:
forming a second I/O cell having a second circuitry area and a second bond pad, the second circuitry area has a second tapered area.
6. An integrated circuit package system comprising:
forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segment of the first bond pad;
forming an I/O ring having the first I/O cell;
forming an integrated circuit die having the I/O ring; and
connecting an external interconnect and the first bond pad.
7. The system as claimed in claim 6 further comprising forming a second I/O cell having a second circuitry area and a second bond pad with the second circuitry area partitioned along the cell length and on opposing perimeter segment of the second bond pad.
8. The system as claimed in claim 6 further comprising forming a second I/O cell having a second circuitry area and a second bond pad, wherein the second I/O cell is formed at the cell length.
9. The system as claimed in claim 6 wherein forming the first I/O cell having the first circuitry area and the first bond pad includes forming the first bond pad in geometric shape comprised of a line segment, an arc, or a combination thereof.
10. The system as claimed in claim 6 further comprising forming a second I/O cell having a second circuitry area and a second bond pad, wherein the second I/O cell is connected to the external interconnect.
11. An integrated circuit package system comprising:
a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segments of the first bond pad;
an I/O ring having the first I/O cell;
an integrated circuit die having the I/O ring; and
an interconnect between an external interconnect and the first bond pad.
12. The system as claimed in claim 11 further comprising:
a second I/O cell having a second circuitry area and a second bond pad; and
wherein:
the I/O ring includes:
the I/O ring having the second I/O cell.
13. The system as claimed in claim 11 further comprising:
a second I/O cell having a second circuitry area and a second bond pad; and
wherein:
the I/O ring includes:
the I/O ring having the second I/O cell adjacent to the first I/O cell.
14. The system as claimed in claim 11 further comprising:
a second I/O cell having a second circuitry area and a second bond pad; and
wherein:
the first I/O cell having the first circuitry area and the first bond pad includes:
the first bond pad at a first predetermined position in the I/O ring;
the second I/O cell having the second circuitry area and the second bond pad further includes:
the second bond pad at a second predetermined position in the I/O ring; and
the I/O ring further includes:
the I/O ring having the second I/O cell adjacent to the first I/O cell such that the first bond pad and the second bond pad not in contact.
15. The system as claimed in claim 11 wherein:
the first I/O cell includes:
a first tapered area of the first circuitry area; and further comprising:
a second I/O cell having a second circuitry area and a second bond pad, the second circuitry area has a second tapered area.
16. The system as claimed in claim 11 wherein:
the first I/O cell with a cell width has the first circuitry area and the first bond pad with the first circuitry area partitioned along the cell length and on opposing perimeter segment of the first bond pad;
the I/O ring having the first I/O cell has a contact;
the integrated circuit die having the I/O ring has a core; and
the interconnect between the external interconnect and the first bond pad is a wire.
17. The system as claimed in claim 16 further comprising a second I/O cell having a second circuitry area and a second bond pad with the second circuitry area partitioned along the cell length and on opposing perimeter segment of the second bond pad.
18. The system as claimed in claim 16 further comprising a second I/O cell having a second circuitry area and a second bond pad, wherein the second I/O cell is formed at the cell length.
19. The system as claimed in claim 16 wherein the first I/O cell having the first circuitry area and the first bond pad includes the first bond pad in geometric shape comprised of a line segment, an arc, or a combination thereof.
20. The system as claimed in claim 16 further comprising a second I/O cell having a second circuitry area and a second bond pad with the interconnect between the second I/O cell and the external interconnect.
Description
    CROSS-REFERENCE TO RELATED APPLICATION(S)
  • [0001]
    This application claims the benefit of U.S. Provisional Patent Application Ser. No. 60/594,705 filed Apr. 29, 2005, and the subject matter thereof is hereby incorporated herein by reference thereto.
  • TECHNICAL FIELD
  • [0002]
    The present invention relates generally to integrated circuits, and more particularly to input/output circuitry.
  • BACKGROUND ART
  • [0003]
    Modern electronics, such as smart phones, personal digital assistants, location based services devices, and enterprise class appliances, are packing more integrated circuits into an ever shrinking physical space with expectations for decreasing cost. As more functions are packed into the integrated circuits and more integrated circuits into the package, integrated circuit packages must continue to provide a mechanism for making electrical interconnection between the integrated circuit die and the leads that are utilized to make electrical interconnections to circuits, power, and ground external to the integrated circuit die. In the early stages of integrated circuit development, there were relatively few connections between the integrated circuit die and the external circuitry.
  • [0004]
    For those early types of integrated circuits, the interconnection to the integrated circuit package was relatively straightforward and generally involved leads arranged around a die cavity to be electrically connected to die pads. There were also relatively few circuits on each integrated circuit die and the circuit operational rates were, by modern day standards, relatively slow. Accordingly, the spacing and configuration of the leads with respect to the die pads did not pose additional difficulty for reliable assembly.
  • [0005]
    Virtually across all applications, there continues to be growing demand for reducing size of the integrated circuits. However, the size reduction often does not come with input/output (I/O) reduction for the integrated circuit to communicate to the external circuitry. As the integrated circuit technology advanced, more circuitry were able to be fabricated in a similar die area so that substantially increased functionality could be accomplished on a given integrated circuit die. The added functionality and increase in the number of circuitry involved generally required a larger number of discrete connections to the external world. As physical sizes decreased and the number of required die pads increased, it was necessary to develop integrated circuit dice and packages that would accommodate connections to a larger number of external connections. Both integrated circuit developers and integrated package manufacturers worked to develop die interconnect systems that would accommodate the higher die pad densities.
  • [0006]
    Numerous technologies have been developed to meet these requirements. Some of the research and development strategies focus on new technologies while others focus on improving the mature technologies. Research and development in the existing technologies may take a myriad of different directions. These approaches may involve improving integrated circuit technology, package technology, or a combination thereof.
  • [0007]
    The design process for integrated circuits usually consists of parallel design of the core circuitry and the I/O cell circuitry with a subsequent integration of the two. The I/O cell circuitry is usually developed in the form of “cell libraries” from which the desired cells for a given integrated circuit design are invoked, “dropped in” and wired to the core circuitry with suitable place and route tools.
  • [0008]
    The I/O cell circuitry, which consists of functional elements such as I/O drivers, electrostatic discharge (ESD) structures, and the bonding pads for external connection to a package, is usually contained within an “I/O cell”. The appropriate I/O cells are then instantiated around the core of the chip by the chip design tools. The pitch of the I/O cells, and thus the pitch of the bonding pads, is an important parameter from the packaging standpoint.
  • [0009]
    For I/O intensive designs, the pitch is very fine (˜50 um or less), making the packaging task more difficult. As such, so-called “staggered designs” have been developed, wherein I/O cells at alternating locations are offset relative to their nearest neighbors, resulting in a greater direct distance between adjacent bonding pads, thereby somewhat alleviating the task of packaging the chip.
  • [0010]
    Unfortunately, this approach also results in a die size penalty approximately equal to two times the amount of die pad offset per side. The die size penalty results in correspondingly fewer die per wafer and higher unit cost per die, which is understandably undesirable.
  • [0011]
    Thus, a need still remains for an integrated circuit package system having improved I/O cells providing reduced die size and providing higher I/O count without placing undesired burden on the packaging process. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
  • [0012]
    Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.
  • DISCLOSURE OF THE INVENTION
  • [0013]
    The present invention provides an integrated circuit package system including forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segment of the first bond pad, forming an I/O ring having the first I/O cell, forming an integrated circuit die having the I/O ring, and connecting an external interconnect and the first bond pad.
  • [0014]
    Certain embodiments of the invention have other aspects in addition to or in place of those mentioned or are obvious from the above. The aspects will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0015]
    FIG. 1 is a plan view of an integrated circuit package system in an embodiment of the present invention;
  • [0016]
    FIG. 2 is a more detailed view of a first I/O ring with a first I/O cell in an embodiment of the present invention;
  • [0017]
    FIG. 3 is a more detailed view of a second I/O ring with a first I/O cell and a second I/O cell in an alternative embodiment of the present invention;
  • [0018]
    FIG. 4 is a more detailed view of a third I/O ring with a first I/O cell and a second I/O cell in another alternative embodiment of the present invention;
  • [0019]
    FIG. 5 is a more detailed view of the first I/O cell of FIG. 4;
  • [0020]
    FIG. 6 is a more detailed view of the second I/O cell of FIG. 4; and
  • [0021]
    FIG. 7 is a flow chart of an integrated circuit package system for manufacture of the integrated circuit package system in an embodiment of the present invention.
  • BEST MODE FOR CARRYING OUT THE INVENTION
  • [0022]
    In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known system configurations, and process steps are not disclosed in detail. Likewise, the drawings showing embodiments of the apparatus are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown greatly exaggerated in the figures. In addition, where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features one to another will ordinarily be described with like reference numerals.
  • [0023]
    The term “horizontal” as used herein is defined as a plane parallel to the conventional integrated circuit surface, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane. The term “on” refers to direct contact among the elements.
  • [0024]
    The term “processing” as used herein includes deposition of material, patterning, exposure, development, etching, cleaning, molding, and/or removal of the material or as required in forming a described structure.
  • [0025]
    Referring now to FIG. 1, therein is shown a plan view of an integrated circuit package system 100 in an embodiment of the present invention. An integrated circuit die 102 includes I/O cells 104 bridging the communication between the external world and a core 106 at the interior of the integrated circuit die 102. The I/O cells 104 are instantiated adjacent to one another along the boundary of the integrated circuit die 102 forming an I/O ring 108. The core 106 includes circuitry, such as digital, analog, memory, or power circuitry, and located within the I/O ring 108.
  • [0026]
    The integrated circuit die 102 mounts on a die paddle 110, wherein the die paddle 110 attaches to tie bars 112. The I/O cells 104 connect to external interconnects 114, such as leads or lead finders, with interconnects 116, such as bond wires. An encapsulation 118, such as an epoxy mold compound (EMC), covers the integrated circuit die 102, the interconnects 116, the die paddle 110, and the tie bars 112. The encapsulation 118 also exposes a portion of the external interconnects 114 for further connections to the next system level (not shown), such as a printed circuit board or another integrated circuit package.
  • [0027]
    For illustrative purpose, the integrated circuit package system 100 has the die paddle 110, although it is understood that the die paddle 110 may not be included. Also of illustrative purpose, the tie bars 112 attach to the die paddle 110, although it is understood that the tie bars 112 may not be included. Further for illustrative purpose, the integrated circuit die 102 is shown as having a single row of the external interconnects 114, although it is understood that the number of rows may be differ. Yet further for illustrative purpose, the interconnects 116 are shown as bond wires, although it is understood that other types of interconnects may be used, such as solder bumps. Yet further for illustrative purpose, the interconnects 116 are shown connecting the I/O cells 104 and the external interconnects 114, although it is understood that the interconnects 116 may form other connections, such as between the I/O cells 104 and the core 106, or the external interconnects 114 and the core 106.
  • [0028]
    As integrated circuit technology continues to shrink, more functions may be packed in the core 106 or the same equivalent function requires less area of the core 106. The integrated circuit technology progression is not always accompanied by a count reduction of the external interconnects 114 for the integrated circuit die 102. As the core 106 continues to shrink or the number of the external interconnects 114 remain the same or increase, the integrated circuit die 102 reaches a condition referred to as I/O limited. This condition exists when the physical dimensions of the I/O cells 104 and the I/O ring 108 limits the minimum die size of the integrated circuit die 102 regardless on the amount of functions in the core 106.
  • [0029]
    Further, connections to the external world do not permit the I/O cells 104 to scale in size as the circuitry in the core 106. Both functional requirements, such as voltage levels or drive current, and reliability requirements, such as electrostatic discharge (ESD), latch up, or undershoot/overshoot immunity, prohibit circuitry size reduction in the I/O cells 104 further increasing the likelihood of reaching an I/O limited condition.
  • [0030]
    Modern electronics are exposed to wider and more aggressive environmental as well operational ranges. This places more emphasis for the integrated circuit die 102 to tolerate a wider range of system environments forcing more circuitry functions to be designed in the I/O cells 104. This also exacerbates the likelihood of forming the integrated circuit die 102 that is I/O limited.
  • [0031]
    Referring now to FIG. 2, therein is shown a more detailed view of a first I/O ring 200 with a first I/O cell 202 in an embodiment of the present invention. The first I/O ring 200 may represent the I/O ring 108 of FIG. 1. The first I/O cell 202 may represent one of the I/O cells 104 of FIG. 1.
  • [0032]
    The first I/O ring 200 depicts the first I/O cell 202 repetitively instantiated next to one another separated by a pitch 204 along a side of an integrated circuit die 206. The first I/O ring 200 is between an edge of the integrated circuit die 206 and a core 208. An interconnect 210, such as a bond wire, connects a bond pad 212 of the first I/O cell 202 and one of the external interconnects 114 shown in FIG. 1. For illustrative purpose, the bond pad 212 is shown in a square geometric shape, although it is understood that the bond pad 212 may be formed in different geometric shapes, such as a circle or a polygon.
  • [0033]
    Shrinking integrated circuit technology push the size of the integrated circuit die 206 and the first I/O ring 200 smaller. Decreasing the first I/O ring 200 for the integrated circuit die 206 that is I/O limited requires a decrease of a cell width 214 of the first I/O cell 202 and the pitch 204. To accommodate the I/O circuitry, a cell length 216 of the first I/O cell 202 increases. Packaging processes impose restrictions on the size of the bond pad 212 for reliable and high yield wire bonding providing a lower bound of the cell width 214, wherein the cell width 214 is about equal to a width of the bond pad 212.
  • [0034]
    A circuitry area 218 of the first I/O cell 202 provides the area for the I/O circuitry. The circuitry area 218 traverses the cell length 216 and surrounds the bond pad 212 along opposing perimeter segments 220, sides, of the bond pad 212. Contacts 222 are at a core side of the first I/O cell 202 for connections to the core 208.
  • [0035]
    Referring now to FIG. 3, therein is shown a more detailed view of a second I/O ring 300 with a first I/O cell 302 and a second I/O cell 304 in an alternative embodiment of the present invention. The second I/O ring 300 may represent the I/O ring 108 of FIG. 1. The first I/O cell 302 and the second I/O cell 304 may represent the I/O cells 104 of FIG. 1 adjacent to each other.
  • [0036]
    The second I/O ring 300 depicts the first I/O cell 302 and the second I/O cell 304 alternately instantiated next to one another along a side of an integrated circuit die 306 and separated by a pitch 308. The second I/O ring 300 is between an edge of the integrated circuit die 306 and a core 310. Interconnects 312, such as bond wires, connect a first bond pad 314 of the first I/O cell 302 and a second bond pad 316 of the second I/O cell 304 to the external interconnects 114 shown in FIG. 1. For illustrative purpose, the first bond pad 314 and the second bond pad 316 are shown in a square geometric shape, although it is understood that the first bond pad 314 and the second bond pad 316 may be formed in different geometric shapes, such as a circle or a polygon.
  • [0037]
    Shrinking integrated circuit technology push the size of the integrated circuit die 306 and the second I/O ring 300 smaller. Decreasing the second I/O ring 300 for the integrated circuit die 306 that is I/O limited requires a decrease of a cell width 318 of the first I/O cell 302 and the second I/O cell 304 as well as the pitch 308. To accommodate the I/O circuitry, a cell length 320 of the first I/O cell 302 and the second I/O cell 304 increases. Packaging processes impose restrictions on the size of the first bond pad 314 and the second bond pad 316 for reliable and high yield wire bonding providing a lower bound of the cell width 318, wherein the cell width 318 is about equal to a width of the first bond pad 314 or the second bond pad 316. To further increase yield and minimize wire crossings, the first bond pad 314 and the second bond pad 316 are staggered lengthwise such that the first bond pad 314 and the second bond pad 316 do not laterally overlap. The staggered nonoverlapped positions of the first bond pad 314 and the second bond pad 316, relative to one another, may be adjusted such that the direct distance between the first bond pad 314 and the second bond pad 316 may be increased.
  • [0038]
    A first circuitry area 322 of the first I/O cell 302 provides the area for the I/O circuitry. The first circuitry area 322 traverses the cell length 320 of the first I/O cell 302 and surrounds the first bond pad 314 along opposing perimeter segments 324, sides, of the first bond pad 314. A second circuitry area 326 of the second I/O cell 304 provides the area for the I/O circuitry. The second circuitry area 326 traverses the cell length 320 of the second I/O cell 304 and surrounds the second bond pad 316 along the perimeter segments 324 on opposite sides of the second bond pad 316. Contacts 328 are at a core side of the first I/O cell 302 and the second I/O cell 304 for connections to the core 310.
  • [0039]
    Referring now to FIG. 4, therein is shown a more detailed view of a third I/O ring 400 with a first I/O cell 402 and a second I/O cell 404 in another alternative embodiment of the present invention. The third I/O ring 400 may represent the I/O ring 108 of FIG. 1. The first I/O cell 402 and the second I/O cell 404 may represent the I/O cells 104 of FIG. 1 adjacent to each other.
  • [0040]
    The third I/O ring 400 depicts the first I/O cell 402 and the second I/O cell 404 alternately instantiated next to one another along a side of an integrated circuit die 406 and separated by a pitch 408. The third I/O ring 400 is between an edge of the integrated circuit die 406 and a core 410. Interconnects 412, such as bond wires, connect a first bond pad 414 of the first I/O cell 402 and a second bond pad 416 of the second I/O cell 404 to the external interconnects 114 shown in FIG. 1. For illustrative purpose, the first bond pad 414 and the second bond pad 416 are shown in a square geometric shape, although it is understood that the first bond pad 414 and the second bond pad 416 may be formed in different geometric shapes, such as a circle or a polygon.
  • [0041]
    Shrinking integrated circuit technology push the size of the integrated circuit die 406 and the third I/O ring 400 smaller. Decreasing the third I/O ring 400 for the integrated circuit die 406 that is I/O limited requires a decrease of a cell width 418 of the first I/O cell 402 and the second I/O cell 404 as well as the pitch 408. To accommodate the I/O circuitry, a cell length 420 of the first I/O cell 402 and the second I/O cell 404 increases. Packaging processes impose restrictions on the size of the first bond pad 414 and the second bond pad 416 for reliable and high yield wire bonding providing a lower bound of the cell width 418, wherein the cell width 418 is a width of the first bond pad 414 or the second bond pad 416. To further increase yield and minimize wire crossings, the first bond pad 414 and the second bond pad 416 are staggered lengthwise such that the first bond pad 414 and the second bond pad 416 do not laterally overlap.
  • [0042]
    The first I/O cell 402 has a first circuitry area 422 for the I/O circuitry, wherein the first circuitry area 422 has a first tapered area 424. The first circuitry area 422 traverses the cell length 420 with the first tapered area 424 along a side of the first bond pad 414 towards the edge of the integrated circuit die 406.
  • [0043]
    The second I/O cell 404 has a second circuitry area 426 for the I/O circuitry, wherein the second circuitry area 426 has a second tapered area 428. The second circuitry area 426 traverses the cell length 420 with the second tapered area 428 on the core side of the second bond pad 416.
  • [0044]
    The location of the first tapered area 424 provides space for a portion of the second bond pad 416. The location of the second tapered area 428 provides space for a portion the first bond pad 414. The complementary tapered sections and adjacent bond pads allow for a higher I/O density in the third I/O ring 400. Contacts 430 are at the core side of the first I/O cell 402 and the second I/O cell 404 for connections to the core 410.
  • [0045]
    Referring now to FIG. 5, therein is shown a more detailed view of the first I/O cell 402 of FIG. 4. The first bond pad 414 is wider than the first circuitry area 422. The first tapered area 424 is on a perimeter segment 502, a side, of the first bond pad 414 nearest the edge side of the integrated circuit die 406. A recess 504 of the first tapered area 424 provides a space for a portion of the second bond pad 416 shown in FIG. 4 for the second I/O cell 404 shown in FIG. 4 adjacent to the first I/O cell 402.
  • [0046]
    The first bond pad 414 may be formed with the integrated circuit technology used to fabricate the integrated circuit die 406 of FIG. 4. The first bond pad 414 may be optionally formed with the post-passivation processing of the integrated circuit die 406 providing the surface area needed for reliable wire bonding while further reducing a width of the first circuitry area 422.
  • [0047]
    Referring now to FIG. 6, therein is shown a more detailed view of the second I/O cell 404 of FIG. 4. The second bond pad 416 is wider than the second circuitry area 426. The second tapered area 428 is on a perimeter segment 602, a side, of the second bond pad 416 nearest the core side of the integrated circuit die 406. A recess 604 of the second tapered area 428 provides a space for a portion of the first bond pad 414 shown in FIG. 4 for the first I/O cell 402 shown in FIG. 4 adjacent to the second I/O cell 404.
  • [0048]
    The second circuitry area 426 on the edge side of the second bond pad 416 may optionally not have circuitry or the second bond pad 416 may be optionally formed at the edge side of the second I/O cell 404. The second bond pad 416 may be optionally formed with the post-passivation processing of the integrated circuit die 406 providing the surface area needed for reliable wire bonding while further reducing a width of the second circuitry area 426.
  • [0049]
    Referring now to FIG. 7, therein is shown a flow chart of an integrated circuit package system 700 for manufacture of the integrated circuit package system 100 in an embodiment of the present invention. The system 700 includes forming a first I/O cell having a first circuitry area and a first bond pad with the first circuitry area partitioned along a cell length and on opposing perimeter segments of the first bond pad in a block 702; forming an I/O ring having the first I/O cell in a block 704; forming an integrated circuit die having the I/O ring in a block 706; and connecting an external interconnect and the first bond pad in a block 708.
  • [0050]
    It has been discovered that the present invention thus has numerous aspects.
  • [0051]
    It has been discovered that the present invention addresses the problem of the die size penalty for I/O limited integrated circuits through circuit partition in the I/O cell relative to the bond pad.
  • [0052]
    An aspect of the present invention is that the circuit partition to both opposing sides of the I/O cell bond pad allows additional degree of freedom for wire bonding with a decrease the width and increase the length of the I/O cell. This additional flexibility lowers the I/O limited threshold allowing smaller die size and reducing overall cost of the integrated circuit. Smaller die size improves wafer yield to further reduce the cost of the integrated circuits.
  • [0053]
    Another aspect of the present invention improves integrated circuit package system with I/O limited integrated circuits with staggered bond pad placement of adjacent I/O cells and the circuitry partition on both sides of the bond pad. The staggered location also minimizes wire crossing.
  • [0054]
    Yet another aspect of the present invention addresses the problem of the die size penalty while retaining the advantage of the staggered design, i.e. increased spacing of adjacent bond pads. It further offers the possibility of making the bond pad size bigger relative to the circuit area, which results in additional simplification of the package structure and process.
  • [0055]
    Yet another aspect of the present invention is the flexibility to create the bond pad for the wire bonding with the semiconductor process used to fabricate the integrated circuit or a post passivation process. This allows additional flexibility to reduce the I/O cell dimension to lower the I/O limiting condition threshold providing higher yield and lower cost.
  • [0056]
    Thus, it has been discovered that the integrated circuit package system method of the present invention furnishes important and heretofore unknown and unavailable solutions, capabilities, and functional aspects for reducing integrated circuit dimensions and lowering cost in systems. The resulting processes and configurations are straightforward, cost-effective, uncomplicated, highly versatile and effective, can be implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing stacked integrated circuit package in packaged devices.
  • [0057]
    While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4947233 *Oct 26, 1987Aug 7, 1990Nec CorporationSemi-custom LSI having input/output cells
US6008532 *Oct 23, 1997Dec 28, 1999Lsi Logic CorporationIntegrated circuit package having bond fingers with alternate bonding areas
US6028449 *Aug 5, 1997Feb 22, 2000Lsi Logic CorporationIntegrated circuit I/O buffer having pull-up to voltages greater than transistor tolerance
US6807078 *Aug 26, 2002Oct 19, 2004Stmicroelectronics LimitedSemiconductor input/output circuit arrangement
US6833620 *Nov 28, 2000Dec 21, 2004Ati Technologies, Inc.Apparatus having reduced input output area and method thereof
US6858945 *Jan 31, 2003Feb 22, 2005Broadcom CorporationMulti-concentric pad arrangements for integrated circuit pads
US7071561 *Jun 8, 2004Jul 4, 2006Taiwan Semiconductor Manufacturing Company, Ltd.Semiconductor device and method of manufacture thereof with two or more bond pad connections for each input/output cell
US20040016980 *Jul 21, 2003Jan 29, 2004Nec Electronics CorporationSemiconductor integrated device
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7594198 *Feb 27, 2007Sep 22, 2009Taiwan Semiconductor Manufacturing Co., Ltd.Ultra fine pitch I/O design for microchips
US7808117May 16, 2006Oct 5, 2010Freescale Semiconductor, Inc.Integrated circuit having pads and input/output (I/O) cells
US8115321 *Apr 30, 2009Feb 14, 2012Lsi CorporationSeparate probe and bond regions of an integrated circuit
US8466566 *Apr 1, 2011Jun 18, 2013Advantest CorporationSemiconductor device, method for manufacturing of semiconductor device, and switching circuit
US8519551 *Jun 18, 2010Aug 27, 2013Fujitsu Semiconductor LimitedSemiconductor device with I/O cell and external connection terminal and method of manufacturing the same
US9171812 *Nov 25, 2013Oct 27, 2015Amkor Technology, Inc.Semiconductor device having conductive pads with neck-down portions to prevent solder reflow
US20070267748 *May 16, 2006Nov 22, 2007Tran Tu-Anh NIntegrated circuit having pads and input/output (i/o) cells
US20070267755 *May 16, 2006Nov 22, 2007Vo Nhat DIntegrated circuit having pads and input/output (i/o) cells
US20080204113 *Feb 27, 2007Aug 28, 2008Taiwan Semiconductor Manufacturing Co., Ltd.Ultra fine pitch I/O design for microchips
US20090051050 *Aug 24, 2007Feb 26, 2009Actel Corporationcorner i/o pad density
US20100252830 *Jun 18, 2010Oct 7, 2010Fujitsu Semiconductor LimitedSemiconductor device and manufacturing method thereof
US20100276816 *Apr 30, 2009Nov 4, 2010Anwar AliSeparate probe and bond regions of an integrated circuit
US20120074577 *Apr 1, 2011Mar 29, 2012Advantest CorporationSemiconductor device, method for manufacturing of semiconductor device, and switching circuit
US20140239493 *Feb 21, 2014Aug 28, 2014Renesas Electronics CorporationSemiconductor chip and semiconductor device
Classifications
U.S. Classification438/106, 257/678, 257/E27.11
International ClassificationH01L21/00, H01L23/02
Cooperative ClassificationH01L2924/181, H01L2224/05554, H01L2224/04042, H01L24/06, H01L2224/49171, H01L2224/85399, H01L24/49, H01L2924/014, H01L2924/14, H01L2224/48247, H01L27/11898, H01L2224/49431, H01L2924/01082, H01L2224/05599, H01L2924/01033, H01L2924/00014, H01L24/03, H01L23/488
European ClassificationH01L24/49, H01L24/06, H01L27/118P
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