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Publication numberUS20070138628 A1
Publication typeApplication
Application numberUS 11/304,084
Publication dateJun 21, 2007
Filing dateDec 15, 2005
Priority dateDec 15, 2005
Also published asUS8860195, US20090294957
Publication number11304084, 304084, US 2007/0138628 A1, US 2007/138628 A1, US 20070138628 A1, US 20070138628A1, US 2007138628 A1, US 2007138628A1, US-A1-20070138628, US-A1-2007138628, US2007/0138628A1, US2007/138628A1, US20070138628 A1, US20070138628A1, US2007138628 A1, US2007138628A1
InventorsKen Lam
Original AssigneeLam Ken M
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Apparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US 20070138628 A1
Abstract
An apparatus and method for incorporating discrete passive components into an integrated circuit package. A first surface of a substrate is coated with a material to mechanically protect the first surface. A first metal layer and then an insulating layer are formed on a second surface of the substrate. Selected areas are removed from the insulating and a second metal layer is formed over the insulating layer and the exposed metal layer. Selected areas of the second metal layer are removed to form a plurality of structures, including at least one of a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached. An electronic component may be attached to at least one of the structures. The resulting integrated circuit die may be incorporated into an electronic package.
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Claims(43)
1. A method of fabrication comprising:
a) providing a substrate with a first surface having a passivation layer; and
b) building a plurality of structures on a second surface of the substrate, the plurality of structures including at least one structure to which an electronic component may be attached, the plurality of structures including at least one of the following:
i) a wirebonding pad;
ii) a solder-bonding pad;
iii) a device interconnect circuit; or
iv) an attach pad to which an electronic component can be attached.
2. The method of claim 1 wherein building the plurality of structures includes forming a metal layer on the second surface of the substrate.
3. The method of claim 2 wherein building the plurality of structures includes forming an insulating layer on the metal layer.
4. The method of claim 3 wherein building the plurality of structures includes removing selected areas of the insulating layer, thereby exposing portions of the first metal layer.
5. The method of claim 4 wherein building the plurality of structures includes forming a second metal layer over the insulating layer and the exposed portions of the first metal layer.
6. The method of claim 5 wherein building the plurality of structures includes removing selected areas of the second metal layer to form the plurality of structures.
7. The method of claim 1 further comprising attaching the substrate to an electronic package.
8. The method of claim 7 wherein the package is a multi-chip module package.
9. The method of claim 1 further comprising coating the first surface with a material to mechanically protect the first surface.
10. The method of claim 1 further comprising attaching the electronic component to the attach pad.
11. The method of claim 10 wherein the electronic component is either an active or passive component.
12. The method of claim 1 wherein the substrate is a semiconductor substrate.
13. The method of claim 1 wherein the second surface is silicon or gallium arsenide.
14. An electronic package comprising:
a) a substrate;
b) an integrated circuit die coupled to a first surface of the substrate, a first surface of the integrated circuit die having a means for coupling to the first surface of the substrate, at least one first electronic component attached to the first surface of the integrated circuit die, at least one structure attached to a second surface of the integrated circuit die, the at least one structure configured to be coupled to a second electronic component.
15. The electronic package of claim 14 wherein the at least one structure attached to the second surface includes at least one of the following:
a) a wirebonding pad;
b) a solder-bonding pad;
c) a device interconnect circuit; or
d) an attach pad to which the second electronic component may be coupled.
16. The electronic package of claim 15 further comprising the second electronic component attached to the at least one structure.
17. The electronic package of claim 16 further comprising the second electronic component coupled to the substrate.
18. The electronic package of claim 17 wherein the second electronic component is coupled to the substrate by a wirebond.
19. The electronic package of claim 16 wherein the second electronic component is either an active or passive component.
20. The electronic package of claim 14 wherein the electronic package is a multi-chip module package.
21. The electronic package of claim 14 wherein the substrate is a printed circuit board.
22. An electronic package comprising:
a) a substrate;
b) a flip chip attached to a first surface of the substrate, a first surface of the flip chip having a means for attachment to the first surface of the substrate, at least one first electronic component attached to the first surface of the flip chip, at least one structure attached to a second surface of the flip chip, the at least one structure configured to be coupled to a second electronic component.
23. The electronic package of claim 14 wherein the at least one structure attached to the second surface includes at least one of the following:
a) a wirebonding pad;
b) a solder-bonding pad;
c) a device interconnect circuit; or
d) an attach pad to which the second electronic component may be coupled.
24. The electronic package of claim 23 further comprising a second electronic component attached to the at least one structure.
25. The electronic package of claim 23 wherein the second electronic component is either an active or passive component.
26. The electronic package of claim 22 wherein the electronic package is a multi-chip module package.
27. The electronic package of claim 22 wherein the substrate is a printed circuit board.
28. A semiconductor device comprising:
a) a first substrate having a first surface and a second surface;
b) a passivation layer on the first surface of the first substrate; and
c) at least one structure attached to the second surface of the first substrate, the at least one structure configured to be coupled to an electronic component.
29. The semiconductor device of claim 28 wherein the at least one structure includes at least one of the following:
a) a wirebonding pad;
b) a solder-bonding pad;
c) a device interconnect circuit; or
d) an attach pad to which the electronic component may be attached.
30. The semiconductor device of claim 28 further comprising a means for attachment to a second substrate, the means for attachment coupled to the first surface of first substrate.
31. The semiconductor device of claim 30 wherein the second substrate is attached to an electronic package.
32. The semiconductor device of claim 30 further comprising at least one electronic component attached to the at least one structure.
33. The semiconductor device of claim 28 wherein the first substrate is a semiconductor substrate.
34. The semiconductor device of claim 28 wherein the semiconductor substrate is silicon or gallium arsenside.
35. The semiconductor device of claim 32 wherein the at least one electronic component is an active or passive component.
36. The semiconductor device of claim 30 wherein the second substrate is a semiconductor substrate.
37. A method of integrated circuit device packaging comprising:
a) providing a substrate;
b) coupling a first surface of an integrated circuit die to the substrate, the first surface coupled to at least one electronic component; and
c) attaching at least one electronic component to at least one structure on a second surface of the integrated circuit die.
38. The method of claim 37 wherein the first surface of the integrated circuit die is coupled to the substrate by solder balls.
39. The method of claim 37 wherein the first surface of the integrated circuit die is coupled to the substrate by wirebond.
40. The method of claim 37 further comprising coupling the at least one electronic component to the substrate.
41. The method of claim 37 wherein the at least one electronic component is coupled to the substrate by a wirebond.
42. The method of claim 37 wherein the electronic component is either an active or passive component.
43. The method of claim 37 wherein the substrate is a printed circuit board.
Description
TECHNICAL FIELD

The present invention generally concerns fabrication of semiconductor devices, particularly semiconductor devices incorporated in integrated circuit packages.

BACKGROUND

Miniaturization of integrated circuit (IC) packages which may be incorporated in portable consumer products such as cellular phones, and mobile or laptop computers, has become increasingly important. One approach to miniaturization is the use of multi-chip modules where multiple chips having related functions are incorporated in a single package.

Single packages may also include stacked chips, in which chips are vertically stacked on top of each other. A potential drawback to using stacked die techniques is that no interconnection exists on the surfaces of the stacked die; the die interconnect is limited to die-to-die and die-to-substrate interconnections. Therefore, the IC die count is typically limited to one die per attach surface. It is not feasible to attach discrete electronic components to these surfaces since they typically require solderable attachment lands and interconnect circuitry or a noble metal surface for low contact resistance connections.

As such, it would be desirable to improve the manner in which discrete electronic components are incorporated in IC packages, such as utilizing die surfaces not conventionally used for die interconnections.

SUMMARY

In one embodiment, a method of fabrication comprises providing a substrate with a first surface having a passivation layer. At least one structure is built on a second surface of the substrate; an electronic component is to be attached to at least one structure. The structures that may be built include a wirebonding pad, a solder-bonding pad, a device interconnect circuit, or an attach pad to which an electronic component may be attached.

Another embodiment is an electronic package. The electronic package comprises a substrate which is coupled to a first surface of an integrated circuit die. The first surface of the integrated circuit die has means for coupling to the first surface of the substrate and has at least one first electronic component attached to the first surface of the integrated circuit die. At least one structure is attached to a second surface of the integrated circuit die.

Yet another embodiment is an electronic package comprising a substrate which is coupled to a flip chip. At least one first electronic component and means for coupling the flip chip to the substrate is attached to a first surface of the flip chip. At least one structure is attached to a second surface of the flip chip.

In another embodiment, a semiconductor device comprises a substrate having a first surface and a second surface, a passivation layer on the first surface of the substrate, and at least one structure attached to the second surface of the substrate. The structure is configured to be coupled to an electronic component.

In yet another embodiment, a method of integrated circuit device packaging comprises providing a substrate, coupling a first surface of an integrated circuit die to the substrate, and attaching at least one electronic component to at least one structure on a second surface of the integrated circuit die. The first surface of the integrated circuit die is coupled to at least one electronic component.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a-1 b are flowcharts of a fabrication process in an exemplary embodiment of the invention.

FIGS. 2 a -2 j are diagrams showing stages of fabrication in an exemplary embodiment of the invention.

FIG. 3 is a view of a chip fabricated in accordance with steps shown in FIGS. 2 a-2 j attached to a substrate.

FIG. 4 is an overhead plan of a multi-chip module incorporating chips fabricated in accordance with steps shown in FIGS. 2 a-2 j.

FIG. 5 is a side view of a multi-chip module incorporating chips fabricated in accordance with steps shown in FIGS. 2 a-2 j.

DETAILED DESCRIPTION

In FIG. 1 a, an exemplary process for fabricating a semiconductor device with circuitry on both surfaces of the device (such that one surface connects the device to an electronic package's substrate (such as a printed circuit board (“PCB”) and another surface may be used to attach discrete electronic components) is shown. A wafer is provided with fabricated circuitry on a first surface of the wafer (block 100). The wafer may be made of any suitable semiconductor material, such as silicon or gallium arsenide, used in the art. It should also be appreciated that any substrate (such as silicon on an insulator), or semiconductor substrate, including the wafer, may be used in various embodiments. The device substrate should not be confused with the same substrate often used to generally label PCBs. The fabricated devices on the first surface are produced through conventional semiconductor manufacturing methods.

A removable layer, for mechanical protection for the first surface of the semiconductor substrate, such as photoresist or dry film, is deposited over a top passivation layer on the first surface of the wafer (block 102), where the fabricated circuitry is located. In FIG. 2 a, the wafer 14 has a first surface 80 and a second surface 82, with a passivation layer 12 and a layer of protective material 10 on a first surface of the wafer 80, which also contains the fabricated devices (not shown here). The layer of protective material 10 is typically 1 to 10 microns thick and provides mechanical protection to the passivation layer 12, which in turn protects the active device circuitry. The layer of protective material is formed using methods well-known to those of skill in the art.

The second surface of the wafer is then metallized (FIG. 1 a, block 104). In FIG. 2 b, the wafer 14 is turned “upside down” and a metal layer 16 is formed over the second surface 82 of the wafer 14. In one embodiment, the second surface 82 of the wafer 14 is blanket metallized by standard metal deposition processes, such as evaporation or chemical vapor deposition (“CVD”), sputtering, and plating. The resulting metal layer 16 is typically about 0.1 micron to 10 microns thick. The metal layer 16 provides RF shielding and wirebonding functions. The metal layer 16 may be a single layer, for example, aluminum (Al), or may be formed of multiple layers, using metals such as titanium tungsten-god (TiW—Au), titanium-gold (Ti—Au), chromium-gold (Cr—Au), titanium tungsten-nickel-gold (Ti—Ni—Au), titanium-nickel-gold (Ti—Ni—Au), titanium-copper-nickel-gold (Ti—Cu—Ni—Au), titanium-tungsten-copper-nickel-silver (TiW—Cu—Ni—Ag), etc. Metal layer 16 choices may be selected based on the mechanism used to attach components to the semiconductor device fabricated on the wafer. For example, the use of gold, silver, and/or palladium is suitable for wire-bonding and the use of nickel and copper is suitable for soldering and electrical conductivity. Nickel is a good diffusion barrier. Titanium, titanium tungsten, and chromium provide adhesion of the metal film stack to the wafer.

An insulating layer is formed over the metal layer (FIG. 1 a, block 106). In FIG. 2 c, an insulating film 18, such as polyimide, benzocyclobutene (BCB), etc., is formed over the metal layer 16. The insulating film 18 is typically about 2 to 15 microns thick. The insulating film 18 is formed using methods well-known to those of skill in the art. This insulating film 18 may be either photo-definable or standard non-photo-sensitive film.

In the case of using a non-photo-sensitive insulating film, a photosensitive material, such as photoresist, is deposited over the insulating film layer (FIG. 1 a, block 108). In FIG. 2 d, a layer of photosensitive film (typically 1 to 10 microns), such as photoresist 20, is deposited over the insulating film 18. This layer 20 of photoresist is patterned and developed using methods well-known to those of skill in the art.

A mask is placed over the photosensitive material, such as photoresist, and then exposed and etched away (FIG. 1 a, block 110). The insulating film layer that is now exposed is removed using wet etch or dry etch techniques. The remaining photosensitive material is also removed using methods well-known to those of skill in the art (FIG. 1 a, block 110). In FIG. 2 e, the second surface 82 of the wafer 14 has a patterned insulating film layer 18 remaining on the metal layer 16 after the removal of the layer of photoresist. The method just described uses a negative acting photoresist. A positive acting photoresist can also be used to achieve the same goal.

The remaining insulating film and exposed metal layer is covered with a second metal layer (FIG. 1 a, block 112). In one embodiment, the surface is blanket metallized; in other embodiments, other metal deposition processes, such as sputtering and plating, may also be employed. In FIG. 2 f, the second metal layer 22 covers the insulating film 18 and the exposed metal layer 16. The second metal layer is typically about 0.1 to 10 microns thick. The second metal layer 22 may be a single layer, for example, aluminum (Al), or may be formed of multiple layers, using metals such as titanium tungsten-god (TiW—Au), titanium-gold (Ti—Au), chromium-gold (Cr—Au), titanium tungsten-nickel-gold (Ti—Ni—Au), titanium-nickel-gold (Ti—Ni—Au), titanium-copper-nickel-gold (Ti—Cu—Ni—Au), titanium-tungsten-copper-nickel-silver (TiW—Cu—Ni—Ag), etc. In other embodiments, the metal layer 22 may be formed of metal which are wirebondable or solderable (such as copper, silver, etc.) or have a diffusion barrier (e.g., nickel).

A layer of photosensitive material, such as photoresist, is deposited over the second metal layer (FIG. 1 b, block 116). In FIG. 2 g, a photosensitive film layer 24 has been deposited on the second metal layer 22. The photosensitive film layer 24 is typically about 1 to 10 microns thick. This layer 24 is patterned and developed using methods well-known to those of skill in the art.

A mask is placed over the photosensitive material, such as photoresist, and then exposed and developed. The metal in the developed areas is then etched away (FIG. 1 b, block 118). The remaining photosensitive material is also removed using methods well-known to those of skill in the art (FIG. 1, block 118). In FIG. 2 h, the exposed areas of the second metal layer which were not protected by the mask are etched away, leaving only the patterned second metal layer. These remaining areas of the second metal layer 22 form interconnect circuitry, bond pads, discrete passive component attach pads, etc.

In one embodiment shown in FIG. 2 i, the metal circuitry on the second surface 82 of the wafer 14 may be protected by an optional coating 26 of insulation, such as polyimide, BCB, etc. The coating 26 may be deposited and then patterned (for instance, by forming, patterning, developing, and etching photoresist in a manner known to those of skill in the art) to form the desired coating 26.

The layer of protective material initially formed over the passivation layer on the first surface of the wafer is removed using methods well-known to those of skill in the art. With reference to FIG. 2 j, the passivation layer 12 is now the top-most layer on the first surface 80 of the wafer 14.

The “build-up” fabrication discussed above in FIGS. 1 a-1 b and 2 a-2 j may be carried out at a substrate level. Where the substrate is a wafer, the wafer may be subsequently singulated at package assembly, forming IC dies. The IC dies created from the fabrication process described in FIGS. 1 a-1 b and 2 a-2 j (including other embodiments where the substrate is not a wafer) serve as the semiconductor device that will be implemented in the IC device package. The IC dies are used to form flip chips or wafer level chip size packages (CSP), although other types of chips may be used.

With reference to FIG. 3, an exemplary flip-chip 36 with fabricated structures on the bare silicon side of the chip 36 is shown attached to an electronic package's substrate, here a PCB, such as a package 4-layer laminate substrate 34. (The chip 36 may have components on the front, or passivation, side of the chip in other embodiments; however, these are not pictured in this embodiment.) The chip 36 is attached to the 4-layer laminate substrate 34 with solder balls 32. The area of fabrication 50 on the silicon side of the chip 36 includes a metal layer 16 which provides RF shielding and/or circuit grounding. Components 30, 28 may be mounted on attach pads 70, 68 formed over the metal layer 16. Component 30 is wirebonded 54 to metal bond pad 52 while component 28 is also wirebonded 56, 60 to metal bond pads 52, 22. Metal bond pad 52 also serves as an interconnect. Component 28 is also wirebonded 66 to a bond pad 58 on the package substrate 34. Leads 62, 64 connect the metal layer 16 to substrate connection pad 58, or ground, and thus provide ground-signal-ground shielding.

Various components can be attached to the attach pads. The active and passive components which may be attached include, but are not limited to, crystals, transceiver ICs, power management ICs, EEPROM ICs, switches, baluns, capacitors, etc. The components may be attached in a variety of ways, including soldering and attaching with a conductive epoxy. These components may be attached and interconnected at wafer level prior to wafer dicing, or attached after saw singulation, or may be attached and interconnected at package assembly, after the chip has been attached to the product substrate.

FIG. 4 shows an exemplary plan view of a multi-chip module using IC chips 36, in this case, flip-chips, with fabricated structures on the bare silicon side of the chip. In this exemplary embodiment, a number of different components have been attached to the chips 36 mounted on the four-layer substrate 34. These components include a crystal 48, a power management IC 46, a balun 44, a switch 42, a transceiver IC 38, and an EEPROM IC 40. In other embodiments, any number of different components and arrangements may be employed and may be mounted on chips other than flip-chips; a wide range of package substrates, with different numbers of layers which may be made of various materials may also be employed. A side elevation of this package is shown in FIG. 5 (with some passives omitted for clarity). In this exemplary embodiment, the height of the package 72, including the substrate and the attached components does not exceed 1.5 mm.

Using the approaches described above, the size of electronic packages may be reduced. This is particularly important given the trend towards miniaturization, especially for portable products such as cellular phones.

While the preceding description has described specific embodiments, it will be evident to a skilled artisan that various changes and modifications can be made to these embodiments. For example, metal or conductive layers other than those described and shown may be used (e.g., platinum, tantalum, etc.). A skilled artisan will recognize that such conductive layers may be deposited or formed by methods and techniques other than those described herein (e.g., copper may be formed by a dual damascene technique known to those of skill in the art). The specification and drawings, therefore, are to be regarded in an illustrative rather than a restrictive sense.

Referenced by
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US7932590Jul 13, 2006Apr 26, 2011Atmel CorporationStacked-die electronics package with planar and three-dimensional inductor elements
US8258599Jul 11, 2006Sep 4, 2012Atmel CorporationElectronics package with an integrated circuit device having post wafer fabrication integrated passive components
US8324023Apr 15, 2011Dec 4, 2012Atmel CorporationStacked-die electronics package with planar and three-dimensional inductor elements
US8426963 *Apr 11, 2011Apr 23, 2013Delta Electronics, Inc.Power semiconductor package structure and manufacturing method thereof
US8743207 *Jul 27, 2010Jun 3, 2014Flir Systems Inc.Infrared camera architecture systems and methods
US8860195Aug 3, 2009Oct 14, 2014Atmel CorporationApparatus and method for increasing the quantity of discrete electronic components in an integrated circuit package
US20110316160 *Sep 7, 2011Dec 29, 2011Infineon Technologies AgSemiconductor Arrangement, Semiconductor Module, and Method for Connecting a Semiconductor Chip to a Ceramic Substrate
US20120026337 *Jul 27, 2010Feb 2, 2012Flir Systems, Inc.Infrared camera architecture systems and methods
US20120181706 *Apr 11, 2011Jul 19, 2012Jian-Hong ZengPower semiconductor package structure and manufacturing method thereof
Legal Events
DateCodeEventDescription
Feb 28, 2006ASAssignment
Owner name: ATMEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAM, KEN M.;REEL/FRAME:017642/0440
Effective date: 20051213