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Publication numberUS20070141830 A1
Publication typeApplication
Application numberUS 11/652,310
Publication dateJun 21, 2007
Filing dateJan 11, 2007
Priority dateJan 18, 2000
Also published asUS7253521, US7262130, US7368378, US7402516, US20050023697, US20060246733, US20060292857
Publication number11652310, 652310, US 2007/0141830 A1, US 2007/141830 A1, US 20070141830 A1, US 20070141830A1, US 2007141830 A1, US 2007141830A1, US-A1-20070141830, US-A1-2007141830, US2007/0141830A1, US2007/141830A1, US20070141830 A1, US20070141830A1, US2007141830 A1, US2007141830A1
InventorsKie Ahn, Leonard Forbes
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods for making integrated-circuit wiring from copper, silver, gold, and other metals
US 20070141830 A1
Abstract
Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, copper typically requires use of a diffusion barrier to prevent it from contaminating other parts of an integrated circuit. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some advantages of using copper. Moreover, conventional methods of forming the copper wiring are costly and time consuming. Accordingly, the inventors devised one or more exemplary methods for making integrated-circuit wiring from materials, such as copper-, silver-, and gold-based metals. One exemplary method removes two or more masks in a single removal procedure, forms a low-resistance diffusion barrier on two or more wiring levels in a single formation procedure, and fills insulative material around and between two or more wiring levels in a single fill procedure. This and other embodiments hold the promise of simplifying fabrication of integrated-circuit wiring dramatically.
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Claims(47)
1. A method of making integrated circuits, comprising:
forming a first mask layer having a first plurality of openings in an insulator layer having a specified vertical thickness on a semiconductor substrate having at least one transistor structure, at least one of the plurality of openings extending completely through the insulator layer to selected contact portions of the transistor;
forming a first conductive material layer on the first mask layer and inside each one of the first plurality of openings;
forming a second mask layer having a second plurality of openings, at least one openings exposing a portion of the first conductive material layer;
forming a second conductive material layer disposed upon the first conductive material and extending upward to a top surface of the second mask layer;
forming a third mask layer having a third plurality of openings, at least one opening exposing a portion of the second conductive material layer; and
forming a third conductive material layer disposed upon the second conductive material and extending upward to a top surface of the third mask layer.
2. The method of claim 1, wherein forming the first and second plurality of openings includes at least one opening having a length at least five times longer than a width to form a trench.
3. The method of claim 2, wherein forming a trench includes the trench having a depth that does not extend completely through the mask layer, and having a horizontal extent to contact at least one of the plurality of openings extending completely through the insulator layer to selected contact portions of the transistor.
4. The method of claim 1, wherein the insulator layer has a thickness of zero.
5. The method of claim 1, wherein forming the first mask layer includes coating the semiconductor substrate and insulator layer with a photosensitive polymer layer.
6. The method of claim 1, wherein forming the first mask layer includes removing an exposed portion of the insulator layer.
7. The method of claim 1, wherein forming the first mask layer includes coating the semiconductor substrate and insulator layer with a first photosensitive polymer layer, exposing the first photosensitive polymer layer to a first optical pattern of light and dark areas, developing the first pattern to form voids in the first photosensitive layer, baking the first photosensitive layer, coating the first photosensitive layer with a second photosensitive polymer layer, exposing the second photosensitive polymer layer to a second pattern of light and dark areas different from the first pattern, developing the second pattern to form voids in the second photosensitive layer, and baking the second photosensitive layer to form the first mask layer.
8. The method of claim 1, wherein forming the openings extending completely through the insulator layer to selected contact portions of the transistor includes forming a diffusion barrier on the selected contact portions of the transistor between the transistor contact areas and the first conductive material layer.
9. The method of claim 1, wherein the second plurality of openings is at least partially different from the first plurality of openings.
10. The method of claim 1, wherein the second plurality of openings has a diffusion barrier formed prior to the formation of the second conductive material layer disposed upon the first conductive material.
11. The method of claim 1, further including forming a plating seed layer after the formation of the first plurality of openings and prior to the formation of the first conductive material layer.
12. The method of claim 1, wherein further forming the first conductive material layer includes electroplating to a thickness approximately equal to the first mask layer.
13. The method of claim 1, further including removing substantially all of the first, second and third mask layers resulting in at least some portions of the first second and third conductive material layers being surrounded by a gas on a top, a bottom and side areas.
14. The method of claim 13, further including forming a diffusion barrier layer on substantially all portions of the first, second and third conductive materials not contacting one of the selected portions of the transistor, one of the other conductive material layers, and the insulator layer.
15. The method of claim 14, further including forming a dielectric layer surrounding substantially all portions of the first, second and third conductive materials not contacting one of the selected portions of the transistor, one of the other conductive material layers, and the insulator layer.
16. The method of claim 13, wherein the first, second and third mask layers are formed of a photosensitive polymer layer and the method of removing substantially all of the first, second and third mask layers includes an oxygen plasma operation.
17. The method of claim 16, wherein the oxygen plasma removes the first, second and third mask layers in a single operation.
18. A method, comprising:
a step for forming a conductive structure;
a step for forming a diffusion-barrier lining around the conductive structure after forming the conductive structure; and
a step for forming an insulative structure around the conductive structure after forming the diffusion-barrier lining.
19. The method of claim 18, wherein the conductive structure is formed on a surface of a semiconductor substrate by electroplating a conductive material on a patterned photo-resist layer forming contact holes to the substrate.
20. The method of claim 19, further including a step of forming a seed layer on the patterned photo-resist layer prior to electroplating.
21. The method of claim 20, further including electroplating for a time period sufficient for a thickness of the conductive material to substantially equal a thickness of the photo-resist layer.
22. The method of claim 18, further including forming the conductive structure by one of sputtering and evaporation of a conductive material on a patterned photo-resist layer forming contact holes to the substrate, and chemical mechanical polishing of the conductive material to result in the top surface of the conductive material being substantially level with a top surface of the photo-resist layer.
23. The method of claim 21, further including removal of the patterned photo-resist layer to result in an air bridge conductor arrangement.
24. The method of claim 23, further including removing the patterned photo-resist by a plasma oxygen operation.
25. The method of claim 18, wherein forming the diffusion barrier layer includes forming a layer of tungsten silicide in contact with a majority of the top, side and bottom surfaces of the conductive structure.
26. The method of claim 25, wherein the diffusion barrier layer includes forming a graded composition of tungsten silicon nitride with the nitrogen composition varying from substantially zero at an interface of the diffusion barrier with the conductive material.
27. The method of claim 26, wherein the diffusion barrier is formed by introducing tungsten hexafluoride and hydrogen gas into a processing chamber at a selected temperature and pressure, introducing silane gas into the processing chamber after the tungsten hexafluoride gas has substantially filled the processing chamber, and terminating the flow of silane before terminating the flow of the tungsten hexafluoride.
28. The method of claim 18, wherein the conductive material is selected from at least one of gold, silver, copper, titanium, tungsten, alloys thereof, silicides thereof, nitrides thereof, and combinations thereof.
29. The method of claim 19, wherein forming an insulative structure around the conductive structure after forming the diffusion-barrier lining includes providing a liquid dielectric material and thermally treating the dielectric material to form a solid dielectric substantially surrounding all portions of the conductive structure not in direct contact with the substrate.
30. The method of claim 18, further including at least a second conductive structure disposed upon the first conductive structure forming a two layer air bridge arrangement, and the diffusion-barrier lining formed around all the conductive structures, substantially covering all exposed portions.
31. A method of making an integrated circuit, comprising:
a step for forming a first mask layer in an integrated circuit assembly having a first plurality of openings;
a step for forming a second mask layer having a second plurality of openings;
a step for forming a first conductive material layer having a thickness of from 20 to 30 nanometers in the first and second plurality of openings;
a step for forming a second conductive material layer having a thickness of from 300 to 600 nanometers upon the first conductive material and extending upward to a top surface of the second mask layer;
a step for forming a third mask layer having a third plurality of openings;
a step for forming a fourth mask layer with a fourth plurality of opening;
a step for forming a third conductive material having a thickness of from 20 to 30 nanometers in the third and fourth plurality of openings and contacting the second conductive material;
a step for forming a fourth conductive material having a thickness of from 300 to 600 upon the third conductive material and extending upward to a top surface of the fourth mask layer;
a step for removing substantially all of the mask layers; and
a step for forming a diffusion barrier layer on substantially all portions of the conductive materials not directly in contact with one of the integrated circuit and portions of other ones of the conductive materials.
32. The method of claim 31, further including forming at least some of the first plurality of openings to portions of the integrated circuit.
33. The method of claim 31, wherein removing substantially all of the mask layers is performed in a single operation including at least one of plasma ashing, plasma etching, solvent striping, chemical dissolution and thermal decomposition.
34. The method of claim 31, wherein the removing operation creates a void between a majority of all surfaces of the conductive materials, and the void is substantially filled with at least one of an aerogel, silicon dioxide, xerogel, polyimide, siloxanes and silicon oxynitrides.
35. The method of claim 31, further including forming an adhesion promoter layer prior to forming the second conductive material.
36. The method of claim 35, wherein the adhesion promoter layer includes titanium nitride.
37. The method of claim 31, wherein the forming of at least one of the conductive material layers includes at least one of sputter deposition, ionized magnetron sputtering, DC magnetron sputtering, evaporation deposition, chemical vapor deposition, electroplating, electroless plating and chemical-mechanical polishing, and wherein at least one conductive material is selected from at least one of gold, silver, copper, titanium, tungsten, alloys thereof, silicides thereof, nitrides thereof, and combinations thereof.
38. A method of making an integrated circuit, comprising:
a step for forming a first wiring level in an integrated circuit assembly;
a step for forming a second wiring level in the integrated circuit assembly; and
a step for forming a diffusion barrier layer around at least a portion of the first and second wiring levels in a single barrier formation procedure.
39. The method of claim 38, further including forming the first and second wiring levels as air bridges having substantially all the top, bottom, and side surfaces of the wiring exposed to a gas.
40. The method of claim 38, further including forming the diffusion barrier layer on substantially all the top, bottom, and side surfaces of the wiring.
41. The method of claim 38, wherein the first and second wiring layers are formed by embedding a conductive material in holes and trenches formed in a patterned photo-resist layer.
42. The method of claim 41, further comprising forming the first and second wiring layers by sputtering the conductive material, and planarizing the conductive material by chemical mechanical polishing to a level approximately equal to a top surface of the patterned photo-resist layer.
43. The method of claim 38, wherein the first and second wiring layers are formed by electroplating a conductive material in holes and trenches formed in a patterned photo-resist layer.
44. The method of claim 43, further comprising terminating the electroplating operation when a thickness of the conductive material is approximately equal to a thickness of the patterned photo-resist layer.
45. The method of claim 44, further comprising removing the patterned photo-resist layers in a single operation.
46. The method of claim 45, wherein further, after removing the patterned photo-resist layers, forming the diffusion barrier surrounding substantially the entirety of a top, a bottom and a side portion of the first and second wiring levels in a single operation.
47. The method of claim 46, wherein further, a void formed by the removing of the patterned photo-resist layers is substantially filled with at least one of an aerogel, silicon dioxide, xerogel, polyimide, siloxanes and silicon oxynitrides.
Description
RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No. 09/484,303, filed Jan. 18, 2000, which is incorporated herein be reference.

TECHNICAL FIELD

The present invention concerns methods of semiconductor device or integrated circuit manufacturing, particularly methods of forming interconnects from copper and other metals.

BACKGROUND OF THE INVENTION

Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon substrate, known as a wafer. The components are then wired, or interconnected, together with aluminum wires to define a specific electric circuit, such as a computer memory. The aluminum wires are typically about one micron thick, or about 100 times thinner than a human hair.

To form the aluminum wires, fabricators sometimes use a dual-damascene metallization technique, which takes its name from the ancient Damascan metalworking art of inlaying metal in grooves or channels to form ornamental patterns. The dual-damascene technique entails covering the components on a wafer with an insulative layer of silicon dioxide, etching small holes in the insulative layer to expose portions of the components underneath, and subsequently etching shallow trenches from hole to hole to define a wiring pattern.

Etching the trenches and holes entails forming a mask, using photolithographic techniques, on the insulative layer. The masks, which typically consists of a material called photoresist, shields some portions of the insulative layer from the etchant and allows the etchant to dissolve away other portions. After etching, fabricators remove the mask to expose the patterned insulative layer. They then blanket the entire insulative layer with a thin sheet of aluminum and polish off the excess, leaving behind aluminum vias, or contact plugs, in the holes and thin aluminum wires in the trenches.

The complexity of some integrated circuits demand several interconnected levels of wiring. Some circuits, such as microprocessors, have five or six interconnected levels, with each level formed by repeating the basic dual-damascene produce. For example, to form a second wiring level, fabricators apply a new insulative layer over the first wiring layer, form another mask on the new layer, etch holes and trenches into the new layer, remove the mask, blanket the new layer with aluminum, before finally polishing off the excess to complete it.

In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. Fabrication of copper-wired integrated circuits sometimes follows an extension of the dual-damascene method which includes an additional step of lining the holes and trenches of an insulative layer with a copper-diffusion barrier before blanketing the layer with copper and polishing off the excess. (The diffusion barrier is generally necessary because copper atoms readily diffuse through common insulators, such as silicon dioxide, resulting in unreliable or inoperative integrated circuits.) Typically, the copper-diffusion barrier is more than 30 nanometers thick and consists of tantalum, tantalum nitride, tantalum-silicon-nitride, titanium nitride, or tungsten nitride. Filling the barrier-lined holes and trenches with copper generally entails depositing a thin copper seed layer on the copper-diffusion barrier, electroplating copper on the seed layer, and then polishing off the excess.

The present inventors identified at least two problems with using the extended dual-damascene technique for making the copper wiring. The first is that typical copper-diffusion barriers add appreciable resistance to the copper wiring, and thus negate some promised performance advantages. And, the second is that the number of separate procedures or steps necessary to make the copper wiring using the extended technique makes fabrication both costly and time consuming.

Accordingly, there is a need for better ways of making copper wiring for integrated circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an exemplary integrated-circuit assembly 100, including two transistors 214 a and 214 b and a mask layer 216 with via holes 216 a and 216 b, and a trench 216 c;

FIG. 2 is a cross-sectional view of the FIG. 1 assembly after formation of conductive structure 218 within holes 216 a and 216 b and trench 216 c;

FIG. 3 is a cross-sectional view of the FIG. 2 integrated-circuit assembly after formation of a mask layer 220 on conductive structure 218;

FIG. 4 is a cross-sectional view of the FIG. 3 assembly after formation of a conductive structure 222 on mask layer 220;

FIG. 5 is a cross-sectional view of the FIG. 4 assembly after removal of mask layers 116 and 220 to define space 224;

FIG. 6 is a cross-sectional view of the FIG. 5 assembly after forming a diffusion-barrier 226 on conductive structures 218 and 222;

FIG. 7 is a cross-sectional view of the FIG. 6 assembly after filling space 224 with one or more insulative materials to form a two-level insulative structure 228;

FIG. 7A is a cross-sectional taken along line 7A-7A of FIG. 7;

FIG. 8 is a block diagram of an exemplary integrated memory circuit which incorporates the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following detailed description, which references and incorporates FIGS. 1-8, describes and illustrates specific embodiments of the invention. These embodiments, offered not to limit but only to exemplify and teach the concepts of the invention, are shown and described in sufficient detail to enable those skilled in the art to implement or practice the invention. Thus, where appropriate to avoid obscuring the invention, the description may omit certain information known to those of skill in the art.

FIGS. 1-7 show a number of cross-sectional views of a partial integrated-circuits assembly 100, which taken collectively and sequentially, illustrate a unique exemplary method of making integrated circuits, and more particularly making integrated-circuit wiring in accord with teachings of the present invention. The method, as shown in FIG. 1, begins with a known integrated-circuit assembly or structure 100, which can exist within any integrated circuit, a dynamic-random-access memory, for example. Assembly 100 includes a substrate 212. The term “substrate,” as used herein, encompasses a semiconductor wafer as well as structures having one or more insulative, conductive, or semiconductive layers and materials. Thus, for example, the term embraces silicon-on-insulator, silicon-on-sapphire, and other advanced structures.

Substrate 212 supports a number of integrated elements 214, for example transistors 214 a and 214 b. Transistors 214 a and 214 b are covered by a mask layer 216, which, for example, comprises photoresist. In the exemplary embodiment, the transistors are metal-oxide-semiconductor field-effect transistors (MOSFETs); however, in other embodiments, the transistors are other types of field-effect transistors or bipolar junction transistors, or mixed transistor types. Still other embodiments use other types of integrated devices.

Layer 216 includes two exemplary via holes 216 a and 216 b positioned over respective contact regions (not shown) of transistors 214 a and 214 b and a trench 216 c connecting the via holes. The exemplary embodiment forms layer 216 from photoresist, through use of spincoating, lithography, and photoresist remover. Some embodiments use plasma ashing to pattern the photoresist. Also, in the exemplary embodiment, via holes 216 a and 216 b are cylindrical with diameters of about 1000 nanometers and depths of about 500 nanometers. Trench 216 c is less than 0.50 microns wide and at least one micron deep. The invention, however, is not limited to any particular mask material, formation technique, geometry, or dimensions.

FIG. 2 shows that the exemplary method next forms a conductive structure 218 on mask 216, with one or more portions of the conductive structure contacting one or more exposed portions of the transistors. In the exemplary embodiment, this entails depositing a 20-30-nanometer-thick copper-, silver-, or gold-based seed layer (not shown separately) using a chemical-vapor-deposition, ionized-magnetron sputtering technique, or DC magnetron self-sputtering technique, and then electroplating additional copper-, silver-, or gold-based material on the seed layer to a total thickness of, for example, 0.5 microns. (As used herein, a copper-, silver-, or gold-based material includes at least 25 weight-percent of the base material.) An exemplary chemical-vapor-deposition technique follows a procedure such as that described in Y. Senzaki, “Chemical Vapor Deposition of Copper Using a New Liquid Precursor with Improved Thermal Stability,” MRS Conference Proceedings of Advanced Metallization and Interconnect Systems for ULSI Applications in 1997, ULSI XIII, P. 451-455, 1998, which is incorporated herein by reference. This procedure yields copper films at a typical deposition rate of 150-170 nanometers per minute at wafer temperatures of 195-225 C. The resistance of these films is in the range of 2.0 micro-ohm-centimeter after annealing at 400 C. for five minutes.

Exemplary ionized sputtering technique and d-c magnetron sputtering techniques follow procedures similar to those outlined in S. M. Rossnagel et al., Metal Ion Deposition from Ionized Magnetron Sputtering Discharge,” J. Vac. Sci. Technology B, 12(1), p. 449-453, 1994. And Z. J. Radzimski et al, “Directional Copper Deposition using D-C Magnetron Self-sputtering,” J. Vac. Sci Technology B 16(3), p. 1102-1106, 1998. Exemplary conditions for the ionized-magnetron sputtering operation are: target power range of 10-30 kilowatts for a 200-300 millimeter diameter wafer (or integrated-circuit assembly), RF coil power at 3-5 kilowatts, negative DC bias of 100-200 volts, sputtering argon gas pressurized at 1-35 millitorrs. Ionized-magnetron sputtering, which provides greater acceleration of the metal deposition material than conventional sputtering, forces the sputtered material to more closely conform to the interior profiles of holes and trenches of the targeted surface.

Notably, the exemplary embodiment omits formation of an adhesion layer to promote adhesion of copper (or other materials) to the mask layer. Some embodiments use a 20-50 nanometer-thick layer of titanium nitride (TiN) over the transistor contacts as an adhesion layer and a diffusion barrier. However, other embodiments provide an adhesion layer of titanium nitride. After depositing the conductive material, the exemplary method removes excess material, for example, using a chemical-mechanical planarization or polishing procedure.

Next, as FIG. 3 shows, the exemplary method forms a mask layer 220 over conductive structure 218. Mask layer 220 includes an opening (via) 220 a which exposes a portion of conductive structure 218 and a trench 220 b which intersects opening 220 a. Exemplary formation of conductive structure follows a procedure similar to that used to form mask layer 216 and occurs with at least a portion of mask layer 216 still in place.

FIG. 4 shows that the exemplary method next forms a conductive structure 222 on mask 216, with portions of structure 222 contacting exposed portions of conductive structure 218. In the exemplary embodiment, this entails depositing a 20-30-nanometer-thick copper-, silver-, or gold-based seed layer and electroplating additional copper-, silver-, or gold-based material to an exemplary thickness of 0.5 microns. Excess material is then removed using a chemical-mechanical planarization or polishing procedure. Subsequently, one or more higher-level conductive structures can be formed similarly. FIG. 5 shows that after forming conductive structure 222, the method removes at least a portion of mask structures 216 and 220, defining one or more spaces or voids 224 around conductive structures 218 and 222. Without the surrounding masks, conductive structures 218 and 222 appears as a two-level airbridge. The exemplary embodiment removes substantially all of the mask structures by ashing them in an oxygen plasma.

After removal of the mask structures, the exemplary method forms a diffusion barrier 226 on at least portions of conductive structures 218 and 222. In the exemplary embodiment, this entails growing or depositing a two-to-six nanometer-thick layer of WSiN over substantially all of conductive structures 218 and 222. Exemplary formation of this layer of WSiN occurs within a hybrid reaction chamber such as that described in co-filed and co-assigned patent application entitled Methods and Apparatus for Making Copper Wiring in Integrated Circuits. This application, attorney docket 303.618US1 (99-0469), is incorporated herein by reference.

More particularly, exemplary formation of diffusion barrier 226 entails forming a graded composition of tungsten silicide (WSix), with x varying from 2.0 to 2.5. This entails heating the assembly to a temperature of 360 C. and introducing hydrogen, tungsten hexafluoride, and silane gases into a process chamber enclosing the assembly. The exemplary embodiment introduces the hydrogen and tungsten hexaflouride gases about one-to-three seconds before introducing the silane gas and stops introducing the silane gas about one-to-three seconds before stopping introduction of the hydrogen and tungsten hexaflouride. Exemplary flow rates for the silane and tungsten hexaflouride gases are respectively 1000 sccm and 14 sccm. These flow rates result in a composition of WSi2.3, with a growth rate of approximately 50 nanometers per minute.

To complete the diffusion barrier, the exemplary method nitrides the graded composition of WSix, forming WSixNy. The exemplary nitridation follows an electron-cyclotron-resonance (ECR) plasma nitridation procedure. One version of this procedure is described in A. Hirata et al., WSiN Diffusion Barrier Formed by ECR Plasma Nitridation for Copper Damascene Interconnection, Extended Abstracts of 1998 International Conference on Solid State Devices and Materials, p. 260-261, which is incorporated herein by reference. This entails introducing nitrogen gas and argon gas into the chamber, with the argon gas exciting a plasma. In the exemplary embodiment, the WSixNy is not a compound-forming barrier, but a stuffed barrier, which prevents diffusion by stuffing nitrogen atoms into diffusion paths, such as interstitial sites, within the tungsten silicide. Other embodiments uses diffusion barriers having different compositions and thicknesses, and some entirely omit a diffusion barrier.

FIG. 7 shows that after completion of diffusion barrier 226, the exemplary method fills at least a portion of the remainder of space 224 (denoted 224′ in FIG. 6) with one or more insulative materials to form a two-level insulative structure 228. The exemplary embodiment fills substantially all of space 224, which was previously occupied by mask structures 216 and 220, with a single dielectric material using a single procedure. More particularly, the exemplary embodiment vapor deposits a silicon oxide, such as SiO2, or low-k (that is, low-dielectric-constant) materials, such as xerogels or aerogels. Various methods, such as physical-vapor deposition, chemical-vapor deposition, spin-coating, sol-gel procedures, and so forth can be used to apply these dielectrics.

FIG. 8 shows one example of the unlimited number of applications for one or more embodiments of the present invention: a generic integrated memory circuit 600. Circuit 600, which operates according to well-known and understood principles, is generally coupled to a processor (not shown) to form a computer system. More precisely, circuit 600 includes a memory array 642 which comprises a number of memory cells 643 a-643 d, a column address decoder 644, and a row address decoder 645, bit lines 646, word lines 647, and voltage-sense-amplifier circuit 648 coupled to bit lines 646.

In the exemplary embodiment, each of the memory cells, the address decoders, and the amplifier circuit includes one or more copper-, silver, or gold-based conductors according to the present invention. Other embodiments, use conductors of other materials, made in accord with one or more methods of the present invention. In addition, connections between the address decoders, the memory array, the amplifier circuit are implemented using similar interconnects.

CONCLUSION

In furtherance of the art, the inventors have one or more exemplary methods for making integrated-circuit wiring from materials, such as copper-, silver-, and gold-based metals, some of which allow fabrication of wiring with fewer steps and lower electrical resistance than some conventional methods. One exemplary method initially forms a first mask and a first metal structure on the first mask and then forms a second mask and a second metal structure on the second mask, with the first mask and first metal structure still in place. Continuing, this exemplary method removes both masks in a single removal procedure, forms a diffusion barrier to both metal structures in a single formation procedure, and fills insulative material in and around both metal structures in a single fill procedure. Applying one or more procedures across multiple wiring levels, as in this embodiment, ultimately precludes the necessity of applying these procedures separately to each wiring level and thus promises to simplify fabrication.

The embodiments described above are intended only to illustrate and teach one or more ways of practicing or implementing the present invention, not to restrict its breadth or scope. The actual scope of the invention, which embraces all ways of practicing or implementing the invention, is defined only by the following claims and their equivalents.

Classifications
U.S. Classification438/622, 257/E21.589, 257/E21.162, 257/E23.141
International ClassificationH01L21/4763, H01L21/768, H01L21/285
Cooperative ClassificationH01L21/76856, H01L21/76885, H01L21/76852, H01L21/28512
European ClassificationH01L21/768C3D2B, H01L21/285B4, H01L21/768C6, H01L21/768C3C2