Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20070163920 A1
Publication typeApplication
Application numberUS 11/648,693
Publication dateJul 19, 2007
Filing dateJan 3, 2007
Priority dateJan 5, 2006
Also published asCN1997269A
Publication number11648693, 648693, US 2007/0163920 A1, US 2007/163920 A1, US 20070163920 A1, US 20070163920A1, US 2007163920 A1, US 2007163920A1, US-A1-20070163920, US-A1-2007163920, US2007/0163920A1, US2007/163920A1, US20070163920 A1, US20070163920A1, US2007163920 A1, US2007163920A1
InventorsMasaharu Sasaki
Original AssigneeYamaha Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Housing for electronic components
US 20070163920 A1
Abstract
A housing is formed in such a way that a plurality of chip trays each holding a plurality of semiconductor chips are stored in a storage tray, wherein the chip tray is formed by vertically connecting an upper unit and a lower unit, both of which have the same structure. The semiconductor chips are held between the upper unit and the lower unit of the chip tray, thus preventing two-dimensional movement thereof. When a plurality of housings each having the aforementioned structure are vertically combined together, a plurality of semiconductor chips can be further held between the upper unit of one housing and the lower unit of another housing. This makes it possible to simultaneously transport numerous semiconductor chips, whereby the semiconductor chips are each encapsulated in a surface mount chip package.
Images(10)
Previous page
Next page
Claims(10)
1. A housing comprising:
at least one chip tray for holding a plurality of semiconductor chips; and
a storage tray for storing the at least one chip tray,
wherein the chip tray is formed by vertically connecting an upper unit and a lower unit, between which the plurality of semiconductor chips are held.
2. A housing according to claim 1, wherein the chip tray is shaped in an appropriate size, which is completely held inside of the storage tray within its thickness.
3. A housing according to claim 1, wherein the storage tray has a plurality of engagement portions, which realize engagement with the chip tray and which maintain a vertically connected state of the upper unit and the lower unit.
4. A housing according to claim 1, wherein both of the upper unit and the lower unit have a same structure, so that the lower unit is covered with the upper unit.
5. A housing according to claim 1, wherein when being vertically combined with another housing, a plurality of semiconductor chips are further held between the upper unit thereof and the lower unit of the other housing.
6. A housing according to claim 1, wherein the plurality of semiconductor chips are each encapsulated in a surface mount chip package.
7. A housing according to claim 2, wherein the storage tray has a plurality of engagement portions, which realize engagement with the chip tray and which maintain a vertically connected state of the upper unit and the lower unit.
8. A housing according to claim 2, wherein both of the upper unit and the lower unit have a same structure, so that the lower unit is covered with the upper unit.
9. A housing according to claim 2, wherein when being vertically combined with another housing, a plurality of semiconductor chips are further held between the upper unit thereof and the lower unit of the other housing.
10. A housing according to claim 2, wherein the plurality of semiconductor chips are each encapsulated in a surface mount chip package.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to housings for holding electronic components such as semiconductor chips therein.

This application claims priority on Japanese Patent Application No. 2006-771, the content of which is incorporated herein by reference.

2. Description of the Related Art

Conventionally, various types of housings have been used to hold and transport electronic components such as semiconductor chips. A typical example of the conventionally-known housing is designed to include a plurality of chip trays, each of which holds a plurality of semiconductor chips, and a storage tray, which is larger than the chip tray in size and thickness so as to store the semiconductor chips. The storage tray has a plurality of pockets whose upper ends are opened and which store the chip trays. A plurality of projections are formed on the upper surface of the chip tray so as to define a plurality of areas, on which a plurality of semiconductor chips are held in such a way that they are tightly held and surrounded by the projections and are prevented from being moved in two-dimensional directions. The chip trays each holding plural semiconductor chips are stored in the pockets of the storage tray; then, the storage tray is transported. This makes it possible to simultaneously transport the plural chip trays.

In the above, semiconductor chips are each simply mounted on the upper surface of the chip tray. If the housing rattles during transportation, semiconductor chips may be dislodged in position so as to cause positional deviations or inclinations thereof. This causes an undesirable storage condition for semiconductor chips.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a housing that can hold semiconductor chips in a stable manner by preventing unexpected movement of semiconductor chips during transportation.

A housing of the present invention includes at least one chip tray for holding a plurality of semiconductor chips, and a storage tray for storing the chip tray, wherein the chip tray is formed by vertically connecting an upper unit and a lower unit, between which the semiconductor chips are held. The chip tray is shaped in an appropriate size and is completely held inside of the storage tray within its thickness. In addition, the storage tray has a plurality of engagement portions, which realize engagement with the chip tray and which maintain the vertically connected state of the upper unit and the lower unit. Both of the upper unit and the lower unit have the same structure, so that the lower unit can be covered with the upper unit.

In the above, when the housing is vertically combined with another housing, a plurality of semiconductor chips are further held between the upper unit of the housing and the lower unit of the other housing. Incidentally, the semiconductor chips are each encapsulated in a surface mount package.

As described above, the present invention allows plural chip trays stored in the storage tray to be simultaneously transported, wherein a plurality of semiconductor chips are held between the upper unit and the lower unit of the chip tray. This prevents the semiconductor chips from being dislodged in position during transportation; hence, even when the housing rattles during transportation, it is possible to prevent positional shifts of the semiconductor chips, thus maintaining a stable storage condition for the semiconductor chips.

Since the chip tray is shaped in an appropriate size, which can be completely stored inside of the storage tray within its thickness, it is possible to prevent the total thickness of the housing from being increased when the chip trays are stored in the storage tray; that is, it is possible to realize a compact size with respect to the housing. In particular, when a plurality of housings are vertically combined together, it is possible to reduce the total space required for transportation of the housings.

Due to the provision of the engagement portions having elasticity, it is possible to detachably attach the chip tray to the storage tray. This prevents the chip tray from being unexpectedly separated from the storage tray; and this also maintains the vertically connected state between the upper unit and the lower unit. That is, it is possible to stabilize the stored condition of the semiconductor chips by means of the chip tray and the storage tray.

Since both of the upper unit and the lower unit have the same structure, it is possible to utilize a common design with respect to constituent parts thereof. This reduces the number of different parts required for the upper and lower units.

When a plurality of housings each having the aforementioned structure are vertically combined together, a plurality of semiconductor chips can be further held between the upper unit of one housing and the lower unit of another housing. This increases the total number of semiconductor chips subjected to simultaneous transportation. Incidentally, the semiconductor chips are each encapsulated in a surface mount chip package, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, aspects, and embodiments of the present invention will be described in more detail with reference to the following drawings, in which:

FIG. 1 is a plan view showing a housing including chip trays and a storage tray in accordance with a preferred embodiment of the present invention;

FIG. 2 is a front view of the housing;

FIG. 3 is an enlarged view showing essential parts of the chip tray;

FIG. 4A is an enlarged perspective view showing an upper unit of the chip tray;

FIG. 4B is an enlarged perspective view showing a lower unit of the chip tray;

FIG. 4C is an enlarged perspective view showing the storage tray;

FIG. 5 is a bottom view showing the backside of the upper unit;

FIG. 6 is a cross-sectional view taken along line A-A in FIG. 3, which shows that the upper unit and the lower unit are vertically connected together so as to form the chip tray;

FIG. 7A is a cross-sectional view taken along line A-A in FIG. 3, which shows the upper unit;

FIG. 7B is a cross-sectional view taken along line A-A in FIG. 3, which shows the lower unit;

FIG. 7C is a cross-sectional view taken along line A-A in FIG. 3, which shows the storage tray;

FIG. 8 is a plan view showing the storage tray, which does not hold the chip trays shown in FIG. 1;

FIG. 9A is a cross-sectional view taken along line B-B in FIG. 3, which shows the upper unit;

FIG. 9B is a cross-sectional view taken along line B-B in FIG. 3, which shows the lower unit;

FIG. 9C is a cross-sectional view taken along line B-B in FIG. 3, which shows the storage tray; and

FIG. 10 is a cross-sectional view showing that two housings each including the chip trays and storage tray are vertically combined together.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will be described in further detail by way of examples with reference to the accompanying drawings.

FIG. 1 is a plan view showing a housing in accordance with a preferred embodiment of the present invention; FIG. 2 is a front view of the housing; FIG. 3 is an enlarged view showing essential parts of the housing shown in FIG. 1; and FIGS. 4A to 4C are enlarged perspective views showing main parts of the housing.

A housing 10 includes a plurality of chip trays 11, each of which holds a plurality of chips C, and a storage tray 12 for holding the chip trays 11. The present embodiment does not specifically define the type of the chip C; however, the drawings show that the chips C are encapsulated in surface mount chip packages such as BGA (ball grid array) packages and CSP (chip scale packaging), wherein each chip C has a two-dimensional square shape in which a plurality of terminals are arranged along one side thereof, for example.

As shown in FIGS. 4A and 4B, the chip tray 11 is formed by an upper unit 14 and a lower unit 15, which can be combined together. Both of the upper unit 14 and the lower unit 15 are formed using the same tray member of the same structure, which allows the chips C to be mounted thereon. For this reason, the following description is given mainly with respect to the upper unit 14, wherein parts identical to those of the upper unit 14 are designated by the same reference numerals; hence, the detailed description thereof will be omitted as necessary.

The upper unit 14 is formed using an integrally molded member composed of a resin. As shown in FIG. 3, FIGS. 4A-4C, FIGS. 5 and 6, and FIGS. 7A-7C, the upper unit 14 includes a main component 17 having a square shape in plan view, a plurality of first projections 18, each of which has a rectangular shape in plan view, which project upwardly from the surface of the main component 17, and which are arranged in a two-dimensional manner with a prescribed spacing therebetween (see FIG. 3), a plurality of second projections 19, each of which has a cross shape in plan view and which project downwardly from the backside of the main component 17 (see FIG. 5), and a plurality of square ribs 20, each of which has a square shape in plan view and which project downwardly from the periphery of the backside of the main component 17.

As shown in FIGS. 7A and 7B, a peripheral area 17A of the main component 17 is lowered by a step portion 17B in comparison with the other area of the main component 17. A plurality of recesses 22 are formed at prescribed positions in both of the right and left sides and in both of the upper and lower sides (see FIGS. 3 and 5). Among four corners of the main component 17, one corner K (i.e., a lower-left corner in FIG. 3) has a tapered shape, which allows an operator or worker to recognize the circumferential direction of the upper unit 14.

The first projections 18 are arranged on the surface of the main component 17 in a two-dimensional manner so as to arrange the chips C with a prescribed spacing therebetween, so that four first projections 18 are positioned along four sides of each chip C. That is, each single chip C is held in a chip keeping area defined by four first projections 18, which are positioned adjacently to each other, thus preventing two-dimensional movement of the chip C.

As shown in FIG. 5, the second projections 19 are arranged on the backside of the main component 17 in a two-dimensional manner with a prescribed spacing therebetween. Specifically, each second projection 19 having a cross shape is positioned on the backside of the chip holding area for holding each chip C on the surface of the main component 17. As shown in FIG. 7A, a height h1 of the second projection 19, which projects downwardly from the backside of the main component 17, is smaller than a height h2 of the first projection 18, which projects upwardly from the surface of the main component 17.

The lower unit 15 is formed similar to the upper unit 14; that is, as shown in FIG. 7B, a plurality of first projections 18 are formed on the surface of the main component 17, and a plurality of second projections 19 are formed on the backside of the main component 17.

When the upper unit 14 and the lower unit 15 are vertically combined together as shown in FIG. 6, the tip ends of the first projections 18 of the lower unit 15 come in contact with the backside of the main component 17 of the upper unit 14; and the tip ends of the second projections 19 of the upper unit 14 come in contact with the surface of the main component 17 of the lower unit 15. This makes it possible to securely hold the chips C by means of the first projections 18 and the second projections 19 between the upper unit 14 and the lower unit 15.

The square ribs 20 project downwardly from the periphery of the backside of the main component 17 in such a way that the inner sides thereof are positioned slightly outwardly of the step portions 17B. That is, when the upper unit 14 and the lower unit 15 are vertically combined together, the square ribs 20 of the upper unit 14 engage with the step portions 17B and the first projections 18, which are positioned adjacent to the step portions 17B. This makes it possible to reliably connect the upper unit 14 and the lower unit 15 together.

No special limitation is imposed on the structure of the storage tray 12; however, the present embodiment is designed such that the storage tray 12 is formed as an integrally molded member composed of an appropriate resin such as ABS resin. As shown in FIG. 8, the storage tray 12 includes a tray 24 having an elongated rectangular shape, an absorption portion formed at the center of the tray 24, eight storages 26 (i.e., four storage spaces formed in the left side, and four storage spaces formed in the right side) for storing the chip trays 11 respectively, and a frame 27 formed in the periphery of the tray 24.

The absorption portion 25 is a planar surface surrounded by a frame-shaped rib 29 defining a square area and is subjected to absorption by means of an absorption grid, which is used for the transportation of the housing 10. The upper ends of the frame-shaped rib 29 are positioned substantially in the same plane as the upper surface of the tray 24, whereby the absorption portion 25 is positioned below and in parallel with the upper surface of the tray 24. In addition, a plurality of grid ribs 30 whose heights are identical to the height of the frame-shaped rib 29 are formed in the surrounding areas of the frame-shaped rib 29.

As shown in FIG. 4C, the storage 26 includes an inlet/outlet recess 32 having a rectangular shape, which is slightly larger than the upper unit 14. This allows the chip tray 11 to be attached to or detached from the storage 26 by way of an opening of the inlet/outlet recess 32. The storage 26 also includes four circumferential walls 33, which extend from the opening to the bottom of the inlet/outlet recess 32 so as to define a rectangular space therebetween, a plurality of flanges 34 forming engagement portions, which project inwardly from the lower ends of the circumferential walls 33, a plurality of lock elements 36 forming engagement portions lying along two circumferential walls 33, which are opposite to each other in the inlet/outlet recess 32 in plan view (see FIG. 3), and a plurality of positioning projections 37, which are positioned along the other two circumferential walls in the inlet/outlet recess 32. Herein, the inside of the flange 34 is opened.

A plurality of cutouts 38 are formed along the other two circumferential walls 33 in connection with the lock elements 36. As shown in FIG. 4C, each of the cutouts 38 is elongated vertically from the upper surface of the tray 24 to the flange 34 and is shaped in an appropriate size embracing the lock element 36 therein.

As shown in FIG. 9C, the lock elements 36 are arranged inside of the cutouts 38. As shown in FIG. 6 and FIG. 7C, the lock elements 36 are each placed in a vertically standing position, wherein small projections 40, which project inwardly into the space of the inlet/outlet recess 32, are formed at the upper ends of the lock elements 36. The small projections 40 are each formed in a semi-circular shape in a cross-section thereof; hence, when the chip tray 11 is stored in the storage 26, the small projections 40 engage with the outer periphery of the main component 17 of the upper unit 14. A plurality of interconnection elements 41 horizontally extend from the lower ends of the lock elements 36 and are interconnected to the interior surfaces of the cutouts 38. Herein, the upper portions of the lock elements 36 can slightly move due to the elastic deformation of the interconnection elements 41 and due to the elastic deformation of the lock elements 36.

Two pairs of positioning projections 37 are positioned along each of the two circumferential walls 33 of the inlet/outlet recess 32. The positioning projections 37 are positioned in such a way that, when the chip tray 11 is stored in the storage 26, the positioning projections 37 are received inside of the recesses 22 of the chip tray 11. Therefore, even when the chip tray 11 is rotated in a circumferential direction by 90 from the prescribed position shown in FIG. 3 and is pushed into the storage 26, the positioning projections 37 interfere with the peripheral areas 17A of the main components 17 of the chip tray 11, thus inhibiting the chip tray 11 from being inserted into the storage 26. That is, the chip tray 11 should be stored in the storage 26 of the storage tray 12 in such a way that the positioning projections 37 do not interfere with the peripheral areas 17A, wherein the chip tray 11 is precisely positioned inside of the storage 26 at the prescribed position (at which the tapered corner K is positioned as shown in FIG. 3) or at another position (at which the chip tray 11 is rotated by 180 in comparison with the illustration of FIG. 3).

As shown in FIG. 6, the depth of the storage 26 is determined in such a way that the chip tray 11 (in which the upper unit 14 and the lower unit 15 are vertically connected together) is completely stored inside of the storage 26 within the thickness of the storage tray 12. In the state shown in FIG. 6, the tip ends of the first projections 18 of the upper unit 14 are positioned substantially in the same plane as the surface of the tray 24, and the tip ends of the square ribs 20 of the lower unit 15 are positioned above the lower portion of the frame 27 and do not extend outwardly from the frame 27.

The frame 27 is elongated downwardly from the periphery of the tray 24, and a step portion 27A whose height is lower than the height of the upper surface of the tray 24 is formed on the upper end of the frame 27. When a plurality of housings 10 are vertically combined together as shown in FIG. 10, the lower end of the frame 27 of the storage tray 12 of one housing 10 is mounted on the step portion 27A of the frame 27 of the storage tray 12 of the other housing 10. As shown in FIG. 2 in view of FIG. 1, a pair of recesses 43 whose openings are directed downwardly are formed on the backside of the frame 27. In addition, a pair of hooks 44 are interconnected to both sides of the frame 27.

In order to store the chips C in the housing 10, each chip C is mounted on the main component 17 of the lower unit 15 in such a way that the four sides thereof are positioned opposite to the corresponding four first projections 18 of the lower unit 15. Next, the upper unit 14 and the lower unit 15 are vertically connected together in such a way that the step portion 17B and the first projections 18 lying along the step portion 17B of the lower unit 15 are engaged with the square ribs 20 of the upper unit 14. Thus, the second projections 19 of the upper unit 14 are precisely positioned just above the chips C stored in the lower unit 15. This prevents the chips C from being dislodged in position; that is, the lower unit 15 is covered with and closed by the upper unit 14. The chip tray 11 (consisting of the upper unit 14 and the lower unit 15 including the chips C) is precisely located in such a way that the positioning projections 37 of the storage 26 of the storage tray 12 are received in the recesses 22 of the upper unit 14 and the lower unit 15; then, the chip tray 11 is pushed into the storage 26. At this time, the peripheral areas 17A of the upper unit 14 and the lower unit 15 slide along the small projections 40 of the lock elements 36 of the storage 26 so that the lock elements 36 are slightly inclined outwardly due to the elasticity thereof. When the lower surface of the peripheral area 17A of the lower unit 15 is mounted on and comes in contact with the flanges 34 of the storage 26, the lock elements 36 are restored at the initial position, so that the small projections 40 of the lock elements 36 are engaged with the upper surface of the peripheral area 17A of the upper unit 14. That is, the chip tray 11 is vertically held by means of the flanges 34 and the small projections 40 of the lock elements 36. This prevents the vertical movement of the chip tray 11. Thus, it is possible to securely store the chip tray 11 in the storage 26 of the storage tray 12 while maintaining the vertically connected state of the upper unit 14 and the lower unit 15.

Similarly, the other chip trays 11 holding the chips C are stored in the other storages 26 of the storage tray 12; thus, it is possible to realize the fully loaded state of the housing 10 as shown in FIG. 1.

Similar to the lower unit 15, a plurality of chips C can be held by means of the upper unit 14. The chips C held in the upper unit 14 are covered with the lower unit 15 when two housings 10 are vertically combined together as shown in FIG. 10. That is, when one housing 10 in which the chips C are held in the upper unit 14 is vertically combined with and covered with the other housing 10, the second projections 19 of the lower unit 15 of the other housing 10 are precisely positioned just above the chips 10 held in the upper unit 14 of one housing 10.

In order to extract the chips 10 from the chip tray 11 held in the storage 26 of the storage tray 12 of the housing 10, an external force is compulsorily applied to the chip tray 11 so as to release the engagement between the chip tray 11 and the lock elements 36, thus extracting the chip tray 11 from the opening of the inlet/outlet recess 32 of the storage 26. Then, the upper unit 14 is separated from the lower unit 15 so as to expose the chips C, which can be thus extracted individually.

As described above, the present embodiment is designed such that the chips C are held between the upper unit 14 and the lower unit 15. This makes it possible to collectively transport a plurality of chip trays 11 held by the storage tray 12, wherein it is possible to prevent the chips C from being unexpectedly shifted in position and from falling off during transportation.

In addition, it is possible to prevent the vertical movement of the chip tray 11 by means of the flanges 34 of the storage 26 and the lock elements 36. The chip tray 11 can be easily reversed and extracted from the storage 26 by reversing the storage tray 12. This makes it possible to speedily perform testing such as electrification inspection with respect to both sides of the chips C.

When a plurality of housings 10 are vertically combined together, the chips C held by the upper unit 14 of one housing 10 are covered with the lower unit 15 of the other housing 10; hence, it is possible to reliably hold the chips C.

The present invention is not necessarily limited by the present embodiment; hence, the present invention can be modified in a variety of ways in terms of the shapes, positions, and directions of the aforementioned components and parts without departing from the scope of the invention defined by the appended claims.

For example, it is possible to increase or decrease the number of storages 26 formed in the storage tray 12 as long as each storage 26 is designed to store at least one chip tray 11. In order to improve visual recognition, it is possible to apply different colors to the chip tray 11 and the storage tray 12. This makes it possible to smoothly attach the chip tray 11 to the storage tray 12 and to smoothly detach the chip tray 11 from the storage tray 12. Of course, it is possible to apply various design changes to the upper unit 14 and the lower unit 15 in accordance with dimensions of the chips C and the number of chips C.

In addition, it is possible to appropriately change the number of lock elements 36 and the positions of the lock elements 36 as long as the vertical movement of the chip trays 11 held in the storage tray 26 can be reliably secured.

The lock elements 36 are not necessarily designed so as to have small projections 40 at the upper ends thereof. That is, the lock elements 36 can be modified in such a way that the small projections 40 are formed at both of the upper ends and lower ends of the lock elements 36. In this modification, the small projections 40 formed at the upper ends and lower ends of the lock elements 36 are engaged with the upper unit 14 and the lower unit 15 respectively. This guarantees a stable storage condition. In addition, even when only the upper unit 14 is held in the storage 26, it is possible to reliably establish the engagement between the upper unit 14 and the small projections 40 of the lock elements 36, thus preventing the vertical movement of the upper unit 14.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7475816 *Aug 12, 2005Jan 13, 2009Rochelo Donald RProtective case for a plurality of different sized memory cards
US8041196 *Dec 23, 2008Oct 18, 2011Shinko Electric Industries Co., Ltd.Heat radiating plate storage tray
US20110094899 *Feb 2, 2009Apr 28, 2011Coventry UniversityContainer for Waste Electrical and Electronic Equipment
US20110259772 *Sep 24, 2009Oct 27, 2011Illinois Tool Works Inc.Devices and method for handling microelectronics assemblies
US20130087186 *Oct 11, 2011Apr 11, 2013Sunlink Corp.Photovoltaic module carrier
Classifications
U.S. Classification206/725
International ClassificationB65D85/00
Cooperative ClassificationH01L21/67333
European ClassificationH01L21/673E
Legal Events
DateCodeEventDescription
Apr 11, 2007ASAssignment
Owner name: YAMAHA CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SASAKI, MASAHARU;REEL/FRAME:019184/0804
Effective date: 20061222