US 20070171753 A1
A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.
40. A method of operating a DRAM device in either a first relatively higher power mode or a second, relatively higher power mode, comprising:
when operating in the first mode, refreshing rows of memory cells in an array one-row-at-a-time at a first rate;
when operating in the second mode, refreshing rows of memory cells in the array multiple rows-at-a-time at a second rate that is slower than the first rate; and
when switching from operation in the first mode to operation in the second mode, transferring data from each row of the array in which data are stored to at least one other row of memory cells.
41. The method of
42. The method of
activating a word line for the row in which data are stored thereby coupling each of the memory cells in the row to one of a pair of respective complimentary digit lines;
sensing the voltage between each of the pairs of complimentary digit lines using a respective sense amplifier that drives the differential voltage between the complimentary digit lines to a predetermined voltage; and
while each of the sense amplifiers is driving the predetermined voltage between the respective pair of complimentary digit lines, activating a respective word line for the at least one other row of memory cells thereby coupling one of the digit lines in each of the pairs of complimentary digit lines to the respective memory cell in the at least one other row of memory cells.
43. The method of
44. The method of
45. The method of
46. The method of
This invention relates to dynamic random access memory devices, and, more particularly, to a method and system for allowing a memory device to be quickly and easily switched into and out of a low power, half density, operating mode.
As the use of electronic devices, such as personal computers, continue to increase, it is becoming ever more important to make such devices portable. The usefulness of portable electronic devices, such as notebook computers, is the limited by the limited length of time batteries are capable of powering the device before needing to be recharged. This problem has been addressed by attempts to increase battery life and attempts to reduce the rate at which such electronic devices consume power.
Various techniques have been used to reduce power consumption in electronic devices, the nature of which often depends upon the type of power consuming electronic circuits that are in the device. For example, electronic devices, such a notebook computers, typically include dynamic random access memory (“DRAM”) devices that consume a substantial amount of power. As the data storage capacity and operating speeds of DRAM devices continues to increase, the power consumed by such devices has continued to increase in a corresponding manner.
A variety of operations are performed in DRAM devices, each of which affects the rate at which the DRAM device consumes power. One operation that tends to consume power at a substantial rate is refresh of memory cells in the DRAM device. As is well-known in the art, DRAM memory cells, each of which essentially consists of a capacitor, must be periodically refreshed to retain data stored in the DRAM device. Refresh is typically performed by essentially reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. This refresh is generally performed on a row-by-row basis at a rate needed to keep charge stored in the memory cells from leaking excessively between refreshes. Since refresh essentially involves reading data bits from and writing data bits to a large number of memory cells refresh tends to be a particularly power-hungry operation. Thus many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
The amount of power consumed by refresh also depends on which of several refresh modes is active. A Self Refresh mode is normally active during periods when data are not being read from or written to the DRAM device. Since portable electronic devices are often inactive for substantial periods of time, the amount of power consumed during Self Refresh can be an important factor in determining how long the electronic device can be used between battery charges.
One technique that has been used to reduce the amount of power consumed by refreshing DRAM memory cells is to vary the refresh rate as a function of temperature. As is well known in the art, the rate at which charge leaks from a DRAM memory cell increases with temperature. The refresh rate must be sufficiently high to ensure that no data is lost at the highest temperature in the specified range of operating temperatures of the DRAM device. Yet, DRAM devices normally operate at a temperature that is substantially lower than their maximum operating temperature. Therefore, DRAM devices are generally refreshed at a rate that is higher than the rate actually needed to prevent data from being lost, and, as a result, unnecessarily consume power. To address this problem, some commercially available DRAM devices allow the user to program a mode register to select a lower maximum operating temperature. The DRAM device then adjusts the refresh rate to correspond to the maximum operating temperature selected by the user.
Although adjusting the refresh rate as a function of temperature does reduce the rate of power consumed by refresh, it nevertheless still allows power to be consumed at a significant rate for several reasons. For example, although the refresh rate may be reduced with reduced maximum operating temperature, the refresh may still result in refreshing a large number of memory cells that are not actually storing data.
Another approach to reducing the rate at which power is consumed by a refresh operation is to refresh less than all of the memory cells in the DRAM device in attempt to refresh only those memory cells needed to store data for a given application. As described in U.S. Pat. No. 5,148,546 to Blodgett, a software program being executed in a computer system containing the DRAM devices is analyzed to determine the data storage requirements for the program. The DRAM device then refreshed only those rows of memory cells that are needed to store data. In another approach, the DRAM device may be operated in a partial array self refresh (“PASR”) mode. In the PASR mode, a mode register is programmed by a user to specify a bank or portion thereof of memory cells that will be used and thus must be refreshed. The remaining memory cells are not used and thus need not be refreshed during at least some refresh modes. Although these techniques for refreshing less than all of the memory cells in a memory device can substantially reduce the rate of power consumption, it can nevertheless require a substantial amount of power to refresh the cells that are to be refreshed.
Still another technique that can be used to reduce the rate of refresh involves operating DRAM devices in a half density mode. A DRAM device that may be operated in a half density mode is described in U.S. Pat. No. 5,781,483 to Shore. In the half density mode, the low order bit of each row address, which normally designates whether the addressed row is even or odd, is ignored, and both the odd row and adjacent even row are addressed for each memory access. In a folded digit line architecture, activating an odd row will couple each memory cell in the row to a respective digit line, and activating an even row will couple each memory cell in the row to a respective complimentary digit line. Thus, for example, writing a “1” to an addressed row and column would result in writing a logic “1” voltage level to the memory cell in the addressed odd row and writing a logic “0” logic level to the memory cell in the addressed even row. Reading from the addressed row and column results in a logic “1” voltage level being applied to the digit line for the addressed column and a logic “0” voltage level being applied to the complimentary digit line for the addressed column. Therefore, in the half density mode, a sense amplifier coupled to the digit line and complimentary digit line for each column receives twice the differential voltage that it normally receives when reading a memory cell at an addressed row and column.
The patent to Shore describes the use of the half density mode for the purpose of allowing the DRAM device to be used despite the presence of defective memory cells. If a memory cell in an addressed row and column is defective, the data bit stored in that memory cell can still be recovered from the other memory cell in the addressed row and column. However, it has been recognized that the half density mode can be used to reduce that rate at which power is consumed during refresh. Although a refresh in the half density mode requires twice as many memory cells to be refreshed for a given amount of stored data, the required refresh rate is less than half the required refresh rate when the DRAM device is operating in the full density mode. The substantially lower refresh rate required in the half density results from the increased differential voltage that is applied to the sense amplifiers in the half density mode, as previously explained. As a result, the memory cells can be allowed to discharge to a greater degree between refreshes without the data bits stored therein being lost. Therefore, storing data in the half density mode can reduce the rate of power consumption during refresh
In conventional DRAM devices, the density mode, i.e., either half or full, is generally determined prior to sale of the device. If the power consumption of the DRAM device is of concern, the half density mode can be selected. Otherwise, the full density mode can be selected. Yet many power management algorithms for electronic devices containing DRAM devices, such as notebook computers, switch to a low power mode when the electronic device is inactive and back to a high power mode when the electronic device is active. It is therefore necessary for electronic devices to be able to frequently switch back and forth between low power and high power modes.
In conventional DRAM devices, it is not possible to switch between a full density mode and a half density mode. This limitation may be due to the difficulty in making this transition. The difficulty of being able to rapidly switch between the full density mode and the half density mode primarily results from two requirements. First is the need to first free-up alternate rows of memory cells into which data from an adjacent row of memory cells can be transferred for half density storage. The second requirement is the need to transfer data from the memory cells in a row storing data to a memory cell in the adjacent row once the adjacent row has been freed up by transferring data to another row. More particularly, if the DRAM device is operating in the full density mode, generally data will be stored in both even rows and odd rows of memory cells. To switch to the half density mode would require that the data stored in the even rows of memory cells, for example, be transferred to empty odd rows of memory cells. It would then be necessary to read the data stored in each odd row, and write the read data to corresponding memory cells in the adjacent even row. Transferring data between memory cells in this manner by conventional read/write operations would require a great deal of time and would therefore preclude quickly switching back and forth between the full density mode and the half density mode. Also, transferring approximately half of the data stored in the DRAM device by conventional read/write operations, which would be necessary to switch from the full density mode to the half density mode, would itself consume a great deal of power. While more efficient row copy schemes have been proposed for test purposes, such as the row copy scheme described in U.S. Pat. No. 5,381,368 to Morgan et al., these row copy schemes are generally suitable only when the same data or a repeating pattern of data are to be written to the entire array of memory cells. Yet switching from the full density mode to the half density mode would require transferring many rows of disparate data bits to respective adjacent rows after freeing up the adjacent rows by transferring the disparate data bits to other rows. It therefore does not seem possible to easily transition between the half density mode and the full density mode.
There is therefore a need for a power-saving technique that would allow switching into and out of a half density, low refresh rate mode without requiring time and power consuming reading and writing of data to a second set of memory cells.
A system and method according to the invention allows a DRAM device to be easily and quickly switched back and forth between a full density mode consuming power at a relatively fast rate and a half density mode consuming power at a relatively slow rate. The row addresses applied to the DRAM device are reordered by remapping the most significant bit of each row address to the least significant bit of the row address during all operating modes. As a result, all of the odd (or even) rows of the DRAM array are populated with data before any of the even (or odd) rows are populated with data. As long as the data stored in the DRAM device uses less than half of the capacity of the DRAM device, data will then be stored only in alternate rows, and the row adjacent each row in which data are stored will be free to store data. When the DRAM device is to be switched from the full density mode to the half density mode, data stored in each row is simply transferred to the adjacent row. Thereafter when operating in the half density mode, the row corresponding to each row address and the adjacent row are accessed at the same time. Although the data stored in each row can be transferred to the adjacent row by a variety of techniques, it is preferably transferred by transferring the data from each row to the adjacent row during the first refresh of the row. More particularly, when a row is first refreshed after the DRAM device has been switched to the half density mode, the sense amplifiers are left active so that the voltage levels corresponding to the data stored in the memory cells being refreshed are maintained on the respective digit line pairs. The adjacent row is then activated thereby transferring the voltage on the digit lines to the memory cells in the adjacent row. Once the data have been transferred to the adjacent rows during refresh at the full density refresh rate, the refresh rate can be significantly reduced during operation in the half density mode.
A memory map 10 for a conventional DRAM device (not shown) is shown in
Data are often written to the rows of memory cells in a DRAM array in numerical order. As a result, data written to the DRAM device first populates the memory cells in row 0, then the memory cells in row 1, then the memory cells in row 2, etc. The presence of valid data in adjacent rows is the primary reason why it would be very time consuming to switch from the full density mode to the half density mode, as previously explained. Since data will generally be stored in row 1, it would not be possible to simply transfer the data from row 0 to row 1. Instead, that data stored in the memory cells in row 1 must first be read from row 1 and then written to unused memory cells in another row. Only then can the data in row 0 be transferred to row 1. As mentioned earlier, transferring a large block of data in this manner is time consuming and requires a relatively large amount of power.
A memory map 20 showing the organization of memory cells in a DRAM device according to one embodiment of the invention is shown in
One technique for organizing a DRAM array as shown by the memory map 20 of
As shown in Table 1, consecutive row addresses are mapped to addresses for consecutive even rows until row address 31, which is mapped to row address 62. At this point, half of the rows have been mapped. Row address 32, the next row address in chronological sequence, is mapped to row 1. Thus, it is not until row 32 has been addressed that data are stored in any odd row. Thereafter, consecutive row addresses are mapped to consecutive odd rows until row 63 is mapped to row address 63.
Organizing the memory as explained with reference to
One embodiment of a DRAM device 40 according to one embodiment of the invention is shown in
Specific memory cells in an active row are selected by a column decoder 66 responsive to either an external column address received through the address bus 56 or internal column addresses received from a column address counter 68. The column address counter 68 is used in a burst mode to sequentially access several columns starting from a column designated by an externally applied column address. Data from memory cells selected by row and column addresses are coupled between the memory array 44 and a data bus 70 by an Input/Output Control circuit 72.
One embodiment of the memory array 44 is shown in greater detail in
In operation in the normal mode, data bits are written to the memory cell capacitors 82, 84, 90, 92 by causing one of the row decoders 50, 52 to actuate one of the word lines 46, 48 and then driving one of the digit lines 80, 86 to either 0 volts or VCC. The voltage on one of the digit lines 80, 86 is thereby transferred to one of the memory cell capacitors 82, 84, 90, 92. Data bits are read from the memory cell capacitors 82, 84, 90, 92 by equilibrating the digit lines 80, 86 to 0.5 VCC, then causing one of the row decoders 50, 52 to actuate one of the word lines 46, 48, and then enabling the sense amplifier 96. The charge of the memory cell capacitor, which is at either 0 volts or VCC (or some voltage between 0 volts and VCC if the memory cell has not been refreshed recently), is then coupled through one of the access transistors 74, 76 to one of the digit lines 80, 86. The capacitor then charges or discharges the digit line 80, 86 below or above 0.5 VCC. The other digit line 80, 86 that is not coupled to a memory cell capacitor will remain at the 0.5 VCC voltage to which it was originally set during equilibration. The sense amplifier 96 responds to the increase or decrease in voltage coupled to one of the digit lines 80, 86 by driving the digit lines 80, 86 to opposite voltages (0 volts and VCC) and outputs a corresponding data bit on the data line 98.
As previously explained, charge can leak from the memory cell capacitors 82, 84, 90, 92 so that the data bits stored therein become unreadable unless they are refreshed at a fairly frequent interval. During refresh, each of the word lines 46, 48 is sequentially activated and the sense amplifier 96 for each column is energized to recharge or discharge the memory cell capacitors 82, 84, 90, 92. Because of the large number of memory cells in a conventional DRAM array 44, refreshing in the memory cells can require substantial current.
In operation in the low power, half density mode, data bits are stored in the memory cell capacitors 82, 84, 90, 92 in the same manner as described for the normal operating mode. However, in order for the DRAM device 40 to be operable in the half density mode, the data stored in the DRAM device 40 must occupy less than half of its capacity. Under the circumstances, data will be stored only in the memory cells coupled to the even-numbered word lines. The data bit stored in each memory cell in each of the even-numbered rows is written to the memory cell in the same column of the adjacent odd-numbered row. Thus, for example, if the memory cell capacitor 82 has been charged to VCC indicative of a binary “1” data bit stored in the memory cell capacitor 82, the memory cell capacitor 92 in the adjacent odd-numbered row will be discharged to 0 volts. Charging the memory cell capacitor 92 to 0 volts is also indicative of a binary “1” data bit stored in the memory cell capacitor 92 since the memory cell capacitor 92 is coupled to the complementary digit line 86. When data are read from the memory array 44, the even-numbered word line 46 a and the odd-numbered word line 48 a are activated at the same time. The charge on the memory cell capacitor 82, which is at VCC, is then coupled through the access transistor 74 a to the digit line 80, and the lack of charge on the memory cell capacitor 92, which is at 0 volts, is then coupled through the access transistors 76 a to the complimentary digit line 86. The differential voltage applied to the sense amplifier 96 will thus be twice the voltage applied to the sense amplifier during a read operation in the normal operating mode. As a result of this increased differential voltage applied to the sense amplifier 96, the charge on the memory cell capacitors 82, 92 can be permitted to change to a greater extent without a loss of data. The time between refreshing the memory cell capacitors 82, 92 can therefore be substantially increased. Alternatively, data could be stored in the full density mode only in the memory cells coupled to the odd-numbered word lines, and, in transitioning to the half density mode, the data could be transferred to the memory cells coupled to the even-numbered memory cells.
Another embodiment of a memory array 44″ is shown in
Returning, now, to
As previously explained, it is necessary to periodically refresh the memory cells in the array 44. The memory cells may be refreshed in the active mode by the command decoder 104 decoding an Auto Refresh command applied to the DRAM device 40. The command decoder 104 then causes the Array Control circuit 112 to generate appropriate control signals to refresh the memory cells in the array 44 one row at a time. The rows are selected for refresh by respective row addresses generated by the Row Address Counter 58 responsive to the AREF control signal generated by the command decoder 104. In subsequent AREF cycles, the Counter 58 is incremented once for each Auto Refresh command to generate respective row addresses for each row of memory cells that causes the row decoders 50, 52 to activate respective word lines.
The memory cells in the array 44 may be refreshed by the command decoder 104 applying the SREF control signal to a Self Refresh Control circuit 116, which, in turn, causes an internal timer to periodically increment the Row Address Counter 58. The Row Address Counter 58 then generates respective row addresses for each row of memory cells. Once the DRAM device 40 is placed in the Self Refresh mode responsive to a decoded SREF signal, the Self Refresh Control circuit 116 will remain in the Self Refresh mode until it is taken out of that mode responsive to an appropriate memory command being applied to the command decoder 104. In the Self Refresh mode, the Self Refresh Control circuit 116 supplies a signal to the Array Control circuit 112 to cause the circuit 112 to generate control signals to activate a row of memory cells corresponding to the row address generated by the Counter 58 and to energize a sense amplifier for each column of memory cells. The Self Refresh mode is thus similar to the Auto Refresh mode except that, in the Self Refresh mode, the command signal to begin each refresh cycle is generated internally by the Self Refresh Control circuit 116 rather than by an external Auto Refresh command. The ability of the DRAM device 40 to remain in the Self Refresh mode without any external input is the primary reason that the Self Refresh mode is typically used when the DRAM device 40 is inactive. When the DRAM device 40 is inactive, many of the circuits in the DRAM device 40 are also often deenergized to reduce the power consumed by the DRAM device 40.
The Self Refresh Control circuit 116 is also coupled to a Row Address Counter 118 that is used in transitioning to the low power, half density mode in accordance with an embodiment of the invention. More specifically, when transitioning to the half density mode, the counter 118 is reset and then increments responsive to each refresh as data from each even-numbered row of memory cells are copied to adjacent odd-numbered row of memory cells. The Row Address Counter 118 thus keeps track of the number of even-numbered rows that have been copied to adjacent odd-numbered rows to determine when the transition to the half density mode is complete. When all of the data stored in the even-numbered rows have been copied to the odd-numbered rows, the Row Address Counter 118 outputs a COPY DONE signal to the Self Refresh Control circuit 116. The manner in which the circuit 116 transitions to the low power, half density mode will now be explained with reference to the flowchart of
A determination is made at 166 as to whether the final row of the memory array 40 has been reached, which, as previously explained, is indicated by the Row Address Counter 118 generating the COPY DONE signal. Initially, of course, the final row will not have been reached so that the Row Address Counter 58 is incremented by two rows at 168. The process then returns and repeats steps 152-162 to copy the data from each even row to the adjacent odd row. Data from an even row is ultimately written to the final odd row of the memory array 44, and a determination is then made at 166 that Y=YMAX responsive to the Row Address Counter 118 applying the COPY DONE signal to the Self Refresh Control circuit 116. The Refresh Control circuit 116 then causes the operation of the DRAM device 40 to exit at 170 to a process that maintains the DRAM device 40 in the low power, half density mode, as shown in
With reference to
Rows N (assumed in the present example to be initially row 0) and N+1 (assumed in the present example to be initially row 1) are then activated at 192 by causing the Array Control circuit 112 to generate an Activate Row signal while the Row Address Counter 58 is outputting the Row address for row N. However, in this mode, the least significant bit of the row address is ignored by the Row Address Counter 58 (
A determination is then made at 200 as to whether the DRAM device 40 is becoming active so that it should no longer operate in the low power, half density mode. If a determination is made at 200 that the DRAM device 40 should transition to the high power, full density mode, the half density procedure will exit at 202. The operation of the DRAM device 40 will than transition to the high power, full density mode as shown in
The principle difference between the transition to the low power, half density mode shown in
With reference to
In contrast to the refresh procedures in the half density mode, in the full density mode, only a single row N is activated at 222. The sense amplifiers are then energized at 226. After the charge on the memory cell capacitor has been restored to its original value, the row N is deactivated at 228, and the sense amplifiers are deenergized at 230. A determination is made at 232 whether the DRAM device 40 has become inactive so that operation should transition to the low power, half density mode. If so, the procedure exits at 236 to the procedure shown in
It will therefore be apparent that the DRAM device 40 can seamlessly transition back to-and-fourth between the high power, full density mode and the low power, half density mode without requiring cumbersome relocation of data in the odd rows.
A computer system 250 using the DRAM device 40 of
Although the present invention has been described with reference to a preferred embodiment, the invention is not limited to this preferred embodiment. For example, instead of storing data in two rows in the low power mode, data can alternatively be stored in 4, 8 or more rows by copying the data that is stored in the full density to mode to 3, 7 or more rows of memory cells, and reordering addresses accordingly. For example, for a quarter density mode, the two most significant row address bits can be reordered to be the two least significant row address bits inside the memory device. Then as the memory is written to sequentially, only every fourth row will be written internally if only one forth of the memory capacity is used. When transitioning to a quarter density mode, the valid row of data can be copied to the next three empty rows by first turning on the valid row, then turning on the empty rows as described previously. Thereafter, all four rows can be simultaneously turned on to enhance the signal applied to the senseamps and therefore improve the refresh characteristics. Conventionally memory cells are grouped into sub arrays of cells where each sub array has associated wordline drivers and senseamps where the row address MSB will select between groups of memory sub arrays. In the preferred embodiment of the present invention, the row address MSB is mapped to the internal row address LSB to allow for a fast row copy operation when transitioning to a low power partial density mode. Alternatively, the row address MSB could be remapped to some other row address within the sub array address space other than the low LSB. Therefore, the invention is limited only by the appended claims, which include within their scope all equivalent devices or methods which operate according to the principles of the invention as described.