US 20070190760 A1
A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.
1. A parallel plate capacitor for use in an integrated circuit comprising a set of capacitor plates disposed on consecutive levels in the back end of an integrated circuit, alternate ones of the capacitor plates overlapping with vertically adjacent capacitor plates and being adapted to connect to electrical sources of opposite polarity, thereby forming a first set of a first polarity and a second set of a second polarity, said capacitor plates being formed simultaneously with other interconnections in the remaining portion of the integrated circuit; whereby said capacitor plates have the same thickness as said other interconnections and are separated vertically by the same amount of interlevel dielectric, in which:
each of said capacitor plates is a solid continuous layer, wherein at least one of said capacitor plates comprises a set of perforations formed within said solid continuous layer.
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9. A method of forming a parallel plate capacitor comprising a set of capacitor plates disposed on consecutive levels in the back end of an integrated circuit, alternate ones of the capacitor plates overlapping with vertically adjacent capacitor plates and being adapted to connect to electrical sources of opposite polarity, thereby forming a first set of plates of a first polarity and a second set of plates of a second polarity, comprising the steps of:
depositing successively a set of capacitor levels of conductive interconnects in the back end of an integrated circuit, each of said capacitor levels including at least one conductive plate having the same thickness as other interconnect members on said capacitor levels and deposited simultaneously with said other interconnections.
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The field of the invention is that of forming a plate capacitor having a set of horizontal conductive plates separated by a dielectric (MIM-CAP).
High performance (high Q-value) metal-insulator-metal capacitor (MIM cap) is one of the essential passive devices in RF/Analog circuitry. In order to achieve high-Q value, low resistance metal plates are typically used. In prior work, the bottom plate of a metal-insulator-metal (MIM) capacitor is typically made of back end of the line (BEOL) aluminum metal wire on the xth level of the back end (zero-cost). An additional photolithography mask is used for MIM cap top plate formation. This additional top plate mask leads to extra wafer processing cost of about $25/wafer. In the advanced CMOS technologies with Cu BEOL, up to three masks are employed to create high-Q MIM capacitors.
In an effort to reduce cost, vertical parallel plate capacitors (VPP) have been recently developed/introduced in the advanced Analog/RF CMOS technologies. VPPs capacitor plates are made of BEOL Mx wire fingers and vias. Due to scaling of BEOL wiring width and spacing, the capacitance density of VPP becomes appreciable for technologies with minimum features smaller than 0.25 um. However, the performance of a VPP capacitor is limited because of the high resistance associated with metal fingers/vias, which is particularly troublesome for high frequency application.
As a result, a high performance MIM capacitor is still desirable & needed for Analog/RF CMOS technologies.
The present invention utilizes BEOL wide Cu planes as MIM capacitor electrodes and the existing inter-level dielectric layers as MIM dielectric films; i.e. the thickness of the capacitor plates and of the dielectric is the same in the capacitor as in the rest of the circuit.
The Mx electrodes are tied together to create a parallel plate capacitor. As a result, the resistance of MIM plates according to the present invention is extremely low, which leads to a high performance MIM capacitor.
The capacitance density for the invented MIM increases as the inter-level dielectric films become thinner for more advanced technologies. Moreover, more BEOL metal wiring levels are employed for advanced technologies, which can lead to higher capacitance density for the present invention because more metal levels can be connected together.
To further enhance capacitance density of this zero-cost high-Q MIM capacitor, Vx vias are added through Mx perforation holes (through-vias). The use of through-vias increases capacitive coupling and reduces/eliminates additional wiring area needed for MIM cap plate connection, which again leads to cap density enhancement.
An Ansoft Q3D simulation indicates that capacitance density improvement of greater than 30% is possible compared with through-via practice.
Fabrication of the invented high-Q MIM is fully compatible with Cu BEOL processing. The plates are deposited in apertures in the interlevel dielectric simultaneously with the other interconnects on that level. The blocks labeled 56 that connect the plates of each polarity are schematic representations. They may be vertical bars of metal, vertically aligned damascene conductors, regular interconnects, or any other structure. Preferably, they are vertically aligned dual damascene structures, so that no additional masks or processing steps are needed. No additional processing steps are added in this invented high-Q MIM. An estimate of the capacitance density for six levels of thin metal wire BEOL in 65 nm technology results in cap density of 0.88 fF/μm2 when no perforation is assumed.
This no perforation assumption is valid for MIMs that require small plates. When MIM plates become large (approximately 20 microns on edge), perforating of copper plates is necessary in order to achieve uniform copper plate thickness. Significant copper plate thinning is expected when large non-perforated Cu plates are used due to the fast Cu polish rate associated with large plates during CMP processing.
However, the capacitance density loss due to perforation is limited. Based on an Ansoft Q3D simulation using design information for a known process using 90 nm ground rules, the loss of capacitance density from perforation is only about ⅓ of the perforation density (for example, the capacitance reduction comparing 38% perforation to no perforation is only 11.5%).
In all cases in Table I, the overlap area of the plates is 25 micron2.
As can be seen in Table I, the perforated but unconnected version of
Similarly, the perforated and unconnected version of
Connecting the vias improves the capacitance ratio substantially, as well as taking up less area after the removal of the vertical connection bars 56.
As can be seen from example 6 from table I, more perforation in copper plates results in lower capacitance. However, the loss in capacitance is much smaller than one skilled in the art would expect. When copper plates are perforated at 38%, the capacitance loss is approximately 11.5%.
The Figures show an even number of plates in the capacitor. Those skilled in the art will understand that an odd number of plates may also be used, so that the top and bottom plates will have the same polarity, e.g. ground.
While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.