US 20070195608 A1
The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide in various combinations to obtain the desired tunneling current values at the operating voltage of the memory device.
1. A method of storing data in a memory device, comprising:
addressing selected ones of a plurality of memory cells with selected ones of a plurality of word lines and a plurality of bit lines;
increasing a voltage applied to a control gate on the selected memory cells, the memory cells each including a substrate, a source region, a drain region and a floating gate disposed beneath the control gate and separated therefrom by an inter-gate insulator layer, the floating gate comprising a conductive film including a mixture of germanium, silicon and carbon;
trapping electrons on the floating gate in response to a positive voltage having at least a first voltage level being applied to the control gate for at least a first time period, changing the memory cell to a first memory state; and
ejecting electrons from the floating gate in response to a negative voltage having at least a second voltage level being applied to the control gate for at least a second time period, changing the memory cell to a second memory state.
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8. A method of storing data in a memory device having a source region and a drain region separated by a channel region in a substrate, a gate insulator adjacent to the channel region, a floating gate on the gate insulator comprising a conductive film including germanium, silicon and carbon, an inter-gate insulator on the floating gate, a control gate on the inter-gate insulator, comprising:
trapping electrons on the floating gate in response to a positive voltage having a first voltage level applied to the control gate for a first time period, changing the memory cell to a first memory state; and
ejecting electrons from the floating gate in response to a negative voltage having a second voltage level applied to the control gate for a second time period, changing the memory cell to a second memory state.
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This application is a divisional of U.S. application Ser. No. 11/063,825 filed Feb. 23, 2005, which is incorporated herein by reference in its entirety.
This application relates generally to semiconductor devices and device fabrication and, more particularly, to transistor gate materials and their properties, and in particular to floating gate devices.
The electronic device industry uses many different types of memory in computers and other electronic systems, such as automobiles and traffic control systems. Different types of memory have different access speeds and different cost per stored bit. For example, items of memory that require rapid recovery may be stored in fast static random access memory (RAM). Information that is likely to be retrieved a very short time after storage may be stored in less expensive dynamic random access memory (DRAM). Large blocks of information may be stored in low cost, but slow access media such as magnetic disk. Each type of memory has benefits and drawbacks, for example DRAMs lose the stored information if the power is shut off. While the magnetic memory can retain the stored information when the power is off (known as non-volatile), the time to retrieve the information is hundreds of times slower than semiconductor memory such as RAM. One type of non-volatile semiconductor memory device is electrically programmable read-only memory (EPROM). There are also electrically-erasable programmable read-only memory (EEPROM) devices. One type of EEPROM is erasable in blocks of memory at one time, and is known as flash memory. Flash memory is non-volatile like magnetic memory, is much faster than magnetic memory like RAM, and is becoming widely used for storing large amounts of data in computers. However, writing information to a conventional flash memory takes a higher write voltage than it does to write information to conventional RAM, and the erase operation in flash requires a relatively long time period.
Conventional EEPROM devices, such as flash memory, may operate by either storing electrons on an electrically isolated transistor gate, known as a floating gate, or not storing electrons on the floating gate. Typically the write (or program) operation and the erase operation are performed by another transistor gate, known as the control gate, which is located above the floating gate. A large positive voltage on the control gate will draw electrons from the substrate through the gate oxide and trap them on the floating gate. The erase operation uses a large negative voltage to drive any stored electrons on the floating gate off of the gate and back into the substrate, thus returning the floating gate to a zero state. This operation may occur through various mechanisms, such as Fowler-Nordheim (FN) tunneling. The rate at which the electrons can be transported through the insulating gate oxide to and from the floating gate is an exponential factor of both the thickness of the insulator and of the electrical height of the insulation barrier between the substrate and the floating gate. Grown gate oxides have great height, and slow tunneling.
Electronic devices have a market driven need to reduce the size and power consumption of the devices, such as by replacing unreliable mechanical memory like magnetic disks, with transistor memory like EEPROM and flash. These increasingly small and reliable memories will likely be used in products such as personal computers (PCs), personal digital assistants (PDAs), mobile telephones, laptop PCs, and even in replacing the slow hard disk drives in full sized computer systems. This is because a solid state device, such as flash memory, is faster, more reliable and has lower power consumption than a complex and delicate mechanical system such as a high speed spinning magnetic disk. What is needed is an improvement in the erase time for EEPROM devices. With improved erase times, the high density of flash memory, and a speed of operation comparable to DRAMs, flash memory might replace both magnetic memory and DRAMs in certain future computer devices and applications.
The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.
The terms wafer and substrate used in the following description include any structure having an exposed surface with which to form an integrated circuit (IC) structure. The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. Both wafer and substrate include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art. The term conductor is understood to generally include n-type and p-type semiconductors and the term insulator or dielectric is defined to include any material that is less electrically conductive than the materials referred to as conductors or as semiconductors.
The term “horizontal” used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.
Field effect transistors (FETs) are used in many different electronic devices, including memory devices. FETs are used both as access transistors and as memory elements. The structure of a typical FET 100 is shown in
The illustrative floating gate transistor 200, as shown in
The reason that changing the material of the substrate or of the floating gate changes the electrical height of the tunneling barrier is best understood by examination of what is known as an energy band diagram, as shown in
Another method of changing the tunneling voltage, and thus equivalently increasing the tunneling current at a particular voltage level, is to change the overall tunneling barrier height by increasing the internal energy level of the conductors on either side of the insulator, rather than by lowering the insulator barrier level. Changing the silicon substrate to some other material may cause numerous practical problems in the fabrication of devices, since so much is known about the use of silicon. Changing the material of the floating gate to a material with what is known as a lower electron affinity, denoted by the lower case Greek letter Chi (χ) results in higher tunneling currents. A lower electron affinity reduces the effective height of the insulator tunneling barrier, which as noted previously has an exponential effect on the amount of tunneling current at a given voltage.
A transistor built on a single crystal silicon substrate has a band gap diagram 300, with a conduction level 302, a valence level 304, and a Fermi level 306, as shown for a lightly doped P type silicon substrate with reference to the vacuum level 308, which represents the amount of energy it would take to remove an electron from the silicon. On the opposite side of a gate oxide 309, heavily doped N type polycrystalline silicon will have a conduction level 310, a Fermi level 312 and a valence level 314. The gate oxide 309 has an energy level value 316, whose difference from the vacuum level 308 represents the electron affinity χ of the gate oxide, typically thermally grown silicon dioxide. For good quality thermally grown silicon dioxide, the value of χ is 0.9 eV. For electrons on the floating gate conduction band 310, the value of electron affinity χ is the difference between 310 and the vacuum level 308, and for doped polysilicon is approximately 4.1 eV. Thus, the barrier that an electron tunneling from the floating gate 212 conduction band 310 to the silicon substrate 202 in the area of the channel 208, must traverse during an erase operation is the height represented by the difference between the top of the gate oxide 316 and the conduction band 310, or 4.1 eV minus 0.9 eV, or about 3.2 eV. As noted previously, the tunneling rate is an exponential factor of the height of the barrier, and the width of the oxide, which is controlled by the process parameter of gate oxide thickness.
The distance between the conduction level 310 and the valence level 314 is known as the band gap, and has a value in silicon of approximately 1.1 eV. Since the value of electron affinity for the gate oxide is not going to change, then the use of a floating gate material that has a larger band gap would result in a lower electron affinity, and thus a reduced tunneling barrier. Changing the electron affinity of the gate material also changes the threshold voltage of the transistor, and may be used in conjunction with channel doping levels and gate insulator thickness and dielectric constant to adjust the threshold voltage level.
Crystalline silicon carbide and silicon germanium carbide can be epitaxially grown on a silicon substrate and may be used in both metal oxide semiconductor field effect transistors (MOSFET) or bipolar transistor devices, with the silicon substrate acting as a seed layer for crystal growth. In an embodiment the silicon carbide, germanium carbide and silicon germanium carbide are microcrystalline or amorphous. Such microcrystalline layers or amorphous layers may be grown on insulator layers such as silicon dioxide gate insulator layers, or other insulator layers, by chemical vapor deposition (CVD), laser assisted CVD, plasma CVD, ultra-high vacuum CVD, or sputtering.
System 600 may include, but is not limited to, information handling devices, telecommunication systems, and computers. Peripheral devices 610 may include displays, additional storage memory, or other control devices that may operate in conjunction with controller 602 and/or memory 606. It will be understood that embodiments are equally applicable to any size and type of memory circuit and are not intended to be limited to a particular type of memory device.
An embodiment has a floating gate transistor with a gate made of a material having a lower tunneling barrier and thus lower erase times. Another embodiment has the floating gate formed of germanium silicon carbide. Another embodiment has the composition of the floating gate determined by a desired tunneling current. Another embodiment includes a transistor with a conventional gate having the composition of the germanium silicon carbide adjusted to optimize the threshold of a metal oxide semiconductor field effect transistor (MOSFET).
An embodiment for a method for forming a floating gate memory device includes forming a floating gate having a lower tunneling barrier by forming the gate of a mixture of germanium, silicon and carbon. Another embodiment includes a method of storing data by setting the voltage of the control gate, drain diffusion and source diffusion to either trap electrons on a floating gate made of germanium, silicon and carbon, or by ejecting trapped electrons from the floating gate by Fowler-Nordheim tunneling.
Applications include structures for transistors, memory devices such as flash, and electronic systems with gates containing a mixture of germanium, silicon and carbon, and methods for forming such structures.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. It is to be understood that the above description is intended to be illustrative, and not restrictive, and that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Combinations of the above embodiments and other embodiments will be apparent to those of skill in the art upon studying the above description. The scope of the embodiments of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.