US20070210812A1 - High-density probe array - Google Patents
High-density probe array Download PDFInfo
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- US20070210812A1 US20070210812A1 US11/464,571 US46457106A US2007210812A1 US 20070210812 A1 US20070210812 A1 US 20070210812A1 US 46457106 A US46457106 A US 46457106A US 2007210812 A1 US2007210812 A1 US 2007210812A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
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- E—FIXED CONSTRUCTIONS
- E21—EARTH DRILLING; MINING
- E21B—EARTH DRILLING, e.g. DEEP DRILLING; OBTAINING OIL, GAS, WATER, SOLUBLE OR MELTABLE MATERIALS OR A SLURRY OF MINERALS FROM WELLS
- E21B19/00—Handling rods, casings, tubes or the like outside the borehole, e.g. in the derrick; Apparatus for feeding the rods or cables
- E21B19/16—Connecting or disconnecting pipe couplings or joints
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- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02D—FOUNDATIONS; EXCAVATIONS; EMBANKMENTS; UNDERGROUND OR UNDERWATER STRUCTURES
- E02D5/00—Bulkheads, piles, or other structural elements specially adapted to foundation engineering
- E02D5/22—Piles
- E02D5/34—Concrete or concrete-like piles cast in position ; Apparatus for making same
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- E—FIXED CONSTRUCTIONS
- E02—HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
- E02D—FOUNDATIONS; EXCAVATIONS; EMBANKMENTS; UNDERGROUND OR UNDERWATER STRUCTURES
- E02D2600/00—Miscellaneous
- E02D2600/20—Miscellaneous comprising details of connection between elements
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49151—Assembling terminal to base by deforming or shaping
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Abstract
A probe array may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.
Description
- This application claims priority from Korean Patent Application 10-2006-0021479, filed on Mar. 7, 2006, which is incorporated by reference.
- Hard disks and optical disks are commonly used as data storage units. However, due to the super-paramagnetic limit of a hard disk or the laser diffraction limit of an optical disk, there is a limit to the amount of data that can be stored with these conventional devices.
- In order to overcome these restrictions, a high-density data storage device using scanning probe microscopy (SPM) technology has been proposed. This data storage device includes a data storage medium, a probe tip for writing data to or reading data from the data storage medium, a probe including a cantilever on which the probe is mounted, a scanner for transferring the data storage medium, a controller for issuing commands to the storage device and controlling the operation of the storage device, and a signal processor. However, even though such a conventional storage device can store a large amount of data, it cannot be easily put to practical use because of the following problems. Since only a limited number of probe tips can be installed on the data storage medium, each probe tip must be transferred over a long distance to access or write data. For example, each probe tip may have to move through intervals of about 100 μm along x- and y-axes of the data storage medium for data to be read or written. Also, the data storage device needs a servomechanism for precisely controlling the position of the probe tip, and a unit capable of moving along a z-axis to prevent wear of the probe tip. As a result, the size of the cantilever increases, the circuit for driving the cantilever becomes more complicated, and power consumption increases. Further, a data storage device using a cantilever cannot randomly access data, and hence the access time increases.
- A conventional storage device is disclosed in U.S. Patent Publication No. 2004/0047275 entitled “Storage Device and Method for Operating a Storage Device” by Cherubini, et al. The storage device described therein can neither effectively store high-density data nor randomly access the data. This is because a heater platform and probe tips are mounted on a cantilever, thus making it difficult to sufficiently increase the number of probe tips and reduce the space occupied by the cantilever.
- Some of the inventive principles of this patent disclosure relate to a probe array that may be fabricated by forming probes arranged on a sacrificial substrate, forming a probe substrate above the probes, and removing the sacrificial substrate. In one embodiment, first probes may be two-dimensionally formed in row and column directions on a sacrificial substrate. Second probes may be formed between the first probes arranged in the row direction such that a distance between the first and second probes is smaller than the resolution limit in a lithography process. A probe substrate may be formed on the sacrificial substrate having the first and second probes, and the sacrificial substrate may be removed.
- In some embodiments, the first probes may be fabricated by forming a mold insulating layer on the sacrificial substrate, patterning the mold insulating layer, thereby forming first holes exposing the sacrificial substrate, forming a first conductive layer on the sacrificial substrate having the first holes, and planarizing the first conductive layer. First hole spacers may be formed to cover sidewalls of the first holes after forming the first holes. The mold insulating layer may include a lower mold insulating layer, a planarization stop layer, and an upper mold insulating layer that are sequentially stacked, the upper mold insulating layer being removed during the planarization of the second conductive layer. A top surface of each of the first and second probes may have an area equal to or greater than a bottom surface thereof. First metal interconnections may be formed to cover the first probes arranged in the column direction, and second metal interconnections may be formed between the first metal interconnections to cover the second probes. Forming the first metal interconnections may include forming an intermetal dielectric layer on the sacrificial substrate having the first and second probes, patterning the intermetal dielectric layer, thereby forming first grooves exposing the first probes arranged in the column direction, forming first groove spacers to cover sidewalls of the first grooves, forming a first metal layer on the sacrificial substrate having the first groove spacers, and planarizing the first metal layer.
- Some inventive principles of this patent disclosure relate to a method of fabricating a storage device by forming a data storage element on a storage substrate, forming probes on a sacrificial substrate, forming a probe substrate over probes, removing the sacrificial substrate, and aligning the probe substrate and the storage substrate such that the data storage element is disposed opposite to the probes.
- Some inventive principles of this patent disclosure relate to a probe array including first probes arranged two-dimensionally in row and column directions, second probes disposed between the first probes arranged in the row direction, a distance between the first and second probes being smaller than the resolution limit in a lithography process, a probe substrate disposed on the first and second probes.
- Some inventive principles of this patent disclosure relate to a storage device having a storage substrate, a data storage element disposed on the storage substrate and having a plurality of data storage regions, a probe substrate over the data storage element; and robes positioned on the data storage element and aligned with the storage substrate.
- Some inventive principles of this patent disclosure relate to a storage device assembly including a data storage element disposed on a storage substrate and having a plurality of data storage regions, a probe substrate on the data storage element, first probes positioned on the data storage element, fixed under the probe substrate, and arranged two-dimensionally in row and column directions, second probes disposed between the first probes under the probe substrate, a distance between the first and second probes being smaller than the resolution limit in a lithography process, and a control unit to move the probe substrate or the storage substrate.
- In some embodiments, the first and second probes correspond to the respective data storage regions, a surface of each of the data storage regions is divided into multiple quadrants, and a central portion of each of the multiple quadrants is a binary digit portion. Each of the data storage regions may be divided into four quadrants. The control unit may move the probe substrate or the storage substrate such that one probe corresponding to one data storage region is positioned on one selected from the multiple quadrants of the data storage region.
- Some inventive principles of this patent disclosure relate to a method of reading/writing data from/to a storage device by two-dimensionally arranging probes in row and column directions on a data storage element having a plurality of data storage regions, wherein the probes correspond to the respective data storage regions, a surface of each of the data storage regions is divided into multiple quadrants, and a central portion of each of the multiple quadrants is a binary digit portion.
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FIG. 1 is a plan view of a storage device according to exemplary embodiments of the present invention. -
FIGS. 2A through 2I are cross-sectional views illustrating a method of fabricating a probe array according to an exemplary embodiment of the present invention. -
FIGS. 3A through 3K are cross-sectional views illustrating a method of fabricating a probe array according to another exemplary embodiment of the present invention. -
FIGS. 4A through 4G are cross-sectional views illustrating a method of fabricating a probe array according to still another exemplary embodiment of the present invention. -
FIG. 5 is a plan view of a storage device according to other exemplary embodiments of the present invention. -
FIGS. 6A through 6F are cross-sectional views of a storage medium according to yet another exemplary embodiment of the present invention. -
FIG. 7 illustrates the layout of a storage device assembly according to exemplary embodiments of the present invention. -
FIG. 8A is an enlarged view of a portion of a storage medium according to exemplary embodiments of the present invention. -
FIG. 8B is an enlarged view of a portion of a probe array according to exemplary embodiments of the present invention. -
FIGS. 9A through 9D are plan views illustrating a method of reading/writing data according to exemplary embodiments of the present invention. - The inventive principles of this patent disclosure are described more fully hereinafter with reference to the accompanying drawings in which exemplary embodiments of the invention are shown. This inventive principles may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the inventive principles to those skilled in the art. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.
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FIG. 1 is a plan view of a storage device according to an exemplary embodiment of the present invention,FIGS. 2A through 2I are cross-sectional views illustrating a method of fabricating a probe array according to an exemplary embodiment of the present invention,FIGS. 3A through 3K are cross-sectional views illustrating a method of fabricating a probe array according to another exemplary embodiment of the present invention, andFIGS. 4A through 4G are cross-sectional views illustrating a method of fabricating a probe array according to yet another exemplary embodiment of the present invention. InFIGS. 2A through 2I , 3A through 3K, and 4A through 4G, reference character “PA” refers to a region taken along line I-I′ ofFIG. 1 , and reference character “PB” refers to a region taken along line II-II′ ofFIG. 1 .FIG. 5 is a plan view of a storage device according to another exemplary embodiment of the present invention, andFIGS. 6A through 6F are cross-sectional views of a storage medium according to another exemplary embodiment of the present invention. InFIGS. 6A through 6F , reference character “SA” refers to a region taken along line III-III′ ofFIG. 5 , and “SB” refers to a region taken along line IV-IV′ ofFIG. 5 . - Referring to
FIG. 1 , the storage device includes first probes and second probes. The first probes are arranged two-dimensionally in rows and columns (i.e., in the X and Y directions). For example, n first probes D11, D21, . . . , Dn1 may be arranged in the X direction, and m first probes D11, D12, . . . , D1 m may be arranged in the Y direction. Thus, n×m first probes D11, D21, . . . , and Dnm may be provided. - The second probes may be disposed between the first probes D11, D21, . . . , Dnm arranged in the X direction. That is, n second probes E11, E21, . . . , En1 may be arranged in the X direction, and m second probes E11, E12, . . . , E1 m may be arranged in the Y direction. Thus, n×m second probes E11, E21, . . . , Enm may be provided.
- In accordance with the inventive principles of this patent disclosure, the first probes D11, D21, . . . , Dmn may be spaced apart from the second probes E11, E21, . . . , Enm by a distance smaller than the resolution limit in a lithography process. Thus, the first probes D11, D21, . . . , ad Dnm and the second probes E11, E21, . . . , Enm may be arranged in a high density pattern.
- The first probes may be covered by first metal interconnections arranged in the Y direction. For example, n first metal interconnections A1, A2, . . . , An may be provided in the Y direction. Second metal interconnections may be disposed between the first metal interconnections in the Y direction. For example, n second metal interconnections B1, B2, . . . , Bn covering the second probes may be provided in the Y direction.
- The first probes D11, D21, . . . , Dnm and second probes E11, E21, . . . , Enm may constitute a high density probe array. A plurality of lower electrodes may be arranged in the X direction across the first metal interconnections A1, A2, . . . , An and the second metal interconnections B1, B2, . . . , Bn. For example, m lower electrodes C1, C2, . . . , Cm may be arranged in the X direction under the first metal interconnections A1, A2, . . . , An and the second metal interconnections B1, B2, . . . , Bn. Although not shown in
FIG. 1 , data storage elements may be provided on the lower electrodes C1, C2, . . . , Cm. - Next, a storage device according to another exemplary embodiment of the present invention will be described with reference to
FIG. 5 . Referring toFIG. 5 , the storage device includes first probes, second probes, third probes, and fourth probes. The first probes are arranged two-dimensionally in X and Y directions. For example, n first probes d11, d21, . . . , dn1 may be arranged in the X direction, and m first probes d11, d12, . . . , d1 m may be arranged in the Y direction. Thus, n×m first probes d11, d21, . . . , dnm may be provided. - The second probes may be arranged in the X direction and disposed between the first probes d11, d21, . . . , dnm. For example, n second probes e11, e21, . . . , en1 may be arranged in the X direction, and m second probes e11, e12, . . . , elm may be arranged in the Y direction. Thus, n×m second probes e11, e21, . . . , enm may be provided.
- The third probes may be arranged in the Y direction and disposed between the first probes d11, d21, . . . , dnm. For example, m third probes f11, f12, . . . , f1 m may be arranged in the Y direction, and n third probes f11, f21, . . . , fn1 may be arranged in the X direction. Thus, n×m third probes f11, f12, . . . , fnm may be provided.
- The fourth probes may be arranged in the Y direction and disposed between the second probes e11, e21, . . . , enm. For example, m fourth probes g11, g12, . . . , g1 m may be arranged in the Y direction, and n fourth probes g11, g21, . . . , gn1 may be arranged in the X direction. Thus, n×m fourth probes g11, g12, . . . , gnm may be provided.
- In some embodiments of the present invention, the first, second, third, and fourth probes may be spaced apart from adjacent probes by a distance smaller than the resolution limit in a lithography process. Accordingly, the first, second, third, and fourth probes may be arranged at a high density pattern.
- First metal interconnections parallel to each other in the Y direction may cover the first probes d11, d21, . . . , dmn and the third probes f11, f12, . . . , fnm. For instance, n first metal interconnections a1, a2, . . . , an may be provided in the Y direction. Additionally, n second metal interconnections b1, b2, . . . , bn may be interposed between the first metal interconnections a1, a2, . . . , an and arranged in the Y direction. The second metal interconnections b1, b2, . . . , bn may cover the second probes e11, e21, . . . , enm and the fourth probes g11, g12, . . . , gnm. The above-described first, second, third, and fourth probes may constitute a probe array. Thus, the probe array may include the first probes d11, d21, . . . , dnm, the second probes e11, e21, . . . , enm, the third probes f11, f12, . . . , fnm, and the fourth probes g11, g12, . . . , gnm that are integrated at a high density level.
- Additionally, a plurality of lower electrodes may be provided across the first metal interconnections a1, a2, . . . , an and the second metal interconnections b1, b2, . . . , bn and arranged in the X direction. For instance, m first lower electrodes Ca1, Ca2, . . . , Cam may be arranged in the X direction and m second lower electrodes Cb1, Cb2, . . . , Cbm may be interposed between the m first lower electrodes Ca1, Ca2, . . . , Cam. The distance between the first lower electrodes Ca1, Ca2, . . . , Cam and the second lower electrodes Cb1, Cb2, . . . , Cbm may be smaller than the resolution limit in a lithography process. The first lower electrodes Ca1, Ca2, . . . , Cam and the second lower electrodes Cb1, Cb2, . . . , Cbm may be disposed under the first metal interconnections a1, a2, . . . , an and the second metal interconnections b1, b2, . . . , bn. Although not shown in
FIG. 5 , data storage elements may be provided on the first lower electrodes and the second lower electrodes. - A storage device, as described above, may include a high-density probe array, and thus, the storage device may store data at high density levels.
- Methods for fabricating a probe array, including the first probes D11, D21, . . . , Dnm and the second probes E11, E21, . . . , Enm, as illustrated
FIG. 1 , will now be described. - An embodiment of one exemplary method of fabricating a probe array according to the inventive principles of this patent disclosure will be described with reference to
FIGS. 1 and 2A through 2I. Referring toFIGS. 1 and 2A , asacrificial substrate 1 is first prepared. Thesacrificial substrate 1 may be formed by sequentially stacking a silicon substrate and a sacrificial insulating layer. The sacrificial insulating layer may be a material layer that may be removed by a wet etching process. For example, the sacrificial insulating layer may be a silicon oxide layer. A firstmold insulating layer 3 may be formed on thesacrificial substrate 1. The firstmold insulating layer 3 may be formed by sequentially stacking a lowermold insulating layer 4, aplanarization stop layer 5, and an uppermold insulating layer 6. - Referring to
FIGS. 1 and 2B , the firstmold insulating layer 3 may be patterned, thereby formingfirst holes 3 a to expose thesacrificial substrate 1. Thefirst holes 3 a may be arranged two-dimensionally in the X and Y directions.First hole spacers 9 may be formed to cover sidewalls of thefirst holes 3 a. After that, a firstconductive layer 15 may be formed on thesacrificial substrate 1 having thefirst hole spacers 9 as shown inFIG. 2C . - Referring to
FIGS. 1 and 2D , the firstconductive layer 15 may be planarized. As a result, first probes 16 may be formed in thefirst holes 3 a, the sidewalls of which are covered by thefirst hole spacers 9. The planarization of the firstconductive layer 15 may be performed using a chemical mechanical polishing (CMP) technique until theplanarization stop layer 5 is exposed. As a result, the uppermold insulating layer 6 is removed and thefirst probes 16 are formed. A top surface of each of thefirst probes 16 may have an area equal to or greater than a bottom surface thereof. A plurality offirst probes 16 may be arranged in the X and Y directions. For example, n first probes D11, D21, . . . , Dn1 may be arranged in the X direction, and m first probes D11, D12, . . . , D1 m may be arranged in the Y direction. Thus, n×m first probes 16 may be arranged. - Referring to
FIGS. 1 and 2E ,first metal interconnections 18 may be formed to cover thefirst probes 16 in the Y direction. Each of thefirst metal interconnections 18 may have a width greater than the width of the top surface of each of the first probes 16. After that, a secondmold insulating layer 21 may be formed on thesacrificial substrate 1 having thefirst metal interconnections 18 as shown inFIG. 2F . - Referring to
FIGS. 1 and 2G ,second holes 24 may be formed through the secondmold insulating layer 21, theplanarization stop layer 5, and the lowermold insulating layer 4. Thesecond holes 24 may be formed between thefirst probes 16 arranged in the X direction. Thereafter,second hole spacers 27 may be formed to cover sidewalls of the second holes 24. A second conductive layer may be formed on thesacrificial substrate 1 having thesecond hole spacers 27 and then planarized until the secondmold insulating layer 21 is exposed. As a result, second probes 30 may be formed in thesecond holes 24 which have sidewalls covered by thesecond hole spacers 27. A top surface of each of thesecond probes 30 may have an area equal to or greater than a bottom surface thereof. The distance between thesecond probes 30 and thefirst probes 16 may be smaller than the resolution limit in a lithography process. -
Second metal interconnections 33 may be formed in the Y direction to cover the second probes 30. The first probes 16 may be formed with a height different from thesecond probes 30 as shown inFIG. 2G . Also, thesecond metal interconnections 33 may be formed on a level different from thefirst metal interconnections 18. - Referring to
FIGS. 1 and 2H , aprobe substrate 36 may be formed above thesacrificial substrate 1 having thesecond metal interconnections 33. Theprobe substrate 36 may be a glass substrate, a silicon substrate or any other suitable substrate. Thereafter, thesacrificial substrate 1 is removed as shown inFIG. 2I , for example, by an etching process. As a result, thesacrificial substrate 1 may be separated from the first andsecond probes probe substrate 36. - The lower
mold insulating layer 4 may be removed during the removal of thesacrificial substrate 1. Also, during the removal of thesacrificial substrate 1, the first andsecond hole spacers second probes second probes first probes 16 and thesecond probes 30 may be smaller than the resolution limit in a lithography process, highly integrated probes may be obtained. - Next, a method of fabricating a probe array according to another exemplary embodiment of the present invention will be described with reference to
FIGS. 1 and 3A through 3K. Referring toFIGS. 1 and 3A , asacrificial substrate 100 is prepared. Thesacrificial substrate 100 may be substantially the same as the sacrificial substrate described with reference toFIG. 2A . Amold insulating layer 103 may be formed on thesacrificial substrate 100. Themold insulating layer 103 may be formed by sequentially stacking a lowermold insulating layer 104, aplanarization stop layer 105, and an uppermold insulating layer 106. Themold insulating layer 103 may be patterned, thereby formingfirst holes 103 a to expose thesacrificial substrate 100. Thefirst holes 103 a may be arranged two-dimensionally in X and Y directions.First hole spacers 109 may be formed to cover sidewalls of thefirst holes 103 a. A firstconductive layer 115 may be formed on thesacrificial substrate 100 having thefirst hole spacers 109. Thereafter, as shown inFIG. 3B , the firstconductive layer 115 may be planarized until a top surface of themold insulating layer 103 is exposed, thereby resulting in formation offirst probes 116. For example, n×mfirst probes 116 may be arranged in the X and Y directions in the same manner as described with reference toFIGS. 1 and 2D . - Referring to 1 and 3C, the
mold insulating layer 103 may be patterned, thereby formingsecond holes 118 between thefirst probes 116 arranged in the X direction.Second hole spacers 121 may be formed to cover sidewalls of thesecond holes 118. Thereafter, a secondconductive layer 124 may be formed on thesacrificial substrate 100 having thesecond hole spacers 121 as shown inFIG. 3D . - Referring to
FIGS. 1 and 3E , the secondconductive layer 124 may be planarized. Specifically, the secondconductive layer 124 may be planarized by a CMP technique until theplanarization stop layer 105 is exposed. Thus, the uppermold insulating layer 106 may be removed during the planarization of the secondconductive layer 124. As a result, the secondconductive layer 124 may be left assecond probes 125 that are surrounded by thesecond hole spacers 121. A portion of thefirst probes 116 may also be removed in the process, thereby shortening the height of thefirst probe 116, which may be surrounded by thefirst hole spacers 109. Thefirst probes 116 may be formed to the same height as the second probes 125. - Referring to
FIGS. 1 and 3F , anintermetal dielectric layer 130 may be formed on thesacrificial substrate 100 having the first andsecond probes intermetal dielectric layer 130 may be patterned, thereby formingfirst grooves 133 to expose thefirst probes 116 arranged in the Y direction. Thereafter,first groove spacers 136 may be formed to cover sidewalls of thefirst grooves 133. Anetch stop layer 127 may be formed before the intermetaldielectric layer 130 is formed. Theetch stop layer 127 may be etched during the formation of thefirst groove spacers 136 such that thefirst probes 116 are exposed. - Referring to
FIGS. 1 and 3G , a first metal layer may be formed on thesacrificial substrate 100 having thefirst groove spacers 136 and then planarized until theintermetal dielectric layer 130 is exposed. As a result,first metal interconnections 139 may be formed in thefirst grooves 133, the sidewalls of which are covered by thefirst groove spacers 136. Accordingly, thefirst interconnections 139 may cover thefirst probes 116 arranged in the Y direction. - Referring to
FIGS. 1 and 3H , theintermetal dielectric layer 130 may be patterned, thereby formingsecond grooves 142 between thefirst interconnections 139. Theetch stop layer 127 may be exposed by thesecond grooves 142. - Referring to
FIGS. 1 and 3I ,second groove spacers 145 may be formed to cover sidewalls of thesecond grooves 142. Theetch stop layer 127 may also be etched during the formation of thesecond groove spacers 145 so that thesecond probes 125 may be exposed. After that, asecond metal layer 148 may be formed on thesacrificial substrate 100 having thesecond groove spacers 145. - Referring to
FIGS. 1 and 3J , thesecond metal layer 148 may be planarized to formsecond metal interconnections 149. In order to prevent short circuiting between thefirst metal interconnections 139 and thesecond metal interconnections 149, thesecond metal layer 148 may be planarized until upper regions of the first andsecond groove spacers first metal interconnections 139 may be spaced apart from thesecond metal interconnections 149 as shown inFIG. 3J . The distance between thefirst metal interconnections 139 and thesecond metal interconnections 149 may be smaller than the resolution limit in a lithography process. - Referring to
FIGS. 1 and 3K , aprobe substrate 152 may be formed above thesacrificial substrate 100 having the first andsecond metal interconnections sacrificial substrate 100 may be removed. The lowermold insulating layer 104 may be removed during the removal of thesacrificial substrate 100. Further, the first andsecond hole spacers sacrificial substrate 100. As a result, the first andsecond probes FIG. 3K . That is, the first andsecond probes probe substrate 152. - Hereinafter, a method of fabricating a probe array according to yet another exemplary embodiment of the present invention will now be described with reference to
FIGS. 1 and 4A through 4G. Referring toFIGS. 1 and 4A , asacrificial substrate 200 is prepared. Thesacrificial substrate 200 may be substantially the same as described with reference toFIG. 2A . Amold insulating layer 203 may be formed on thesacrificial substrate 200. Themold insulating layer 203 may be formed by sequentially forming a lowermold insulating layer 204, aplanarization stop layer 205, and an uppermold insulating layer 206. - The
mold insulating layer 203 may be patterned, thereby formingfirst holes 203 a arranged two-dimensionally in X and Y directions. In this case, a bottom surface of each of thefirst holes 203 a may be narrower than a top surface thereof. After that, a firstconductive layer 208 may be formed on thesacrificial substrate 200 having thefirst holes 203 a as shown inFIG. 4B . Subsequently, the firstconductive layer 208 may be planarized until themold insulating layer 203 is exposed as shown inFIG. 4C . As a result,first probes 209 are formed. The n×mfirst probes 209 may be arranged in the X and Y directions in the same manner as described with reference toFIGS. 1 and 2D . - Referring to
FIGS. 1 and 4D , themold insulating layer 203 may be patterned, thereby formingsecond holes 212 between thefirst probes 209 arranged in the X direction. A bottom surface of each of thesecond holes 212 may be narrower than a top surface thereof. - Referring to
FIGS. 1 and 4E , a second conductive layer may be formed on thesacrificial substrate 200 having thesecond holes 212. - Referring to
FIGS. 1 and 4F , the second conductive layer may be planarized until theplanarization stop layer 205 is exposed, so thatsecond probes 216 left in thesecond holes 212 are formed. The uppermold insulating layer 206 may be removed during the planarization of the second conductive layer, and thus the height of thefirst probes 209 may be reduced. As a result, thefirst probes 209 may be formed to the same height as the second probes 216. The bottom surface of each of the first andsecond probes - Referring to
FIGS. 1 and 4G ,first metal interconnections 239 may be formed to cover thefirst probes 209 arranged in the Y direction. Thereafter,second metal interconnections 249 may be formed between thefirst metal interconnections 239 to cover thesecond probes 216 arranged in the Y direction. The first andsecond metal interconnections second groove spacers second metal interconnections metal interconnections FIGS. 3F through 3K . Thefirst groove spacers 136, thesecond groove spacers 145, thefirst metal interconnections 139, and thesecond metal interconnections 149 shown inFIG. 3K may correspond to thefirst groove spacers 236, thesecond groove spacers 245, thefirst metal interconnections 239, and thesecond metal interconnections 249 ofFIG. 4G , respectively. - A
probe substrate 252 may be disposed above thesacrificial substrate 200 having the first andsecond metal interconnections sacrificial substrate 200 may be removed. The lowermold insulating layer 204 may be removed during the removal of thesacrificial substrate 200. Alternatively, the lowermold insulating layer 204 may be removed after the removal of thesacrificial substrate 200. As a result, thefirst probes 209 and thesecond probes 216 may protrude downward from theprobe substrate 252. - The probe array including the first probes d11, d21, . . . , dnm, the second probes e11, e21, . . . , enm, the third probes f11, f12, . . . , fnm, the fourth probes g11, g12, . . . , gnm, the first metal interconnections a1, a2, . . . , an, and the second metal interconnections b1, b2, . . . , bn described with reference to
FIG. 5 may be easily fabricated by the exemplary methods described with reference toFIGS. 1 , 3A through 3K and 4A through 4G. In other words, the processes performed until the first probes d11, d21, . . . , dnm and the second probes e11, e21, . . . , enm are formed as shown inFIG. 1 may be substantially the same as that described with reference toFIGS. 3A through 4G . - For example, after the first probes d11, d21, . . . , dnm and the second probes e11, e21, . . . , enm are formed using the method described with reference to
FIGS. 3A through 3E , the third probes f11, f12, . . . , fnm and the fourth probes g11, g12, . . . , gnm may be formed by repeating the same method. That is, the third probes and the fourth probes may be formed by substantially the same method as the method of forming the first probes d11, d21, . . . , dnm and the second probes e11, e21, . . . , enm, except that the third probes f11, f12, . . . , fnm and the fourth probes g11, g12, . . . , gnm are disposed between the first probes d11, d21, . . . , dnm and the second probes e11, e21, . . . , enm are arranged in the Y direction. Also, the first metal interconnections a1, a2, . . . , an and the second metal interconnections b1, b2, . . . , bn may be formed in the same manner as described with reference toFIGS. 3F through 3J . - After the first probes d11, d21, . . . , dnm, the second probes e11, e21, . . . , enm, the third probes f11, f12, . . . , fnm, the fourth probes g11, g12, . . . , gnm, the first metal interconnections a1, a2, . . . , an, and the second metal interconnections b1, b2, . . . , bn shown in
FIG. 5 are formed by the above-described methods, a probe substrate may be formed in the same manner as described with reference toFIG. 3K . Accordingly, a detailed description of a method of fabricating the probe array will be omitted here. - Exemplary methods of fabricating a storage medium according to the inventive principles of this patent disclosure will now be described with reference to
FIGS. 5 and 6A through 6F. Referring toFIGS. 5 and 6A , astorage substrate 400 is prepared. For example, thestorage substrate 400 may be a silicon substrate having an insulated surface. Amold insulating layer 403 may be formed on thestorage substrate 400. Themold insulating layer 403 may be patterned, thereby forming a plurality offirst grooves 403 a. For example, mfirst grooves 403 a may be formed in the X direction.First groove spacers 406 may be formed to cover sidewalls of thefirst grooves 403 a. - Referring to
FIGS. 5 and 6B , a first conductive layer may be formed on thestorage substrate 400 having thefirst groove spacers 406, and then planarized until a top surface of themold insulating layer 403 is exposed. As a result, firstlower electrodes 409 may be formed. Subsequently, themold insulating layer 403 may be patterned, thereby formingsecond grooves 412 between the firstlower electrodes 409 as shown inFIG. 6C . - Referring to
FIGS. 5 and 6D ,second groove spacers 415 may be formed to cover sidewalls of thesecond grooves 412. After that, a secondconductive layer 418 may be formed on thestorage substrate 400 having thesecond groove spacers 415. Subsequently, the secondconductive layer 418 may be planarized to form secondlower electrodes 419 as shown inFIG. 6E . Here, the secondconductive layer 418 may be planarized until upper regions of the first andsecond groove spacers lower electrodes lower electrodes - Referring to
FIGS. 5 and 6F , adata storage element 421 may be formed on thestorage substrate 400 having the first and secondlower electrodes data storage element 421 may be formed from a ferroelectric material, a resistance memory material, a polymer or any other suitable material. Thedata storage element 421 may be formed in self-alignment with the first and secondlower electrodes conductive layer 418 is planarized using a CMP technique to expose top surfaces of thegroove spacers lower electrodes groove spacers data storage element 421 may be selectively formed on thelower electrodes data storage element 421 may be formed such that thedata storage element 421 has a lower top surface than the top surfaces of thegroove spacers - The lower electrodes C1, C2, . . . , Cm shown in
FIG. 1 may be formed in the same manner as described with reference toFIGS. 5 and 6A through 6F. Thus, the method of forming the secondlower electrodes 419 is omitted from the methods described with reference toFIGS. 6A through 6F . Therefore, since a method of fabricating a storage medium including the lower electrodes C1, C2, . . . , Cm shown inFIG. 1 may be easily inferred from the methods described with reference toFIGS. 5 and 6A through 6F, a detailed description thereof will be omitted here. - A variety of methods for fabricating probe arrays and storage mediums according to the inventive principles of this patent disclosure have been explained so far. Now, embodiments of probe array structures fabricated according to the inventive principles of this patent disclosure will be described.
- First, an exemplary embodiment of a probe array structure will be described with reference to
FIGS. 1 and 2I . Referring toFIGS. 1 and 2I , first probes 16 andsecond probes 30 are provided under aprobe substrate 36. The first andsecond probes FIG. 1 . The first probes 16 may have a different height from the second probes 30. For example, thesecond probes 30 may have a second height greater than the first height of first probes 16. In this embodiment, the first andsecond probes -
First metal interconnections 18 may be disposed between thefirst probes 16 and theprobe substrate 36, andsecond metal interconnections 33 may be disposed between thesecond probes 30 and theprobe substrate 36. Thesecond metal interconnections 33 may be on a higher level than thefirst metal interconnections 18. A secondmold insulating layer 21 may be interposed between thefirst metal interconnections 18 and theprobe substrate 36. - Next, another exemplary embodiment of a probe array structure according to the inventive principles of this patent disclosure will be described with reference to
FIGS. 1 and 3K . - Referring to
FIGS. 1 and 3K ,first probes 116 andsecond probes 125 are arranged under aprobe substrate 152. The first andsecond probes FIG. 1 .First metal interconnections 139 may be disposed between thefirst probes 116 and theprobe substrate 152, andsecond metal interconnections 149 may be disposed between thesecond probes 125 and theprobe substrate 152. The distance between the first andsecond metal interconnections first probes 116 arranged in the Y direction, and fourth probes may be disposed between thesecond probes 125 arranged in the Y direction. As a result, a probe array including the probes described with reference toFIG. 5 may be formed. - Next, a storage medium according to an exemplary embodiment of the present invention will be described with reference to
FIGS. 5 and 6F . Referring toFIGS. 5 and 6F , a plurality of firstlower electrodes 409 may be disposed on astorage substrate 400. Secondlower electrodes 419 may be disposed between the firstlower electrodes 409. Since the first and secondlower electrodes FIG. 5 , a detailed description thereof will not be presented here. - Next, a storage device assembly and an exemplary method of reading/writing data to/from a storage device according to the inventive principles of this patent disclosure will be described with reference to
FIGS. 7 , 8A and 8B, and 9A through 9D. -
FIG. 7 illustrates the layout of a storage device assembly according to an exemplary embodiment of the present invention,FIG. 8A is an enlarged view of a portion of a storage medium according to an exemplary embodiment of the present invention,FIG. 8B is an enlarged view of a portion of a probe array according to an exemplary embodiment of the present invention, andFIGS. 9A through 9D are plan views illustrating a method of reading/writing data from/to a storage device according to an exemplary embodiment of the present invention. InFIGS. 8A and 8B , and 9A through 9D, reference character “C” refers to a portion of a data storage element, “DS” refers to data storage regions defined on a surface of the data storage element, “A” refers to a first metal interconnection, “B” refers to a second metal interconnection, and “D” and “E” refer to probes. The data storage regions “DS” are regions corresponding to probes of a probe array. The surface of each of the data storage regions “DS” is divided into four quadrants p1, p2, p3, and p4, each of which has a central portion that is defined as a binary digit portion. - Referring to
FIGS. 7 , 8A and 8B, and 9A through 9D, aprobe array 300 is disposed opposite to astorage medium 302. Specifically, theprobe substrate 306 of theprobe array 300 is aligned with thestorage substrate 308 of thestorage medium 302 such that probes 310 disposed under theprobe substrate 306 are aligned with data storage elements formed on thestorage substrate 308, thus forming a storage device. Since components of the probe array and storage medium are explained above, a detailed description thereof will be omitted here. - A
control unit 304 may operate theprobe substrate 306 of theprobe array 302 or thestorage substrate 308 of thestorage medium 302. Thecontrol unit 304 may include digitalized information on the positions of binary digit portions disposed in the data storage regions “DS.” Thecontrol unit 304 including the digitalized position information may transfer theprobe substrate 306 or thestorage substrate 308 such that a probe corresponding to one data storage region “DS” is positioned on one of the four quadrants p1, p2, p3, and p4, i.e., the binary digit portions. As shown inFIGS. 9A through 9D , thecontrol unit 304 may transfer theprobe substrate 306 or thestorage substrate 308 such that a selectedprobe 310 is positioned on a selected quadrant from the four quadrants p1, p2, p3, and p4. A distance by which the probe substrate or the storage substrate is transferred may be 50 nm or less. - The
control unit 304 may transmit electrical signals to the metal interconnections or the lower electrodes. Thus, after a probe is positioned on a selected binary digit portion from the four binary digit portions, thecontrol unit 304 may apply a voltage to the probe positioned on the selected binary digit portion so that data may be read from or written in the selected binary digit portion. - The movement of a probe to the selected quadrants from the four quadrants p1, p2, p3, and p4 may be implemented by the
control unit 304. The control unit may include a digitalized position information of the four quadrants p1, p2, p3, and p4. For example, the digitalized position information of the four quadrants p1, p2, p3, and p4 may be (0,0), (0,1), (1,0), and (1,1). Accordingly, since thecontrol unit 304 may move the probe to a desired binary digit portion disposed in the data storage region “DS,” the storage device may randomly access data. - In some embodiments, a probe may move only within the data storage region “DS.” Since a probe may move in bit units, the probe may only have to move a very short distance to reach the selected binary digit region of the data storage region “DS.” The distance between the probes may be smaller than the resolution limit in a lithography process. Accordingly, since a probe may only need to move a short distance, the durability of the storage device may be increased. As a result, even though some embodiments of storage devices according to the present invention may not use a cantilever for moving the probe along a z-axis, the storage device may be as durable as a conventional storage device. Consequently, data may be read from or written to the storage device at higher speed and may be randomly accessed.
- Since probes of some embodiments of the present invention may be arranged at very high densities, a storage device utilizing the probes may not require a control unit for operation. Instead, a novel storage device in which the probes are fixed onto the data storage region “DS” may be provided according to the present invention. Although such a novel storage device may stores data at lower density than when a control unit is adopted, the fabrication cost may be greatly reduced.
- Exemplary embodiments of the present invention have been disclosed herein and, although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Claims (40)
1. A method of fabricating a probe array, comprising:
forming first probes arranged two-dimensionally in row and column directions on a sacrificial substrate;
forming second probes between the first probes arranged in row direction;
forming a probe substrate above the first and the second probes; and
removing the sacrificial substrate.
2. The method of claim 1 , further comprising forming the first and the second probes such that a distance between the first and the second probes is smaller than the resolution limit in a lithography process.
3. The method of claim 1 , wherein forming the first probes comprises:
forming a mold insulating layer on the sacrificial substrate;
patterning the mold insulating layer, thereby forming first holes exposing the sacrificial substrate;
forming a first conductive layer on the sacrificial substrate having the first holes; and
planarizing the first conductive layer.
4. The method of claim 3 , further comprising, after forming the first holes, forming first hole spacers to cover sidewalls of the first holes.
5. The method of claim 3 , wherein forming the second probes comprises:
patterning the mold insulating layer, thereby forming second holes exposing the sacrificial substrate;
forming a second conductive layer on the sacrificial substrate having the second holes; and
planarizing the second conductive layer.
6. The method of claim 5 , further comprising, after forming the second holes, forming second hole spacers to cover sidewalls of the second holes.
7. The method of claim 5 , wherein the mold insulating layer comprises a lower mold insulating layer, a planarization stop layer, and an upper mold insulating layer that are sequentially stacked, the upper mold insulating layer being removed during the planarization of the second conductive layer.
8. The method of claim 1 , wherein a top surface of each of the first and second probes has an area equal to or greater than a bottom surface thereof.
9. The method of claim 1 , further comprising, before forming the probe substrate:
forming first metal interconnections to cover the first probes arranged in the column direction; and
forming second metal interconnections between the first metal interconnections to cover the second probes.
10. The method of claim 9 , wherein forming the first metal interconnections comprises:
forming an intermetal dielectric layer on the sacrificial substrate having the first and second probes;
patterning the intermetal dielectric layer, thereby forming first grooves exposing the first probes arranged in the column direction;
forming first groove spacers to cover sidewalls of the first grooves;
forming a first metal layer on the sacrificial substrate having the first groove spacers; and
planarizing the first metal layer.
11. The method of claim 10 , wherein forming the second metal interconnections comprises:
patterning the intermetal dielectric layer, thereby forming second grooves exposing the second probes between the first metal interconnections;
forming second groove spacers to cover sidewalls of the second grooves;
forming a second metal layer on the sacrificial substrate having the second groove spacers; and
planarizing the second metal layer.
12. The method of claim 1 , further comprising, before forming the probe substrate:
forming third probes between the first probes arranged in the column direction; and
forming fourth probes between the second probes arranged in the column direction.
13. The method of claim 12 , further comprising, after forming the fourth probes:
forming first metal interconnections to cover the first and third probes arranged in the column direction; and
forming second metal interconnections between the first metal interconnections to cover the second and fourth probes.
14. The method of claim 1 , wherein forming the probes comprises:
forming a first mold insulating layer on the sacrificial substrate;
forming the first probes penetrating the first mold insulating layer;
forming first metal interconnections to cover the first probes arranged in the column direction;
forming a second mold insulating layer on the sacrificial substrate having the first metal interconnections;
forming the second probes between the first probes arranged in the row direction, wherein the respective second probes are formed through the second mold insulating layer and the first mold insulating layer; and
forming second metal interconnections to cover the second probes arranged in the column direction.
15. The method of claim 14 , wherein forming the first probes comprises:
patterning the first mold insulating layer, thereby forming first holes exposing the sacrificial substrate;
forming first hole spacers to cover sidewalls of the first holes;
forming a first conductive layer on the first mold insulating layer to fill the first holes; and
planarizing the first conductive layer.
16. The method of claim 14 , wherein forming the second probes comprises:
patterning the second mold insulating layer and the first mold insulating layer, thereby forming second holes exposing the sacrificial substrate;
forming a second conductive layer on the sacrificial substrate having the second holes; and
planarizing the second conductive layer.
17. A method of fabricating a storage device, comprising:
forming a data storage element on a storage substrate;
forming probes on a sacrificial substrate;
forming a probe substrate over probes;
removing the sacrificial substrate; and
aligning the probe substrate and the storage substrate such that the data storage element is disposed opposite to the probes.
18. The method of claim 17 , wherein the method of forming the probes further compromises:
forming first, second, third and fourth probes in the sacrificial substrate;
forming first metal interconnections to cover the first and the third probes arranged in the column direction; and
forming second metal interconnections between the first metal interconnections to cover the second and the fourth probes.
19. The method of claim 17 further comprising forming a plurality of lower electrodes before forming the data storage element.
20. The method of claim 17 , wherein the data storage element is formed of one selected from the group consisting of a ferroelectric material, a resistance memory material, and a polymer.
21. The method of claim 17 , further comprising, before forming the data storage element, forming line-shaped lower electrodes parallel to the row direction.
22. The method of claim 17 , further comprising forming the probe substrate over the probes opposite to the sacrificial substrate.
23. A probe array comprising:
first probes arranged two-dimensionally in row and column directions;
second probes disposed between the first probes arranged in the row direction, a distance between the first and second probes being smaller than the resolution limit in a lithography process; and
a probe substrate disposed on the first and second probes.
24. The probe array of claim 23 , further comprising:
first metal interconnections disposed between the probe substrate and the first probes arranged in the column direction; and
second metal interconnections disposed between the probe substrate and the second probes arranged in the column direction.
25. The probe array of claim 23 , further comprising:
third probes disposed between the first probes arranged in the column direction, a distance between the first and third probes being smaller than the resolution limit in a lithography process; and
fourth probes disposed between the second probes arranged in the column direction, a distance between the second and fourth probes being smaller than the resolution limit in a lithography process.
26. The probe array of claim 23 , wherein each of the first probes has a first height, and each of the second probes has a second height greater than the first height.
27. A storage device comprising:
a storage substrate;
a data storage element disposed on the storage substrate and having a plurality of data storage regions;
a probe substrate over the data storage element; and
probes positioned on the data storage element and aligned with the storage substrate.
28. The storage device of claim 27 , wherein the probes comprise:
first probes positioned on the data storage element, fixed under the probe substrate, and arranged two-dimensionally in row and column directions; and
second probes disposed between the first probes under the probe substrate, a distance between the first and second probes being smaller than the resolution limit in a lithography process.
29. The storage device of claim 28 , further comprising:
third probes disposed between the first probes arranged in the column direction, a distance between the first and third probes being smaller than the resolution limit in a lithography process; and
fourth probes disposed between the second probes arranged in the column direction, a distance between the second and fourth probes being smaller than the resolution limit in a lithography process.
30. A storage device assembly comprising:
a data storage element disposed on a storage substrate and having a plurality of data storage regions;
a probe substrate on the data storage element;
first probes positioned on the data storage element, fixed under the probe substrate, and arranged two-dimensionally in row and column directions;
second probes disposed between the first probes under the probe substrate, a distance between the first and second probes being smaller than the resolution limit in a lithography process; and
a control unit to move the probe substrate or the storage substrate.
31. The storage device assembly of claim 30 , wherein the first and second probes correspond to the respective data storage regions, a surface of each of the data storage regions is divided into multiple quadrants, and a central portion of each of the multiple quadrants is a binary digit portion.
32. The storage assembly of claim 31 , wherein each of the data storage regions is divided into four quadrants.
33. The storage device assembly of claim 31 , wherein the control unit moves the probe substrate or the storage substrate such that one probe corresponding to one data storage region is positioned on one selected from the multiple quadrants of the data storage region.
34. The storage device assembly of claim 34 , wherein a distance by which the probe substrate or the storage substrate moves is 50 nm or less.
35. The storage device assembly of claim 31 , wherein the control unit comprises digitalized position information of the binary digit portions disposed in the data storage regions.
36. The storage device assembly of claim 30 , further comprising:
line-shaped lower electrodes disposed between the storage substrate and the data storage element; and
line-shaped metal interconnections disposed between the probe substrate and the first and second probes across the lower electrodes.
37. A method of reading/writing data from/to a storage device, comprising:
two-dimensionally arranging probes in row and column directions on a data storage element having a plurality of data storage regions, wherein the probes correspond to the respective data storage regions, a surface of each of the data storage regions is divided into multiple quadrants, and a central portion of each of the multiple quadrants is a binary digit portion.
38. The method of claim 37 , further comprising:
moving the probes such that one of the probes is aligned with one of the multiple binary digit portions; and
reading/writing data from/to the selected binary digit portion by applying a voltage to the probe positioned on the selected binary digit portion.
39. A method of fabricating a probe array, comprising:
forming probes arranged on a sacrificial substrate;
forming a probe substrate above the probes; and
removing the sacrificial substrate.
40. The method of claim 39 , further comprising forming the plurality of probes such that a distance between the probes is smaller than the resolution limit in a lithography process.
Applications Claiming Priority (2)
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KR10-2006-0021479 | 2006-03-07 | ||
KR1020060021479A KR100702032B1 (en) | 2006-03-07 | 2006-03-07 | High density probe array, storage device having the high density probe array, and fabrication methods thereof |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080318086A1 (en) * | 2007-06-19 | 2008-12-25 | Nanochip, Inc. | Surface-treated ferroelectric media for use in systems for storing information |
US20080316897A1 (en) * | 2007-06-19 | 2008-12-25 | Nanochip, Inc. | Methods of treating a surface of a ferroelectric media |
CN110136617A (en) * | 2019-05-15 | 2019-08-16 | 业成科技(成都)有限公司 | Probe and preparation method thereof |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106847723B (en) * | 2011-07-06 | 2020-02-18 | 塞莱敦体系股份有限公司 | Test system with probe device and indexing mechanism |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5671030A (en) * | 1990-08-30 | 1997-09-23 | Canon Kabushiki Kaisha | Liquid crystal panel having a color filter with passivation and insulating layers extending to the seal |
US6011608A (en) * | 1997-03-27 | 2000-01-04 | Kabushiki Kaisha Toshiba | Liquid crystal display panel wherein inorganic film is formed over an inorganic insulating film overlying wirings extending across seal area |
US6683668B2 (en) * | 2001-05-24 | 2004-01-27 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof, and reworking method of alignment film using the same |
US6690186B2 (en) * | 1994-07-07 | 2004-02-10 | Tessera, Inc. | Methods and structures for electronic probing arrays |
US6697138B2 (en) * | 2001-02-22 | 2004-02-24 | Lg Phillips Lcd Co., Ltd. | Transflective liquid crystal display device and manufacturing method for the same |
US20040047275A1 (en) * | 2002-05-23 | 2004-03-11 | International Business Machines Corporation | Storage device and method for operating a storage device |
US6819389B2 (en) * | 2001-12-03 | 2004-11-16 | Hitachi, Ltd. | Liquid crystal display device with a substrate having an opening on an organic film thereof to accommodate sealing material therethrough |
US6859254B2 (en) * | 2001-12-31 | 2005-02-22 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method for fabricating the same |
US20050253606A1 (en) * | 2003-02-04 | 2005-11-17 | Microfabrica Inc. | Microprobe tips and methods for making |
US20060108678A1 (en) * | 2002-05-07 | 2006-05-25 | Microfabrica Inc. | Probe arrays and method for making |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH081444B2 (en) * | 1992-04-22 | 1996-01-10 | 株式会社日本マイクロニクス | Probe assembly |
TW341747B (en) * | 1996-05-17 | 1998-10-01 | Formfactor Inc | Techniques of fabricating interconnection elements and tip structures for same using sacrificial substrates |
CN1208624C (en) * | 1996-05-17 | 2005-06-29 | 福姆法克特公司 | Microelectronic tontact structure and method of making same |
KR100280544B1 (en) * | 1998-12-31 | 2001-03-02 | 김영환 | Probe Card for Semiconductor Wafer Inspection |
JP4017058B2 (en) | 1999-05-31 | 2007-12-05 | 誠 石田 | Probe and sensor equipped with the same |
KR100379415B1 (en) | 2000-01-13 | 2003-04-10 | 엘지전자 주식회사 | ferroelectric recording media and method for fabricating the same |
JP3990232B2 (en) | 2002-08-26 | 2007-10-10 | Necエンジニアリング株式会社 | Probe card test head structure |
KR20040042387A (en) | 2002-11-14 | 2004-05-20 | 엘지전자 주식회사 | Method of manufacturing writing media for use in probe type data storage device |
JP2004213751A (en) | 2002-12-27 | 2004-07-29 | Sony Corp | Two dimensional memory and multi-probe two dimensional memory system |
-
2006
- 2006-03-07 KR KR1020060021479A patent/KR100702032B1/en not_active IP Right Cessation
- 2006-08-15 US US11/464,571 patent/US7583095B2/en not_active Expired - Fee Related
-
2007
- 2007-03-07 CN CN2007100854990A patent/CN101034573B/en not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5671030A (en) * | 1990-08-30 | 1997-09-23 | Canon Kabushiki Kaisha | Liquid crystal panel having a color filter with passivation and insulating layers extending to the seal |
US6690186B2 (en) * | 1994-07-07 | 2004-02-10 | Tessera, Inc. | Methods and structures for electronic probing arrays |
US6011608A (en) * | 1997-03-27 | 2000-01-04 | Kabushiki Kaisha Toshiba | Liquid crystal display panel wherein inorganic film is formed over an inorganic insulating film overlying wirings extending across seal area |
US6697138B2 (en) * | 2001-02-22 | 2004-02-24 | Lg Phillips Lcd Co., Ltd. | Transflective liquid crystal display device and manufacturing method for the same |
US6683668B2 (en) * | 2001-05-24 | 2004-01-27 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof, and reworking method of alignment film using the same |
US6819389B2 (en) * | 2001-12-03 | 2004-11-16 | Hitachi, Ltd. | Liquid crystal display device with a substrate having an opening on an organic film thereof to accommodate sealing material therethrough |
US6859254B2 (en) * | 2001-12-31 | 2005-02-22 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method for fabricating the same |
US20060108678A1 (en) * | 2002-05-07 | 2006-05-25 | Microfabrica Inc. | Probe arrays and method for making |
US20040047275A1 (en) * | 2002-05-23 | 2004-03-11 | International Business Machines Corporation | Storage device and method for operating a storage device |
US20050253606A1 (en) * | 2003-02-04 | 2005-11-17 | Microfabrica Inc. | Microprobe tips and methods for making |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080318086A1 (en) * | 2007-06-19 | 2008-12-25 | Nanochip, Inc. | Surface-treated ferroelectric media for use in systems for storing information |
US20080316897A1 (en) * | 2007-06-19 | 2008-12-25 | Nanochip, Inc. | Methods of treating a surface of a ferroelectric media |
CN110136617A (en) * | 2019-05-15 | 2019-08-16 | 业成科技(成都)有限公司 | Probe and preparation method thereof |
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US7583095B2 (en) | 2009-09-01 |
CN101034573B (en) | 2011-04-06 |
CN101034573A (en) | 2007-09-12 |
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