US20070222486A1

US20070222486A1 - Driver circuit connected to pulse shaping circuitry

Info

Publication number: US20070222486A1
Application number: US11/745,252
Authority: US
Inventors: Kenneth Koch II; Mozammel Hossain
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-06-13
Filing date: 2007-05-07
Publication date: 2007-09-27
Also published as: US20040169973A1; US6753708B2; US7239185B2; FR2844404A1; US20040160261A1; US20030231034A1

Abstract

In one embodiment a circuit, comprises a first terminal coupled to a voltage source switchable between a first voltage level and a second voltage level, a driver comprising a first inverter, a second inverter, an output stage comprising a PFET and an NFET having source drain paths connected in series across opposite power supply terminals, the PFET and NFET each having a gate electrode that switches on and off in response to a voltage applied to the gate electrode being on opposite sides of a threshold, first pulse shaping circuitry coupled to the first inverter and the PFET and comprising a first resistor and a first capacitor, the first capacitor being connected across the gate electrode of the PFET and a first of the power supply terminals, the first capacitor comprising an NFET, and second pulse shaping circuitry coupled to the second inverter and the NFET and comprising a second resistor and a second capacitor, the second resistor being connected the gate electrode of the NFET and a first of the power supply terminals, the first capacitor comprising an PFET.

Description

RELATED APPLICATIONS

This application is a continuation of commonly assigned and co-pending U.S. patent application Ser. No. 10/777,174, filed Feb. 13, 2004, which is a continuation of commonly assigned U.S. patent application Ser. No. 10/167,493, filed Jun. 13, 2002 the disclosures of which are incorporated by reference herein in their entirety.

BACKGROUND

The present invention relates generally to driver circuits and, more particularly, to a driver circuit including first and second opposite conductivity type transistors which are prevented from conducting simultaneously during a transition between first and second voltage levels by pulse shaping circuitry, and to a method of operating same.
One type of driver circuit that is frequently employed, particularly on integrated circuit chips, includes first and second opposite conductivity type transistors, each including a control electrode and a path which is switched on and off between a pair of further electrodes. Each path is switched on and off in response to a voltage applied to the control electrode of the particular transistor being on opposite sides of a threshold. The paths of the first and second transistors are connected in series across terminals of a DC power supply. An output terminal between the series connected paths drives a load.
In a typical integrated circuit chip, the transistors are opposite conductivity type metal oxide semiconductor field effect transistors (MOSFETs), wherein the control electrodes are gate electrodes and the further electrodes are source and drain electrodes. Such a driver includes a positive channel field effect transistor (PFET) and a negative channel field effect transistor (NFET). The switched path between the source and drain electrodes of each field effect transistor (FET) is frequently referred to as a source drain path and the source drain paths of the PFET and NFET are connected in series across opposite polarity terminals of the power supply.
The typical integrated circuit chip includes many such drivers that are responsive to bilevel sources having positive and negative going transitions between first and second voltage levels that are usually approximately equal to the voltages at the power supply terminals. The bilevel sources can be either data or clock sources. In response to the bilevel source being at the first (low) voltage level, the PFET and NFET are respectively on and off, while the NFET and PFET are respectively on and off in response to the bilevel source being at the second (high) voltage level. A relatively high impedance is provided by the source drain path of the NFET or PFET which is off so that substantial current does not flow through both the PFET and NFET of the driver while the bilevel source is at the first and second voltage levels. To minimize power consumption, the PFET and NFET should not be on at the same time during the transitions.
Many of the drivers of the foregoing type on a typical integrated circuit chip are simultaneously responsive to the transitions. If many of the drivers of the foregoing type are simultaneously responsive to the transitions and if the PFET and NFET of each of these drivers were on at the same time during the transitions, a substantial amount of current, frequently referred to as crow bar current, would be drawn from the power supply. The current could be so great as to cause overheating of the integrated circuit chip and result in a substantial decrease in the voltage between the power supply terminals. Similar problems can also exist with bipolar drivers including PNP and NPN transistors having series connected emitter collector paths.
In the past, one approach to resolving the problem has involved complicated circuitry which takes into account processing variables in making the integrated circuits, as well as changes that occur to the circuit elements as a result of power supply voltage and temperature variations of the integrated circuit chip carrying the circuitry. Another complicated approach has involved staging a number of field effect transistors. These complicated circuits occupy a significant amount of space on the integrated circuit chip and consume additional power, resulting in possible unnecessary heating of the chip.
There is a prior art circuit wherein conventional capacitors are connected in negative feedback paths to the gates of opposite conductivity type field effect transistors having series connected source drain paths. One electrode of each capacitor is connected to an output terminal between the source drain paths, while the other electrode of each capacitor is connected to the gate electrode of one of the field effect transistors. A problem with this approach is that the voltage across each of the capacitors varies as a function of load variations. Hence, switching of the field effect transistors is a function of the load variations which can result in poor control. In this prior art circuit, both field effect transistors appear to be turned on simultaneously during a transition, resulting in substantial current flow. Another problem with this prior art circuit is that the capacitors are charged and discharged through source drain paths of additional field effect transistors, rather than through resistors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a preferred embodiment of the present invention; and
FIG. 2 includes a series of waveforms helpful in describing the operation of the circuit of FIG. 1.

DETAILED DESCRIPTION

Reference is now made to FIG. 1 of the drawing wherein driver circuit 10 is illustrated as being connected between bilevel voltage source 12 and load 14. Driver circuit 10, source 12 and load 14 are complementary metal oxide semiconductor (CMOS) circuits on an integrated circuit chip having a positive DC power supply terminal 16, at a potential of +1.0Vdd, and a negative DC power supply terminal 18, at ground potential, i.e., 0Vdd. The bilevel output of voltage source 12, which can be either a data or clock source, typically switches between potentials of 1.0Vdd and 0Vdd, and has positive and negative going short duration transitions between these potentials. Load 14, typically other circuitry on the integrated circuit and/or off chip circuitry, is subject to substantial variations, depending upon the number of circuits in load 14 which are activated at a particular time.
Driver circuit 10 includes inverters 20 and 22, connected to be driven in parallel by the output of source 12. Driver circuit 10 also comprises output stage 24, including output terminal 26 which is connected in a DC circuit to drive load 14. Output stage 24 is connected to be responsive to output voltages of inverters 20 and 22 via DC circuits 28 and 30 which respectively include switched voltage controlled shunt capacitors 32 and 34.
Inverter 20 includes complementary transistors in the form of PFET 36 and NFET 38 having gate electrodes connected to be driven in parallel by the bilevel output of source 12 at terminal 39 and source drain paths which are switched on and off in a complementary manner by the voltage applied to the gate electrodes of the PFET and NFET. The source drain paths of PFET 36 and NFET 38 are connected in series with each other and across DC power supply terminals 16 and 18. A resistive impedance, i.e., resistor 40, is connected in series with the source drain paths of PFET 36 and NFET 38, between the drains of the PFET and NFET of inverter 20. The use of resistor 40 as a resistive impedance, is advantageous because it (1) enables a lower resistance to be achieved and (2) provides better resistance value stability with regard to variations of integrated circuit temperature and power supply voltage, and integrated circuit manufacturing. A first end of DC circuit 28 is connected to a common terminal at one side of resistor 40 and the drain electrode of PFET 36.
Inverter 22 is similar to inverter 20, in that inverter 22 includes PFET 42 and NFET 44 and a resistive impedance in the form of resistor 46. The gate electrodes of PFET 42 and NFET 44 are connected to be driven in parallel by the output voltage of source 12 at terminal 39 and the source drain paths of PFET 42 and NFET 44 are connected in series with each other and a resistive impedance, i.e., resistor 46. However, inverter 22 differs from inverter 20 because the common terminal of resistor 46 and the drain of NFET 44 are connected to a first end of DC circuit 30. Inverters 20 and 22 thus can be considered as switching circuits for selectively supplying, to the output terminals thereof, voltages substantially equal to the power supply voltages 1.0Vdd and 0Vdd.
Output stage 24 includes PFET 48 and NFET 50 having source drain paths connected in series with each other across DC power supply terminals 16 and 18. The drain electrodes of PFET 48 and NFET 50 have a common connection to output terminal 26 which is connected to load 14. PFET 48 and NFET 50 have gate electrodes respectively connected to the second ends of DC circuits 28 and 30. The gate electrodes of PFET 48 and NFET 50 are respectively connected to first electrodes of shunt capacitors 32 and 34. The second electrode of capacitor 32 is connected to ground DC power supply terminal 18, while the second electrode of capacitor 34 is connected to +Vdd power supply terminal 16. Because of the connections of the electrodes of capacitors 32 and 34 to the gate electrodes of PFET 48 and NFET 50 and to the constant voltages at the power supply terminals 16 and 18, the waveforms across the capacitors are independent of the current that load 14 draws from output stage 24. PFET 48 and NFET 50 have thresholds such that (1) in response to the voltage applied to the gate electrode of PFET 48 being less than and greater than the threshold voltage of the PFET, the PFET source drain path is turned on and off, respectively, and (2) in response to the voltage applied to the gate electrode of NFET 48 being less than and greater than the threshold voltage of the NFET, the NFET source drain path is turned off and on, respectively.
In the preferred embodiment, capacitors 32 and 34 respectively comprise NFET 52 and PFET 54. One electrode of each of capacitors 32 and 34 respectively comprises the gate electrodes of NFET 52 and PFET 54. The other electrode of each of capacitors 32 and 34 respectively comprises the source drain paths of NFET 52 and PFET 54. The source and drain electrodes of NFET 52 are connected together and to ground terminal 18, while the source and drain paths of PFET 54 are connected together and to +Vdd power supply terminal 16. Each of NFET 52 and PFET 54 includes an insulator between the gate electrode and the source drain path thereof.
The circuitry of FIG. 1, including the thresholds of PFET 48 and NFET 50, is such that the source drain paths of PFET 48 and NFET 50 are never simultaneously on. Consequently, crowbar current cannot flow between power supply terminals 16 and 18 through the source drain paths of PFET 48 and NFET 50.
Reference is now made to FIG. 2 of the drawing which is helpful in describing the operation of the circuit of FIG. 1. The output voltage of source 12, indicated by bilevel waveform 60, is illustrated as having a 50-50 duty cycle, although it is to be understood that the output of source 12 can have any suitable duty cycle for a clock or data source.
During the half cycles of source 12 when the output voltage of the source has a value of 1.0Vdd, NFETs 38 and 44 are turned on and PFETs 36 and 42 are turned off. Consequently, a voltage approximately equal to the ground voltage at terminal 18 is supplied to the first end of DC circuit 28 (at the drain of PFET 36) through the low impedance, turned on source drain path of PFET 38 and resistor 40. At the same time, the ground voltage at terminal 18 is supplied to the first, input end of DC circuit 30 (at the drain of NFET 44) through the low impedance, turned on source drain path of NFET 44. Just before the end of the half cycles when the output voltage of source 12 has a value of 1.0Vdd, inverters 20 and 22 apply low voltages, substantially equal to the voltage at ground terminal 18, to the gate electrodes of PFET 48 and NFET 50, causing the PFET and-NFET to be respectively turned on and off. In addition, at this time there is virtually no voltage across the insulator of NFET 52 because the gate electrode thereof and the source drain path thereof are both substantially at ground potential, resulting in the voltage across capacitor 32 being zero. In contrast, because (1) NFET 44 is turned on, causing the input of DC path 30 to be substantially at ground, i.e., 0Vdd, and (2) the source drain path of PFET 54 is at 1.0Vdd, there is a voltage substantially equal to 1.0Vdd across the insulator of PFET 54 that comprises capacitor 34.
During the half cycles of source 12 when the output voltage of the source has a value of 0Vdd, NFETs 38 and 44 are turned off and PFETs 36 and 42 are turned on. Consequently, the 1.0Vdd voltage at terminal 16 is supplied to the first, input end of DC circuit 28 (at the drain of PFET 36) through the low impedance, turned on source drain path of PFET 36. At the same time, the 1.0Vdd voltage at terminal 16 is supplied to the first end of DC circuit 30 (at the drain of NFET 44) through resistor 46 and the low impedance, turned on source drain path of PFET 42. Just before the end of the half cycles when the output voltage of source 12 has a value of 0Vdd, inverters 20 and 22 apply high voltages, substantially equal to the 1.0Vdd voltage at power supply terminal 16, to the gate electrodes of PFET 48 and NFET 50, causing the PFET and NFET to be respectively turned off and on. Also, at this time there is virtually no voltage across the insulator of PFET 54 because the gate electrode thereof and the source drain path thereof are both substantially at 1.0Vdd, resulting in the voltage across capacitor 34 being zero. In contrast, because (1) PFET 36 is turned on, causing the input of DC path 28 to be substantially at 1.0Vdd, and (2) the source drain path of NFET 52 is at ground potential, there is a voltage substantially equal to 1.0Vdd across the insulator of NFET 52, which has a finite capacitance value.
As indicated by waveforms 62 and 63, PFET 48 is turned on during intervals 64, while NFET 50 is turned on during intervals 66; intervals 64 and 66 alternate with and are mutually exclusive of each other.
At the beginning of and during short duration negative going transitions 68 of the voltage of source 12, from 1.0Vdd to 0Vdd, as indicated by waveform 60, PFET 36 rapidly goes from an off to an on condition while NFET 38 rapidly goes from an on to an off condition. In response to transitions 68, the voltage at the drain of PFET 36, at the input of DC circuit 28, changes rapidly in the positive direction, so that the voltage applied to the gate of PFET 48, indicated by waveform 69, changes rapidly, as indicated by waveform portion 70, from a value substantially equal to 0Vdd to a value substantially equal to 1.0Vdd. This results in PFET 48 changing rapidly from an on condition to an off condition, as indicated by the negative going transitions at the ends of intervals 64 of waveform 62, but has no immediate effect on the zero voltage across discharged capacitor 32.
At the beginning of and during the negative going transitions 68, PFET 42 rapidly goes from an off condition to an on condition while NFET 44 rapidly goes from an on to an off condition. Because capacitor 34 is fully charged to 1.0Vdd at the beginning of the negative going transitions 68 the current flow through resistor 46 does not increase suddenly, but increases exponentially at a rate primarily determined by the resistance of resistor 46 and the finite capacitance of capacitor 34. The exponential increase in the current through resistor 46 causes the voltage across capacitor 34 and between the gate and source of NFET 50 to increase exponentially, as indicated by portion 72 of waveform 74, which represents the voltage across the gate and source of NFET 50. During portion 72, the voltage across the gate of NFET 50 is less than the threshold of the NFET, which is assumed in FIG. 2 to be 0.33Vdd. Thus, NFET 50 remains off for a predetermined interval subsequent to negative going transition 68. During this predetermined interval, both PFET 48 and NFET 50 are off to prevent crowbar current from flowing through the source drain paths thereof between power supply terminals 16 and 18. In response to the voltage across the gate of NFET 50 crossing the threshold of the NFET, the NFET is turned on, as indicated by the positive going transition at the beginning of intervals 66 of waveform 63, whereby current can flow between load 14 and NFET 50 during intervals 66.
As exponential current continues to flow through capacitor 34 and resistor 46 while the voltage of source 12 equals 0Vdd, there is a gradual decrease in the slope of the voltage applied to the gate of NFET 50, as indicated by portion 76 of waveform 74. To enable the target voltage of 1.0Vdd to be achieved, the resistance of resistor 46 and capacitance of capacitor 34 and the duration of the half cycle of source 12 between transitions 68 and 80 of waveform 60 are properly selected. Waveform 74 reaches its target value of 1.0Vdd shortly before the occurrence of positive going transition 80 of waveform 60.
During the entire half cycle of source 12 while the source is applying a voltage of 0Vdd to driver circuit 10 the voltage at the gate of PFET 48 remains substantially at 1.0Vdd, as indicated by portion 82 of waveform 69. This is because PFET 36 couples the 1.0Vdd voltage at terminal 16 to the gate of PFET 48.
In response to positive going transitions 80 of waveform 60, complementary operations occur in driver circuit 10 relative to the operations which occur in response to the negative going transitions 68. Hence, the current flowing through resistor 46 suddenly decreases, as does the voltage at the gate of NFET 50, as indicated by portion 84 of waveform 74. Thereby, NFET 50 suddenly goes from an on to an off state, as indicated by the negative transitions of waveform 63 at the end of intervals 66. In response to the positive going transition 80, the voltage at the gate of PFET 48 decreases exponentially as indicated by portion 86 of waveform 69. PFET 48 remains off until its threshold is crossed, which is assumed in FIG. 2 to be at 0.67Vdd. In response to waveform portion 86 crossing the 0.67Vdd threshold, PFET 48 is turned on, as indicated by the positive going transitions of waveform 62 at the beginning of intervals 64. The voltage across capacitor 32 continues to decrease exponentially until the voltage across capacitor 32 goes substantially to zero. The voltage across capacitor 32 and at the gate of PFET 48 reach a target value substantially equal to 0Vdd shortly before the next negative going transition 68 of waveform 60. Operation continues in this matter.
While there has been described and illustrated a specific embodiment of the invention, it will be clear that variations in the details of the embodiment specifically illustrated and described may be made without departing from the true spirit and scope of the invention as defined in the appended claims. For example, the principles of the invention are applicable to bipolar transistors and discrete capacitors, although the use of FETs for the transition and capacitors is particularly advantageous for integrated circuits.

Claims

1. A circuit, comprising:

a first terminal coupled to a voltage source switchable between a first voltage level and a second voltage level;

a driver comprising:

a first inverter;

a second inverter;

an output stage comprising a PFET and an NFET having source drain paths connected in series across opposite power supply terminals, the PFET and NFET each having a gate electrode that switches on and off in response to a voltage applied to the gate electrode being on opposite sides of a threshold;

first pulse shaping circuitry coupled to the first inverter and the PFET and comprising a first resistor and a first capacitor, the first capacitor being connected across the gate electrode of the PFET and a first of the power supply terminals, the first capacitor comprising an NFET; and

second pulse shaping circuitry coupled to the second inverter and the NFET and comprising a second resistor and a second capacitor, the second resistor being connected the gate electrode of the NFET and a first of the power supply terminals, the first capacitor comprising an PFET.

2. The circuit of claim 1, wherein the first inverter comprises a PFET and an NFET having gate electrodes connected to be driven in parallel by the voltage at the first terminal and source drain paths which are switched on an off in a complementary manner in response to the voltage at the first terminal.

3. The circuit of claim 2, wherein the PFET of the first inverter comprises a source drain path coupled to a supply voltage and the NFET of the first inverter comprises a source drain path coupled to ground.

4. The circuit of claim 2, wherein the first resistor is connected between the source drain path of the NFET of the first inverter and the output terminal of the first inverter.

5. The circuit of claim 1, wherein the second inverter comprises a PFET and an NFET having gate electrodes connected to be driven in parallel by the voltage at the first terminal and source drain paths which are switched on an off in a complementary manner in response to the voltage at the first terminal.

6. The circuit of claim 5, wherein the PFET of the second inverter comprises a source drain path coupled to a supply voltage and the NFET of the first inverter comprises a source drain path coupled to ground.

7. The circuit of claim 5, wherein the first resistor is connected between the source drain path of the NFET of the first inverter and the output terminal of the first inverter.

8. The circuit of claim 1 wherein the first and second capacitors respectively include an NFET and a PFET.

9. The circuit of claim 1 wherein the voltage source cycles between a high voltage level and a ground voltage level.

10. The circuit of claim 9, wherein, in response to a transition of the voltage source between a ground level and a high voltage level, the PFET of the output stage is activated and the NFET of the output stage is deactivated.

11. The circuit of claim 10, wherein, in response to a transition of the voltage source between a ground level and a high voltage level, the first pulse shaping circuit introduces a delay in the activation of the PFET of the output stage.

12. The circuit of claim 9, wherein, in response to a transition of the voltage source between a high voltage level and a ground level, the NFET of the output stage is activated and the PFET of the output stage is deactivated.

13. The circuit of claim 10, wherein, in response to a transition of the voltage source between a high voltage level and a ground level, the second pulse shaping circuit introduces a delay in the activation of the NFET of the output stage.

14. A method of operating a driver circuit responsive to a source voltage that cycles between a high voltage level and a ground level, the driver circuit comprising a PFET and an NFET, each including a control electrode and a source path controlled in response to a voltage applied to the control electrode, the source drain paths of the first and second transistors being connected in series across opposite power supply terminals, and an output terminal between the series connected paths, the method comprising:

during a transition of the voltage source between a ground level and a high voltage level, activating the PFET of the output stage and deactivating the NFET of the output stage, wherein activating the PFET of the output stage comprises delaying a threshold voltage value at the control electrode of the PFET; and

during a transition of the voltage source between a high voltage level and a ground level, activating the NFET of the output stage and deactivating the PFET of the output stage, wherein activating the NFET of the output stage comprises delaying a threshold voltage value at the control electrode of the NFET.

15. The method of claim 14, wherein delaying a threshold voltage value at the control electrode of the PFET comprises charging a shunt capacitor coupled to the PFET.

16. The method of claim 15, further comprising discharging the shunt capacitor coupled to the PFET during a time period when the source voltage is at a ground voltage level.

17. The method of claim 14, wherein delaying a threshold voltage value at the control electrode of the NFET comprises charging a shunt capacitor coupled to the NFET.

18. The method of claim 17, further comprising discharging the shunt capacitor coupled to the NFET during a time period when the source voltage is at a high voltage level.