US 20070234088 A1
Embodiments of the present invention are directed at identifying an idle state for a processor that minimizes power consumption. In accordance with one embodiment, a method for identifying a target idle state that does not require a linear progression into any intermediate states is provided. More specifically the method includes collecting data from a plurality of data sources that describes activities occurring on the computer and/or attributes of the hardware platform. Then, using the collected data, a target idle state for the processor is calculated. Finally, if the current idle state of the processor is different than the target idle state, the method causes the idle state of the processor to be changed to the target idle state.
1. In a computer that includes a processor and a software system for managing the power consumption of the processor, a computer-implemented method of identifying a target idle state for the processor, the method comprising:
(a) obtaining data from a plurality of data sources that:
(i) measures activities that have or will occur on the computer;
(ii) describes attributes of the hardware on the computer;
(b) using the data collected to calculate a target idle state that minimizes power consumption; and
(c) changing the idle state of the processor to the target idle state without requiring the processor to proceed linearly between idle states.
2. The method as recited in
(a) the current idle state of the processor; and
(b) the most recent time when a calculation to identify the target idle state of the processor occurred.
3. The method as recited in
4. The method as recited in
wherein determining whether the processor is idle includes identifying whether a thread managed by an operating system exists with program code that is ready to be executed.
5. The method as recited in
6. The method as recited in
(a) a metric of the idleness of the processor; and
(b) a metric that quantifies activities scheduled to be performed that do not require direct involvement by the processor.
7. The method as recited in
(a) the latency overhead of putting a processor to sleep when the processor is in a specific idle state; and
(b) the power savings achieved when the processor is in a specific idle state.
8. The method as recited in
(a) processing ACPI compliant information in the BIOS of the computer; and
(b) causing the processed data to be stored in a data store that is accessible to the software system that manages the processor's power consumption.
9. The method as recited in
(a) allowing a set of configurable policies to be defined; and
(b) applying the configurable policies to identify the target idle state for the processor.
10. The method as recited in
wherein a factor used to calculate target idle state may be assigned a greater significance than other factors.
11. The method as recited in
12. A computer-implemented method for using a metric that quantifies the processing scheduled to be performed on a computer to identify a target idle state for a processor, the method comprising:
(a) recording events that are scheduled to be performed on the computer in the future;
(b) calculating a metric that quantifies the processing scheduled to the performed on the computer in the future;
(c) using the metric to identify a target idle state for the processor; and
(d) changing the idle state of the processor to the target idle state.
13. The method as recited in
14. The method as recited in
wherein a first factor used to calculate the target idle state may be assigned a greater significance than another factor.
15. The method as recited in
16. In a computer that includes a processor, a software system for managing the power consumption of the processor, the software system comprising:
(a) a data store where data that is relevant in calculating a target idle state for a processor is collected from a plurality of data sources;
(b) a target state routine operative to:
(i) retrieve data from the data store;
(ii) calculate a target idle state that minimizes the power consumed by the processor; and
(c) a processor driver operative to cause the processor to transition from a current state to the target state calculated by the target state routine.
17. The software system as recited in
18. The software system as recited in
19. The software system as recited in
20. The software system as recited in
Market requirements, environmental needs, business costs, and limited battery life dictate that computing devices use as little energy as possible while still providing robust computing services. The energy consumed by a computing device can be more efficiently managed by providing enough computational power for each service as needed instead of providing maximum computational power at all times. Computing devices such as laptop, desktop, and mainframe computers, personal digital assistants (PDAs), cellular telephones, etc., provide services by causing program instructions to be executed by electronic circuitry. The electronic circuitry that executes computer program instructions in a computing device is often contained in a single integrated circuit referred to as a “core.” A core is contained in a single physical package often referred to as a “microprocessor” or simply a “processor.” Moreover, multiple interacting cores may be contained in a single processor.
Most computing devices execute a computer program commonly referred to as an operating system that guides the operation of the computing device and provides services to other programs. More specifically, an operating system controls the allocation and usage of hardware resources such as memory, computing resources, mass memory storage, peripheral devices, etc. The computer instructions for initializing and operating the computing device are typically contained in a component of the operating system often referred to as the “kernel.” Shortly after a computing device is started, the kernel begins executing. Since a kernel has direct control of the hardware and access to data that describes the state of a computing device, a kernel may be used to regulate computing power and otherwise control energy consumption.
In some existing systems, software components in a kernel reduce the consumption of power used by a processor through the use of processor idle sleep states (hereinafter sometimes referred to as “C-states”). For example, some computers adhere to a specification commonly known as Advanced Configuration and Power Interface (“ACPI”). In this example, when a computer is put into in any of the available C-states, instructions are not executed. However, a processor will regularly “wake up” or exit the idle sleep state and transition back to the working state automatically when any user or platform activity occurs so that instructions may be executed. Then, the processor will be put back to “sleep” to save power. Since the processor is able to enter and exit idle sleep states very quickly, the user experience of interacting with programs is not affected when the processor is put into an idle sleep state.
When a predetermined threshold amount of idleness is identified, a processor may transition from the working state (“C0”) in which the processor consumes the most amount of power into an initial idle C-state (“C1”). Traditionally, when a processor is in an idle C-state (e.g., “C1”) and an additional predetermined threshold amount of idleness is identified over a given time period, the processor transitions from the current C-state (e.g., “C1”) into the next higher or deeper C-state (e.g., “C2”). On one hand, each successively higher C-State provides greater levels of power savings. On the other hand, a higher C-state is associated with a greater latency overhead required to exit the idle sleep state. Stated differently, using a higher C-state than is appropriate based on the idleness of the processor could adversely affect system responsiveness and the user experience. As a result, existing systems use a linear promotion and demotion scheme for selecting a C-state in which a predetermined amount of time is accrued in a C-state before a promotion or demotion to the next appropriate C-state occurs. However, a linear promotion/demotion scheme for transitioning between C-states does not take advantage of recent advances in hardware technology. Instead, additional power savings may be achieved by using a non-linear scheme for setting an appropriate processor state.
Generally described, embodiments of the present invention are directed at identifying an idle sleep state for a processor that minimizes power consumption. In accordance with one embodiment, a method for identifying a target idle state that does not require a linear progression into an intermediate idle state is provided. More specifically, in this embodiment, the method includes collecting data from a plurality of data sources that describe activities occurring on the computer and/or attributes of the hardware platform. Then, using the collected data, a target idle state for the processor is identified. Finally, if the current idle state of the processor is different than the target idle state, the method causes the idle state of the processor to change to the target idle state without causing the processor to enter any intermediate idle states.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identify key features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same become better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
The present invention may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally described, program modules include routines, programs, applications, widgets, objects, components, data structures, and the like that perform particular tasks or implement particular abstract data types. Moreover, the present invention may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located on local and/or remote computer storage media.
While the present invention will primarily be described in the context of using a specific software interface known as Advanced Configuration and Power Interface (“ACPI”) to collect data and minimize the amount of power consumed by a processor, those skilled in the relevant art and others will recognize that the present invention is also applicable in other contexts. In any event, the following description first provides a general overview of a computer system in which aspects of the present invention may be implemented. Then a method for performing aspects of the invention is described. The illustrative examples described herein are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Similarly, any steps described herein may be interchangeable with other steps or combinations of steps in order to achieve the same result.
Now with reference to
In the computer 100 illustrated in
In this embodiment, the firmware 106 comprises software components stored in non-volatile memory such as, but not limited to, read-only memory (ROM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Moreover, the firmware 106 includes a Basic Input/Output System (BIOS) 116 with computer instructions that enable the computer 100 to perform functions for initializing the computer's 100 hardware when power is first applied after which the BIOS 116 boots the operating system 102. Typically, when a computer is powered up, the computer's BIOS conducts a hardware check, called a Power-On Self Test (POST), to determine whether the support hardware is present and working correctly. Then instructions in the BIOS direct control to a boot loader that loads the operating system into a computer's volatile memory, e.g., a bank of random access memory (RAM) memory devices. The BIOS is typically located in non-volatile memory to ensure that the BIOS is always available and will not be damaged by failures affecting volatile memory or mass data storage. A BIOS also provides low-level input/output control. For example, in a personal computer, the BIOS contains the computer instructions required to control the keyboard, display screen, disk drives, serial communications, and a plurality of miscellaneous functions. A typical implementation of a BIOS is a PC-AT BIOS, i.e., the BIOS used in a variety of computers that run a Windows® operating system. Other implementations of a BIOS include, but are not limited to, the Open Firmware (OFW) and Open Boot PROM (OBP).
The operating system 102 of the computer 100 often includes a power manager 118 that typically resides in an operating system kernel 120, for controlling the levels of certain processor characteristics, such as but not limited to, voltage and frequency. Generally described, one aspect the power manager 118 provides logic for the power management functions of the computer 100. Moreover, the power manager may communicate with a processor driver 122 that is used to abstract the differences in specific controls between various processors, and to execute state transitions that cause changes in a processor's voltage and/or frequency levels. Also residing in the operating system kernel 120, the processor driver 122 directly interfaces with hardware on the computer 100 to implement logic contained in the power manager 118. For example, when the computer 100 boots, the processor driver 122 reads the data included in a BIOS 116 to discover the power management capabilities of a processor and passes this information to the power manager 118. In accordance with one embodiment, data passed to the power manager 118 includes a set of ACPI compliant data obtained from the BIOS 116 that describes the power management capabilities of a processor component 110. Those skilled in the art and others will recognize that even though the exemplary embodiments described herein uses ACPI compliant data stored in the BIOS 116 to identify the attributes of computer hardware, in other embodiments, the data may adhere to a different standard or not be based on a standard without departing from the scope of the claimed subject matter.
As illustrated in
The data store 150 illustrated in
As further illustrated in
As further illustrated in
Now with reference to
As illustrated in
At block 202, the target state routine 154 obtains a data set that is used to identify an optimized or target state for a processor. In the embodiment depicted in
Now with reference to
As mentioned above, the “GENERAL DATA” category 302 includes five rows entitled “TIME OF PREVIOUS CALCULATION” 306, “POLICIES” 308, “METRIC OF PAST PROCESSOR IDLENESS” 310, “METRIC OF FUTURE PROCESSOR IDLENESS” 312, and “METRIC OF NON-PROCESSOR ACTIVITY” 314. Simply stated, the row 306 contains a variable that measures the time since the most recent calculation to identify a target state for a processor. As described in further detail below, the variable contained in row 306 may be used to identify a target state for a processor.
As further depicted in
As further illustrated in
As further illustrated in
As further illustrated in
In the embodiment of the present invention illustrated in
Those skilled in the art and others will recognize that the data set 300 depicted in
Returning now to
It should be well understood that the calculation performed at block 204 does not require a processor to stay in a particular state in order to be promoted or demoted into the next state. Stated differently, the linear promotion and demotion scheme performed by existing systems that dictates a processor remain in an idle state for a specified period of time is not used by the present invention. Instead, the calculation performed at block 204 may identify a target state that is one or more states away from the current state. Identifying a target state without using a linear promotion/demotion scheme has several advantages. First, advances in hardware technology have continued to reduce the exit latency associated with waking a processor from “sleep.” Thus, additional power savings over existing systems may be achieved by identifying the most appropriate state for a processor given the activity that has or will be performed on a computer. Second, those skilled in the art and others will recognize that processing performed by a processor tends to be “bursty.” Stated differently, over time a processor tends to alternate between periods of either being highly utilized in executing program code or underutilized (e.g., idle). Thus, identifying a target state that does not require linear promotion/demotion better adheres to how processors perform in practice. For example, when a “burst” of processor activity occurs, aspects of the present invention may cause a processor to proceed from a high idle state into the working state without having to progress through any intermediate states. Again, by identifying an appropriate target state when bursts of processor activity or idleness occur, additional power savings are achieved as the processor is not required to proceed through a linear progression of states that are not appropriate given the activity that has or is scheduled to occur on a computer.
It should also be well understood that some factors described above that are used to calculate a target state at block 204 may, and typically will, be given greater significance than other factors. For example, one aspect of the present invention is the use of a metric that measures the future idleness of a processor in calculating a target state for a processor. In this regard and as described previously with reference to
The configurable aspects of the calculation performed at block 204 may be used to account for guarantees provided by an operating system. For example, some “real-time” operating systems in which the present invention may be implemented guarantee that services are satisfied within a specified period of time. In this regard, an operating system may guarantee that a certain amount of incoming network traffic is processed within a specified period of time. In this instance, the “METRIC OF NON-PROCESSOR ACTIVITY” 314 obtained at block 202 that accounts for DMA activity may be given greater significance than other factors described above or may be the only factor used to identify a target state at block 204. These examples illustrate that the way in which the calculation is performed at 204 is highly configurable depending on the needs of an operating system, user, computer manufacturers, etc.
As illustrated in
At block 208, the target state routine 154 updates a data store (e.g., the data store 150) with data that is used by a software system to regulate power consumption of a processor. For example, as mentioned previously, data in the data store 150 may be retrieved to determine when a target state was most recently calculated. At block 208, the routine 154 updates data in the data store 150 that includes this type of information so that power consumption may be accurately regulated in the future.
At block 210, the target state routine 154 causes the state of the processor to be changed from its current state to the target state calculated at block 204. If block 210 is reached the current state of the processor is different than the target state calculated at block 204. In this instance, the target state routine 154 causes the processor to transition into the target state. As described previously, one aspect of the present invention is a processor driver (e.g., the processor driver 122) that abstracts the differences between various processors available in the marketplace and is used to execute transitions in processor states. Thus, in accordance with one embodiment of the present invention, the target state routine 154 causes a state transition to occur, at block 210, by issuing a call to a processor driver. Then, the target state routine 154 proceeds to block 212 where it terminates.
While illustrative embodiments have been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.