US 20070253245 A1
One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.
1. A diode-addressable current-induced magnetization switching (CIMS) memory element comprising:
a magnetic tunnel junction (MTJ); and
a thin-film diode formed on top of the MTJ for addressing the MTJ.
2. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
3. A diode-addressable current-induced magnetization switching (CIMS) memory element, as recited in
4. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
5. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
6. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
7. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
8. A diode-addressable current-induced magnetization switching (CIMS) memory element comprising:
a thin-film diode formed on top of the MTJ for addressing the MTJ; and
a magnetic tunnel junction (MTJ) formed on top of the diode.
9. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
10. A diode-addressable current-induced magnetization switching (CIMS) memory element, as recited in
11. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
12. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
13. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
14. A diode-addressable current-induced magnetization switching (CIMS) memory element, a recited in
15. A method of manufacturing A diode-addressable current-induced magnetization switching (CIMS) memory element comprising:
Forming a pinning layer;
forming a fixed layer on top of the pinning layer;
forming a tunnel layer on top of the pinning layer;
forming a free layer on top of the tunnel layer to form a magnetic tunnel junction (MTJ);
forming a conductive seeding silicon layer on top of the free layer; and
forming a thin-film diode on top of the MTJ.
This application claims priority to a previously-filed U.S. Provisional Application No. 60/795,755, filed on Apr. 26, 2006 and entitled “High capacity low cost multi-stacked cross-line magnetic memory” and is a continuation-in-part of U.S. patent application Ser. No. 11/674,124 entitled “Non-uniform Switching Based Non-Volatile Magnetic Base Memory”, filed on Feb. 12, 2007 and a continuation-in-part of U.S. patent application Ser. No. 11/678,515 entitled “A High Capacity Low Cost Multi-State Magnetic Memory”, filed on Feb. 23, 2007, and a continuation-in-part of U.S. patent application Ser. No. 11/739,648 entitled “Non-Volatile Magnetic Memory With Low Switching Current And High Thermal Stability”, filed on Apr. 24, 2007 the disclosures of which are incorporated herein by reference, as though set forth in full.
1. Field of the Invention
The present invention relates generally to non-volatile magnetic memory and particularly to non-volatile magnetic memory using diode for addressing thereof.
2. Description of the Prior Art
Computers conventionally use rotating magnetic media, such as hard disk drives (HDDs), for data storage. Though widely used and commonly accepted, such media suffer from a variety of deficiencies, such as access latency, higher power dissipation, large physical size and inability to withstand any physical shock. Thus, there is a need for a new type of storage device devoid of such drawbacks.
Other dominant storage devices are dynamic random access memory (DRAM) and static RAM (SRAM) which are volatile and very costly but have fast random read/write access time. Solid state storage, such as solid-state-nonvolatile-memory (SSNVM) devices having memory structures made of NOR/NAND-based Flash memory, providing fast access time, increased input/output (IOP) speed, decreased power dissipation and physical size and increased reliability but at a higher cost which tends to be generally multiple times higher than hard disk drives (HDDs).
Although NAND-based flash memory is more costly than HDD's, it has replaced magnetic hard drives in many applications such as digital cameras, MP3-players, cell phones, and hand held multimedia devices due, at least in part, to its characteristic of being able to retain data even when power is disconnected. However, as memory dimension requirements are dictating decreased sizes, scalability is becoming an issue because the designs of NAND-based Flash memory and DRAM memory are becoming difficult to scale with smaller dimensions. For example, NAND-based flash memory has issues related to capacitive coupling, few electrons/bit, poor error-rate performance and reduced reliability due to decreased read-write endurance. Read-write endurance refers to the number of reading, writing and erase cycles before the memory starts to degrade in performance due primarily to the high voltages required in the program, erase cycles.
It is believed that NAND flash would be extremely difficult to scale below 45 nanometers (nm). Likewise, DRAM has issues related to scaling of the trench capacitors leading to very complex designs which are becoming increasingly difficult to manufacture, leading to higher cost.
Currently, applications commonly employ combinations of EEPROM/NOR, NAND, HDD, and DRAM memory in a system design. Design of different memory technology in a product adds to design complexity, time to market and increased costs. For example, in hand-held multi-media applications incorporating various memory technologies, such as NAND Flash, DRAM and EEPROM/NOR flash memory, complexity of design is increased as are manufacturing costs and time to market. Another disadvantage is the increase in size of a device that incorporates all of these types of memories therein.
There has been an extensive effort in development of alternative technologies, such as Ovanic Ram (or phase-change memory), Ferro-electric Ram (FeRAM), Magnetic Ram (MRAM), Nanochip, and others to replace memories used in current designs such as DRAM, SRAM, EEPROM/NOR flash, NAND flash and HDD in one form or another. Although these various memory/storage technologies have created many challenges, there have been advances made in this field in recent years. MRAM seems to lead the way in terms of its progress in the past few years to replace all types of memories in the system as a universal memory solution.
One of the problems with prior art memory structures including MRAMs is their cell or memory size being too large therefore not lending itself well to scalability. A typical design of such MRAMs uses one or more transistors for one memory cells that lead to nT-1 mem cell type design where n=1-6. This makes the cell size too large leading to issues of scalability and cost. Recently, current-induced magnetization switching (CIMS) is being explored as an alternative memory solution, and allegedly introduces a better way of building higher capacity MRAM type memory. But memories based on MRAM tend to have larger cell size (16-24 F2, where F is the minimum feature based on the lithography technology).
Therefore, in light of the foregoing, what is needed is a non-volatile magnetic memory element utilizing magnetic diodes for addressing memory cells, the memory cells capable of being stacked on top of each other (in the direction of the z-axis) enabling higher capacity, lower cost designs and scalability (independent of lithography limits).
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses a method and a corresponding structure for a magnetic storage memory device that is based on current-induced-magnetization-switching having reduced switching current in the magnetic memory and high memory capacity.
Briefly, an embodiment of the present invention includes a stackable diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.
These and other objects and advantages of the present invention will no doubt become apparent to those skilled in the art after having read the following detailed description of the preferred embodiments illustrated in the several figures of the drawing.
Table 1 shows the effect of number of stacks on the memory cell size in F2
In the following description of the embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration of the specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized because structural changes may be made without departing from the scope of the present invention. It should be noted that the figures discussed herein are not drawn to scale and thicknesses of lines are not indicative of actual sizes.
In an embodiment of the present invention, a diode-addressable current-induced magnetization switching (CIMS) memory element is disclosed. In one embodiment of the present invention, the memory element includes a magnetic tunnel junction (MTJ) on top of which is formed a diode for storing digital information. The memory element is stackable into arrays of memory elements in each stack and each stack separated by deposited dielectric and CMPed surface. In an embodiment of the present invention, a magnetic shielding layer magnetically isolates one stack of memory elements from other stacks.
Referring now to
It should be noted that the memory element 10, in various embodiments, may have a structure such as that disclosed in U.S. patent application Ser. No. 11/674,124 entitled “Non-uniform Switching Based Non-Volatile Magnetic Base Memory”, filed on Feb. 12, 2007 or U.S. patent application Ser. No. 11/678,515 entitled “A High Capacity Low Cost Multi-State Magnetic Memory”, filed on Feb. 23, 2007, or U.S. patent application Ser. No. 11/739,648 entitled “Non-volatile Magnetic Memory With Low Switching Current And High Thermal Stability”, filed on Apr. 24, 2007, the disclosures of which are incorporated herein by reference, as though set forth in full.
The memory element of
In one embodiment, the layer 24 may consist of a number of layers including an anti-ferromagnetic layer consisting of PtMn or IrMn. The layer 24 is used to create pinning for the fixed layer 26, which is the reason it is referred to as a pinning layer. The layer 26 is typically made of CoFeBPtX where the ratios of Fe, Co, Pt and B are varied to make sure that the resulting alloy has an substantially amorphous structure. Layer 28 is made of an oxide typically MgOx where x<=1. This may have a very thin layer of Mg, typically less than 5 Å, to get the proper crystalline structure of the MgOx layer which is required to get good tunneling property. Layer-4 can have a similar material properties and structure as layer 26 and is made of CoFeBPtX alloy. Layer 26 is the “fixed” layer, in that the magnetic orientation is locked in a predetermined orientation based on the induced magnetic anisotropy and the magnetic annealing of the anti-ferromagnetic layer. Layer-4 is the “free-layer” whose orientation would change based on the input-current. The two states of fixed versus free-layer being, parallel and anti-parallel, inducing different resistances, leading to “0” and “1” states.
The isolation layer 14 is the base isolation layer on which the diode 40 is deposited. In an exemplary embodiment, the diode 40 has the structure of FM (ferro-magnetic)/oxide/N—Si where, the layer 16 is the n-doped Si, the layer 18 is the oxide layer selected from any of: MgOx, AlOx, or ZrOx, and the layer 22 is a ferromagnetic layer comprising of Co—Fe—B—Pt and acts as spin-injection layer. Although the embodiment shown in
The MTJ 12 acts like a resistor therefore forming a resistor in series with the diode 40. The diode 40 is essentially used to address the memory element 10 for programming, erasing and/or reading operations. In operation, current is applied at memory element 10 in the direction that is favorable to the diode. The thin film diode may have different characteristics based on the structure of the memory element 10. In one embodiment of the present invention, the current flowing from the bottom up in
The starting state of this magnetic memory is “parallel” state for the magnetic moments of layers 26 and 30. This is the “low resistance”. When a current of say 300 micro-amp is applied from the bottom-up for memory element having a size of 100 nm*150 nm, the majority spins travel across the barrier while the minority “opposite” spin is reflected back into the free-layer 30 applying enough torque to the magnetic moments to flip in the opposite direction, as shown by the opposite arrows in
The diode 40 of each of the memory elements 10 of the stack of elements 41 is shown formed on top of the word line 48 and the diode 40 of each of the memory elements 10 of the stack of elements 43 and is also shown to be formed on the word line 48. The word lines for each stack of elements 41 and 43 are different, as are the bit lines 46 shown formed on top of the memory elements 10 for each element.
A magnetic shield 57 encompasses the top and sides of two of the bit lines and memory elements and program line, as shown in
In the embodiment of
The magnetic shielding layer, such as the layer 57 in
One key aspect of the memory structures of the various embodiments herein is that the electrical current flows perpendicular to the memory-element 10, and provides the necessary torque to the magnetic-spins to cause current-induced magnetization switching, CIMS, leading to parallel and anti-parallel magnetic states of free versus pinned fixed layers. The memory architecture utilizes orthogonal word line and bit line architecture, as shown in
The cell-size of memory element 10, in an exemplary embodiment is: 4 F2/N, where N corresponds to the number of memory layers which are stacked on top. As shown in Table 1, as the number of stacks increase, the cell size decreases proportionately.
In accordance with Table 1, for N=8, the cell size is 0.5 F2, this is same as that of the current Hard-disk drives. Hard-disk drives are highest density storage device and thereby lowest cost. It is believed that in 3-5 years the hard-disk drive industry will employ patterned media to achieve higher areal density. The patterned media has a cell size of F2. Thus the N=8 and N=10 based memory per this invention is the smallest cell-size memory-storage device possible, leading to the lowest cost storage-memory.
Typically and when not selecting any memory elements, the word lines are at a 0 V state. When a word line is driven to a positive (+) voltage, such as −1 volts (V), the word line selects the row of bit lines that it crosses and if a bit line is at a ground voltage, the memory element that is positioned at the crossing of the foregoing word and bit lines, is selected and is programmed. For example, in
While the energy source can be a heating source, such as a rapid thermal annealing process, in one embodiment of the present invention, during manufacturing the magnetic memory elements of the MTJ should not be affected by the processing of the diode of the memory element. In an exemplary technique for achieving the latter, three techniques are employed to ensure that the magnetic structure of the MTJ 12 is not impacted during the deposition of the thin-film diode 40 namely, (i) and to this end, a nucleating layer is used that is of less than 20 nano meters (nm) in thickness of one of more metals or their alloys chosen from the following material: Co, cobalt, Ni, nickel, Pt, platinum; (ii) deposition of these film using a PVD (physical deposition process) such as using rf- or dc-magnetron sputtering under typically a low argon pressure of less than 10 mili-torr and having less than 50 percent of H2 in the gas; (iii) having a pulsed laser source for heating such as using a Nd-YAG laser of peak power of less than 2 kw at 20 Khz. Laser annealing is typically carried out in the vacuum following the deposition of the silicon seeding layer 14, such as shown in
Additional stacks of such memory can be deposited on top of the smooth surface 118, as mentioned with respect to earlier embodiments. The memory elements 10 are programmed by passing current from the bottom thereof. The memory element, in the initial state, has both the layer 26 and the layer 30 having magnetization in the same direction as set by the magnetic annealing process. This is the “low-resistance” state. When a higher current, for example, 300 micro-amps, for a memory cell of size 90 nm×140 nm, is applied from the bottom of the memory element 10 for writing or programming (as compared to the read current of 50 micro-amps) spin-polarized electron having anti-parallel spins from the free layer are reflected back into the free layer 30 and switch the magnetic moment of the free layer into the anti-parallel direction as shown by arrow in
Each of two memory elements above which is formed the erase line 218 has a magnetic-shield layer 212 or a formed on top and around the erase line 218 and the memory elements 10 and above the magnetic-shield layers 212 and 214 are smoothed or flattened using a CMP process so that an adjacent stack may be formed thereontop.
Next, at step 306, a metal-3 layer is deposited on top of the deposited SiO2 layer forming a field erase or erase line, such as the lines 218 or 54 or others. Next, at step 308, a magnetic shielding layer is deposited on top of the deposited program line. The magnetic shielding layer is similar to the shielding layers 116, 136, 138 or the like. Also, at step 308, a SiO2 layer is deposited on top of the deposited magnetic shielding layer and CMP is performed. After the completion of the step 308, the first stack of memory elements is formed. Namely, steps 304-308 comprise the steps performed for manufacturing the first stack, such as the stack 202. Next, a second stack is formed on top of the first stack by performing the steps 310-314.
At step 310, a metal-4 layer is deposited and a second MTJ and diode comprising a second memory element is deposited on top of the metal-4 layer and an etching process is performed and a metal-5 layer is deposited.
Next, at step 312, a metal-6 layer is deposited on top of the metal-5 layer to form a second program line and thereafter, at step 314, a second magnetic shielding layer is deposited on top of the deposited metal-6 layer and a second SiO2 layer is deposited and CMP is performed and the second stack of memory elements is formed. Next, at step 316, if additional stacks are needed, they are formed, sequentially, on top do the second stack in accordance with the steps discussed relative to the formation of the first and second stacks. At step 318 and after the formation of all requisite stacks, an encapsulation process is performed to further shield the stack of elements.
The stack of memory 550 is manufactured using overall temperatures of less than 400 degrees Celsius while the CMOS circuitry 552 is manufactured using temperatures greater than 900 to 950 degrees Celsius. The lower temperature for manufacturing the stack of memory is important in that it allows the amorphous state of the diode to transform to a crystalline state, as noted with respect to
It should be noted that the objects of the drawings or figures discussed and presented herein are not necessarily drawn to scale. Additionally, the relative locations of the MTJ as well as the layers of MTJs such as the fixed and the free-layers can be adjusted based on the type of the diode and its characteristic in the forward and reverse direction.
Although the present invention has been described in terms of specific embodiments, it is anticipated that alterations and modifications thereof will no doubt become apparent to those skilled in the art. It is therefore intended that the following claims be interpreted as covering all such alterations and modification as fall within the true spirit and scope of the invention.