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Publication numberUS20070254439 A1
Publication typeApplication
Application numberUS 11/772,823
Publication dateNov 1, 2007
Filing dateJul 3, 2007
Priority dateMar 22, 2005
Also published asUS7545023, US20060214236
Publication number11772823, 772823, US 2007/0254439 A1, US 2007/254439 A1, US 20070254439 A1, US 20070254439A1, US 2007254439 A1, US 2007254439A1, US-A1-20070254439, US-A1-2007254439, US2007/0254439A1, US2007/254439A1, US20070254439 A1, US20070254439A1, US2007254439 A1, US2007254439A1
InventorsChin-Cheng Chien
Original AssigneeChin-Cheng Chien
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for making semiconductor transistor
US 20070254439 A1
Abstract
A semiconductor transistor includes a substrate, a gate insulating layer positioned on the surface of the substrate, a gate positioned on the gate insulating layer, a channel region positioned in the substrate corresponding to the gate, and a source region and a drain region respectively positioned alongside the channel region. The source region and the drain region are mainly made of a first material and a second material, wherein the first material and the second material have a same lattice structure and different spacing. The source region and the drain region each include a main region in which a percentage of the second material is constant, and a peripheral region in which a percentage of the second material is graded.
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Claims(12)
1. A method for forming a semiconductor transistor comprising:
providing a substrate, the substrate comprising a gate insulating layer positioned on the surface of the substrate, a gate positioned on the gate insulating layer, and a channel region positioned in the substrate corresponding to the gate;
forming two recesses in the substrate alongside the channel region;
forming a first material and a second material in the recesses to respectively form two peripheral regions, the first material and the second material having a same lattice structure and different spacing, and a percentage of the second material in the peripheral regions being graded; and
forming the first material and the second material in the recesses to respectively form two main regions above the peripheral regions, and a percentage of the second material in the main regions being constant.
2. The method of claim 1, wherein the percentage of the second material in each peripheral region decreases from an interface between the main region and the peripheral region to an interface between the peripheral region and the substrate.
3. The method of claim 2, wherein the percentage of the second material in each peripheral region decreases from 30% to 0%.
4. The method of claim 3, wherein the percentage of the second material in each main region is approximately 30%.
5. The method of claim 1, wherein the first material is monocrystalline silicon.
6. The method of claim 1, wherein the second material is germanium.
7. The method of claim 6, wherein the semiconductor transistor is P type.
8. The method of claim 1, wherein the second material is carbon.
9. The method of claim 8, wherein the semiconductor transistor is N type.
10. The method of claim 1, wherein the first material and the second material are epitaxially grown in the recesses.
11. The method of claim 1, further comprising forming two lightly doped regions positioned in the substrate respectively alongside the channel region prior to forming the recesses.
12. The method of claim 1, further comprising performing an implantation process to form a source region and a drain region subsequent to forming the main regions.
Description
CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/907,125 filed Mar. 22, 2005.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor transistor and method for making the same, and more particularly, to a semiconductor transistor with strained source/drain regions that have a reduced interface mismatch defect, and method for making the same.

2. Description of the Prior Art

The performance of semiconductor transistors has increased year after year with the diminution of critical dimensions and the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit. Therefore, how to improve the carrier mobility so as to increase the speed performance of semiconductor transistors has become a major topic for study in the semiconductor field. Attempts have been made to use strained source/drain regions made of silicon germanium, for instance. In this type of semiconductor transistor, a compressive strain occurs in the channel region due to the silicon germanium which has a larger spacing than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional PMOS transistor. As shown in FIG. 1, the conventional PMOS transistor includes a substrate 10 made of monocrystalline silicon, two field isolation regions 12 positioned in the substrate 10, a gate insulating layer 14 positioned on the surface of the substrate 10, a gate 16 positioned on the gate insulating layer 14, and a channel region 18 corresponding to the gate 16 positioned in the substrate 10. The PMOS transistor further includes two lightly doped regions 20 respectively positioned alongside the channel region 18, and a source region 22 and a drain region 24 respectively positioned on opposite sides of the lightly doped regions 20. The source region 22 and the drain region 24 are P type, and made of silicon germanium in which the percentage of germanium is held constant, for example at 30%.

The conventional PMOS transistor suffers some disadvantages. First, the critical thickness of the source region and the drain region is limited to prevent the silicon germanium from peeling. In addition, interface mismatch defects tend to occur between the silicon germanium and the substrate (monocrystalline silicon) because the percentage of germanium between the source region 22 and the drain region 24 (30%), and the substrate 10 (close to 0%) is too large.

SUMMARY OF THE INVENTION

It is therefore a primary object of the claimed invention to provide a semiconductor transistor and method for making the same to overcome the aforementioned problems.

According to the claimed invention, a semiconductor transistor is disclosed. The semiconductor transistor includes a substrate, a gate insulating layer positioned on the surface of the substrate, a gate positioned on the gate insulating layer, a channel region positioned in the substrate corresponding to the gate, and a source region and a drain region respectively positioned alongside the channel region. The source region and the drain region are mainly made of a first material and a second material, wherein the first material and the second material have a same lattice structure and different spacing. The source region and the drain region each include a main region in which a percentage of the second material is constant, and a peripheral region in which a percentage of the second material is graded.

The source region and the drain region each include a main region in which the percentage of the second material (germanium or carbon) is held constant and a peripheral region in which the percentage of the second material is graded. Accordingly, the interface mismatch defect between the source region (also the drain region) and the substrate is reduced. Therefore, the reliability and performance of the semiconductor transistor of the present invention is improved.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a conventional PMOS transistor.

FIG. 2 is a schematic diagram of a semiconductor transistor according to a preferred embodiment of the present invention.

FIG. 3 through FIG. 8 are schematic diagrams illustrating a method for forming a semiconductor transistor according to another embodiment of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2. FIG. 2 is a schematic diagram of a semiconductor transistor according to a preferred embodiment of the present invention. As shown in FIG. 2, the semiconductor transistor includes a substrate 50 made of monocrystalline silicon, a plurality of field isolation regions 52, such as shallow trench insulations (STI), formed in the substrate 50, a gate insulating layer 54 positioned on the surface of the substrate 50, a gate 56 positioned on the gate insulating layer 54, and a channel region 58 positioned in the substrate 50. The semiconductor transistor further includes spacers, including offset spacers 60 and main spacers 64, alongside the gate 56, two lightly doped regions 62 positioned on two opposite sides of the channel region 58, a source region 72 and a drain region 74 positioned on two opposite sides of the lightly doped regions 62.

Each of the source region 72 and the drain region 74 includes a peripheral region 68 and a main region 70 positioned above the peripheral region 68. In this embodiment, the semiconductor transistor is a PMOS transistor, and the source region 72 and the drain region 74 are mainly made of silicon germanium that is formed epitaxially. Germanium has a smaller spacing than monocrystalline silicon, and thus the channel region 58 is compressed. To prevent the mismatch defects in the interface between the source region 72 (also the drain region 74) and the substrate 50, the percentage of germanium in the peripheral region 68 is graded. Specifically, the percentage of germanium in the peripheral region 68 decreases from the interface between the main region 70 and the peripheral region 68 to the interface between the peripheral region 68 and the substrate 50. On the other hand, the percentage of germanium in the main region 70 is held constant. By virtue of the graded peripheral region 68 positioned between the substrate 50 and the main region 70, the interface mismatch defect is reduced. In this embodiment, the percentage of germanium in the main region 70 is approximately 30%, and that in the peripheral region 68 decreases from 30% to 0%.

The composition of the main region 70 and the peripheral region 68 is not limited, and can be optimized. In addition, if the semiconductor transistor is N type, then germanium is replaced by other materials, such as carbon that has a larger spacing than monocrystalline silicon. Accordingly, a tensile stress acts on the channel region 58.

Please refer to FIG. 3 through FIG. 8. FIG. 3 through FIG. 8 are schematic diagrams illustrating a method for forming a semiconductor transistor according to another embodiment of the present invention. As shown in FIG. 3, a substrate 50 made of monocrystalline silicon is provided. The substrate 50 includes a plurality of field isolation regions 52, such as shallow trench insulations (STI), formed in the substrate 50, a gate insulating layer 54 positioned on the surface of the substrate 50, a gate 56 positioned on the gate insulating layer 54, and a channel region 58 positioned in the substrate 50.

As shown in FIG. 4, two offset spacers 60 are formed alongside the gate 56 and the gate insulating layer 54. Subsequently, an implantation process and an annealing process are consecutively performed to form two lightly doped regions 62 in the substrate on two opposite sides of the channel region 58. In this embodiment, the semiconductor transistor is P type, and thus a P type dopant, such as boron, is used.

As shown in FIG. 5, two main spacers 64 are formed alongside the offset spacers 60. Then, an etching process is performed to remove a portion of the substrate 50 alongside the main spacers 64 to respectively form two recesses 66 on two opposite sides of the gate 56. As shown in FIG. 6, silicon germanium is epitaxially grown on the inner wall of the recesses 66 to form two peripheral regions 68. The epitaxially-formed silicon germanium is composed of monocrystalline silicon and germanium, and the percentage of germanium in each peripheral region 68 is graded. In this embodiment, the percentage of germanium increases from 0% to 30% from the inner wall of the recess 66.

As shown in FIG. 7, silicon germanium is again epitaxially grown in the recesses 66 to respectively form two main regions 70 above the peripheral region 68. In each main region 70, the percentage of germanium is maintained constant. In this embodiment, the percentage of germanium is held at 30%. It is noted that the peripheral regions 68 and the main regions 70 are formed in two steps in this embodiment. However, the peripheral regions 68 and the main regions 70 can also be formed in an in-situ manner. Subsequently, an implantation process using a P type dopant, such as boron, is performed upon the main regions 70 and the peripheral regions 68.

As shown in FIG. 8, at least a thermal process, such as a rapid thermal process (RTP), a laser annealing process, or a flash process, is performed to activate the main regions 70 and the peripheral regions 68. If a laser annealing process or a flash annealing process is selected, the process temperature is between about 1200 to 1400 degrees Celsius. Following that, self-aligned salicide (not shown), for instance cobalt salicide or nickel salicide, can be formed on the surface of the main regions 70. Accordingly, a source region 72 and a drain region 74 are formed.

In the above embodiment, a PMOS transistor is exemplarily illustrated. If an NMOS transistor is to be formed, germanium is replaced by carbon, and N type dopants are used in the implantation processes for forming the lightly doped regions 62 and for forming the source region 72 and the drain region 74.

In comparison with the conventional semiconductor transistor, the source region and the drain region each include a main region in which the percentage of germanium (or carbon) is held constant and a peripheral region in which the percentage of germanium (or carbon) is graded. Accordingly, the interface mismatch defect between the source region (also the drain region) and the substrate is reduced. Therefore, the reliability and performance of the semiconductor transistor of the present invention is improved.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7479466 *Jul 14, 2006Jan 20, 2009Taiwan Semiconductor Manufacturing Co., Ltd.Method of heating semiconductor wafer to improve wafer flatness
Classifications
U.S. Classification438/285, 257/E21.409, 257/E29.085, 257/E21.431
International ClassificationH01L21/336
Cooperative ClassificationH01L29/6659, H01L29/165, H01L29/66636, H01L29/7848, H01L29/6656
European ClassificationH01L29/66M6T6F11E, H01L29/78R6, H01L29/165
Legal Events
DateCodeEventDescription
Jul 3, 2007ASAssignment
Owner name: UNITED MICROELECTRONICS CORP., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHIEN, CHIN-CHENG;REEL/FRAME:019509/0283
Effective date: 20050321