|Publication number||US20070257315 A1|
|Application number||US 11/417,846|
|Publication date||Nov 8, 2007|
|Filing date||May 4, 2006|
|Priority date||May 4, 2006|
|Also published as||CN101438399A, CN101438399B, US7968459, US20080258220, WO2007130333A2, WO2007130333A3|
|Publication number||11417846, 417846, US 2007/0257315 A1, US 2007/257315 A1, US 20070257315 A1, US 20070257315A1, US 2007257315 A1, US 2007257315A1, US-A1-20070257315, US-A1-2007257315, US2007/0257315A1, US2007/257315A1, US20070257315 A1, US20070257315A1, US2007257315 A1, US2007257315A1|
|Inventors||Stephen Bedell, Joel de Souza, Zhibin Ren, Alexander Reznicek, Devendra Sadana, Katherine Saenger, Ghavam Shahidi|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Referenced by (12), Classifications (38), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention generally relates to complementary metal oxide semiconductor (CMOS) circuits comprising field effect transistors (FETs) fabricated with one or more ion implantation steps. More particularly, it relates to the ways in which these ion implantation steps may be combined with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained source/drain regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded source/drain regions lattice mismatched with an underlying substrate layer).
Historically, most performance improvements in semiconductor field-effect transistors (FET) have been achieved by scaling down the relative dimensions of the device. This trend is becoming increasingly more difficult to maintain as the devices reach their physical scaling limits. As a consequence, advanced FETs and the complementary metal oxide semiconductor (CMOS) circuits in which they can be found are increasingly relying on strain engineering and specialty silicon-on-insulator substrates to achieve desired circuit performance. However, the ion implantation steps used in fabricating the FETs relying on these enhancements present two particular challenges.
The first challenge pertains to source/drain (S/D) implants in CMOS fabricated in ultrathin silicon-on-insulator (UTSOI) substrates, where the UTSOI layer is typically in the range from 6 to 30 nm in thickness. It is difficult to implant the desired concentration of certain dopant species in the S/D regions without amorphizing the entire SOI layer. If there is no crystalline Si left under the amorphized S/D regions to act as a seed or template, the S/D recrystallization will be highly defective (and thus unsuitable for high performance devices). Through-SOI-thickness amorphization is of particular concern with heavy ions such as As+ and with UTSOI layers on the thin end of the thickness range. This problem is illustrated in
The second challenge pertains to FETs relying on strain engineering. In these FETs, the channel regions of the transistors are strained to produce an increase in the mobility of the charge carriers and thus an increase in the on-state current of the device (at a given drain potential). One method that is currently used to induce channel strain is to grow a compressively strained SiGe layer in a recessed region adjacent to the channel region of the device, as described in U.S. Pat. No. 6,621,131, “Semiconductor Transistor Having a Stressed Channel,” issued Sep. 16, 2003. The SiGe layer then serves as the S/D of the device and imparts uniaxial strain on the channel. The amount of strain in the channel will be proportional to the stress applied by the SiGe layer, which would typically increase with the Ge content of the SiGe. Since increased strain in the channel correlates with better device performance, there is a great interest in SiGe stressors having a high Ge content.
One of the primary challenges in using single-crystal strained regions as a stressor for the channel is to prevent the formation of strain relieving dislocations during strained region growth and subsequent processing. It has been found that the ion implantation step that is used to dope and electrically activate the S/D regions facilitates the relaxation of the strain in the SiGe S/D regions, as illustrated in
Certain implantation conditions (particularly those involving heavy ions such as As+) can result in a significant and irreversible reduction in strain after a prescribed thermal treatment step called an “activation anneal.” Since the driving force for strain relaxation increases with strain, SiGe alloys with a high Ge content are particularly susceptible to undesired relaxation. A method for S/D ion implantation and activation that minimizes S/D plastic relaxation and preserves as much strain as possible would be highly desirable.
The efficacy of heated implants in reducing ion implant damage in bulk semiconductors has been known for some time. The threshold dose of implanted ions required to amorphize a given semiconductor region in a substrate increases with substrate temperature because the transmition from a crystalline material to an amorphous one is determined by the competition between the temperature-independent rate at which the damage and disorder are generated by the implanted ions and the temperature-dependent rate at which the implant damage can be spontaneously repaired. For example, the threshold dose required for amorphization with 200 keV B implanted at low current densities into 100-oriented single crystal Si increases by a factor of 40 as the Si substrate temperature is increased from 200 K to 300 K as described by F. F. Morehead et al., J. Appl. Phys. 43 1112 (1972). While these and similar effects are well known for bulk Si and the III-Vs, the benefits of hot implants have not been previously applied to solve the new problems addressed by the present invention, namely, reduction and/or elimination of (i) implant-induced source/drain amorphization in UTSOI CMOS, and (ii) implant-induced plastic relaxation in FETs with strained source/drain regions.
It is therefore an object of this invention to provide an ion implantation method that allows the desired dopant density profiles to be achieved with satisfactorily limited amorphized layer thicknesses and/or satisfactorily low levels of strain relaxation.
It is a further object of this invention to provide an alternative to the ion implantation method above, wherein said alternative also produces satisfactorily limited amorphized layer thicknesses and/or satisfactorily low levels of strain relief, that is easier to implement with existing tooling.
The present invention teaches the use of ion implantation in combination with in situ or ex situ heat treatments as a method for avoiding or reducing ion implant-induced amorphization and ion implant-induced plastic relaxation.
In a first embodiment of the invention, ion implantation is combined with in situ heat treatment, i.e., implants having the potential to produce undesired amorphization or strain relief are performed at elevated temperature with respect to room temperature. In particular, the invention describes:
The elevated temperatures for the in situ heat treatments of this invention would typically be in the range from 70 to 900° C., preferably be in the range from 150 to 550° C., and most preferably be in the range from 200 to 350° C. Ion implantation at elevated temperatures may also be conveniently described as “hot implantation,” “hot implants,” “heated implantation,” or “heated implants.”
In a second embodiment of the invention, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme that avoids the need for tooling capable of performing hot implants. In this embodiment, the desired total dose is divided into smaller sub-doses, each of which is below the threshold for amorphizing the entire thickness of the S/D regions (for the case of UTSOI) or generating significant strain relief (for the case of strained S/D regions). Annealing performed after each implant recrystallizes the amorphized regions by solid phase epitaxy and/or reduces damage accumulation to a negligible level.
Another aspect of the invention provides FETs and CMOS circuits fabricated with heated implants and/or the DDAB method of implantation.
These and other features, objects, and advantages of the present invention will become apparent upon a consideration of the following detailed description of the invention when read in conjunction with the drawings, in which:
Referring now to the drawings,
Patterned masking layers may be used in these hot implant processes. Ideally, patterned masking layers not remaining in the final device (i.e., disposable masking layers) would be formed prior to the hot implantation step and removed after the hot implantation step. These patterned masking layers would typically define first source/drain (or other) regions that would be subjected to the hot implantation and second source/drain (or other) regions that would be protected from the hot implantation. These disposable masking layers are preferably easily patterned, thermally stable, and easy to remove without damaging the underlying substrate. An example of a mask material meeting these requirements is amorphous carbon with a hydrogen content less than about 15 atomic %. This material is thermally stable and may be patterned (as well as removed) by oxygen-based plasma etching without damage to underlying oxide, nitride, and/or silicon substrate layers. While oxide and nitride layers are also thermally stable and perhaps more easily patterned than amorphous carbon, such materials are harder to remove selectively with respect to the substrate. Multilayer masks comprising one or more upper oxide and/or nitride layers on a base layer of amorphous carbon may provide the optimum compromise between ease of patterning and selective removal.
In a second embodiment of the invention, ion implantation is combined with ex situ heat treatments in a “divided-dose-anneal-in-between” (DDAB) scheme. In this embodiment, the desired total dose is divided into smaller sub-doses, each of which is below the threshold for amorphizing the entire thickness of the S/D regions (for the case of UTSOI) or generating significant strain relief (for the case of strained S/D regions). Annealing performed after each implant restores the S/D regions to their pre-implant levels of crystallinity and/or strain before the accumulated damage reaches a level that is irreversible. Depending on the implantation conditions (species, energy, dose, ion angle of incidence, substrate temperature, etc.), some to none of the thickness of the implanted S/D regions may be amorphized. For high-dose implants producing an amorphous layer, the between-implant anneals restore the initial crystallinity by solid phase epitaxy; for low-dose, non-amorphizing implants, the between-implant anneals remove the incipient nucleation sites for strain-relieving dislocations before they fully develop.
The basic DDAB method of ion implantation comprises
The DDAB method would typically further include
The DDAB method may contain any number of implant and anneal steps to achieve the desired dopant dose and profile with sufficiently low damage to the semiconductor layer regions being implanted. For more than two implant steps, the basic DDAB method above would further include one or more cycles of supplemental implant and annealing steps comprising
The DDAB method of ion implantation may also be implemented without regard to the final levels of semiconductor layer damage, in accord with the previously described steps of
This version of the DDAB method may also include one or more cycles of supplemental implant and annealing steps comprising
Suitable materials for masks used with DDAB are similar to those described above for hot implants. In addition, between-implant anneal temperatures of 230° C. and below are expected to be compatible with many patterned photoresist layers. If higher temperatures are needed (as expected), one may strip the resist before each annealing step and reapply it before each implant step.
Another aspect of the invention provides at least one FET device in a semiconductor layer, the FET device comprising source/drain regions subjected to ion implantation while the semiconductor-on-insulator is held at an elevated temperature in the range from 70° C. to 900° C. While the temperature is held at an elevated temperature the temperature takes into account the temperature rise of the semiconductor-on-insulator due to self heating during ion implantation, which typically is in the range from 0° C. to 50° C. Typically, temperature increases encountered without deliberate wafer cooling are less than 25° C., but may be as high as 50° C. for high does, high current implants.
This invention also provides an FET device in a semiconductor layer, the FET device comprising source/drain regions is subjected to a divided-dose-anneal-in-between (DDAB) method of ion implantation comprising the steps of
This invention also provides FET devices subjected to DDAB methods of ion implantation with multiple implant and annealing cycles, such as, for example, multiple implant and annealing cycles comprising the above first and final implants and anneals plus one or more cycles of supplemental implant and annealing steps comprising
The FETs of this invention may be combined with other FETs to form complementary metal-oxide-semiconductor (CMOS) or other circuits.
The semiconductor layers described in this invention may comprise bulk semiconductors; semiconductor-on-insulator layers; or a combination of bulk and semiconductor-on-insulator layers such that at least part of the semiconductor layer is bulk and at least part of the semiconductor layer is disposed on an insulator; the semiconductor layers comprising one or more of Si, SiC, Ge, GeC, SiGe and SiGeC; these materials in layered combinations; these materials strained, partially strained (or partially relaxed) and/or unstrained (or fully relaxed).
The semiconductor layer may comprise, for example, a silicon-on-insulator layer with a thickness less than 30 nm and/or FETs comprising semiconductor S/D regions separated by a semiconducting channel region, wherein said S/D regions and said channel regions comprise different semiconductor materials, and wherein said S/D regions are strained, partially strained, or unstrained. Particularly favored examples of the FETs to which the hot implant and DDAB methods of this invention may be applied include (i) FETs comprising a semiconducting channel region of Si and S/D regions of a strained SiGe alloy having a Ge content equal to or greater than 25 atomic percent, and (ii) FETs comprising a semiconducting channel region of Si and S/D regions of a strained SiC alloy having a C content greater than 0.5 atomic percent. The semiconductor layers may comprise of a single crystal orientation such as (100) or two or more single crystal orientations (as typified by hybrid orientation substrate technology) such as regions of (100) and (110).
The elevated temperatures for the heated implants of this invention would typically be in the range from 70 to 900° C., preferably be in the range from 150 to 550° C., and most preferably be in the range from 200-350° C. Annealing for the DDAB method would typically include any annealing process known to the art, including furnace annealing, rapid thermal annealing, and laser annealing, for time and temperature ranges known to the art, e.g., temperatures in the range from 150 to 1350° C. and times in the range from 24 hours to sub-milliseconds. Gas ambients may be selected from those known to the art, typically N2 or Ar with or without additional additives selected from the group NH3, H2O, H2, O2, NO, N2O, etc.
The ion implantation of this invention may be performed with any ion known to the art, including atomic ions, molecular ions, singly-charged ions, and multiply-charged ions. Particularly favored ions include the ions of As, B, B1, BF2, Ge, P and Sb. The conditions for the individual implants comprising the DDAB method may be the same or different in one or more particulars (for example, first and final implants might utilize the same species and energy but be different in angle of incidence).
Three examples of the invention will now be described. In the first, it is shown that in situ heating during ion implantation can prevent the amorphization of SOI layers that would occur if the same implants were performed at room temperature such as in the range from 20° C. to 25° C. In the second example, we show how the dependence of amorphization depth on As implant dose may be used to calculate an optimum implementation of the DDAB technique in a semiconductor-on-insulator layer. In the third example, we show how the hot implant and DDAB techniques may be used to preserve the strain in pseudomorphic SiGe layers grown on Si.
The example shows that in situ heating during ion implantation can prevent the amorphization of SOI layers that would occur if the same implants were performed at room temperature. SOI layers 28 nm in thickness were implanted at 26, 150, or 300° C. with 3×1015/cm2 50 keV As+, an implant that has an average projected range (Rp) of about 340 Å and would ordinarily completely amorphize the SOI layer. The reflectance vs. wavelength data of
Table I shows Rs measurements (ohm/sq) of samples implanted with 3×1015/cm2 50 keV As+.
TABLE I Anneal/Implant Temperature 26° C. 150° C. 300° C. as-implanted >1000 k >1000 k 15.5 k 500° C./1 min >1000 k >1000 k 4.4 k 900° C./1 min 10.7 k 8.2 k 790
In the second example; we show how one may use the dependence of amorphization depth on implant dose to calculate an optimum implementation of the DDAB technique in a semiconductor-on-insulator layer disposed on a buried oxide (box). SOI layers 160 nm in thickness were implanted at room temperature with 100 keV As+ (Rp about 71 nm) at doses of 1.25, 2.5, and 5.0×1015/cm2 to produce surface amorphous layers having thicknesses of 91, 111, and 117 nm respectively. None of these doses were sufficient to amorphize the entire 160 nm thickness of the SOI layer. However, SOI layers thinner than about 110 nm in thickness would be expected to totally amorphize at doses higher than 2.5×1015/cm2, form polycrystalline Si upon activation annealing. Dividing the 2.5×1015/cm2 dose into two doses of 1.25×1015/cm2 would leave a residual crystalline layer between the 91 nm amorphization depth and the top of the box after each implant. Annealing between the implants allows the crystallinity of the sample to be restored (by SPE templating from the residual crystalline layer) before the next implant and results in a crystalline material after a final activation anneal.
In the third example, we show how the hot implant and DDAB techniques may be used to preserve the strain in pseudomorphic SiGe layers grown on Si.
It should be noted that the DDAB technique of course involves a tradeoff between the process time for the additional implant and annealing steps and the benefits of further subdivision in implant dose (as measured by a decrease in strain loss). In many cases, the double-step-implant/anneal sequence may be selected optimal. However, the optimal number of subdivisions is likely to be higher for the case of SiGe with a high Ge content and/or materials requiring high implant doses.
While several embodiments of the invention, together with modifications thereof, have been described in detail herein and illustrated in the accompanying drawings, it will be evident that various further modifications are possible without departing from the scope of the invention. For example, (i) multiple hot implants differing in dose, species, and/or energy might be performed with the same masking layer, and/or (ii) the individual implants comprising the DDAB method might include some in situ heating during implantation. Nothing in the above specification is intended to limit the invention more narrowly than the appended claims. The examples given are intended only to be illustrative rather than exclusive.
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7790540||Aug 25, 2006||Sep 7, 2010||International Business Machines Corporation||Structure and method to use low k stress liner to reduce parasitic capacitance|
|US7955928||Mar 30, 2009||Jun 7, 2011||International Business Machines Corporation||Structure and method of fabricating FinFET|
|US8486778||Jul 15, 2011||Jul 16, 2013||International Business Machines Corporation||Low resistance source and drain extensions for ETSOI|
|US8546203||Jul 17, 2012||Oct 1, 2013||International Business Machines Corporation||Semiconductor structure having NFET extension last implants|
|US8557692||Jan 12, 2010||Oct 15, 2013||Taiwan Semiconductor Manufacturing Company, Ltd.||FinFET LDD and source drain implant technique|
|US8614486||Sep 6, 2012||Dec 24, 2013||International Business Machines Corporation||Low resistance source and drain extensions for ETSOI|
|US8673699||Jul 17, 2012||Mar 18, 2014||International Business Machines Corporation||Semiconductor structure having NFET extension last implants|
|US8722431||Mar 22, 2012||May 13, 2014||Varian Semiconductor Equipment Associates, Inc.||FinFET device fabrication using thermal implantation|
|US8815634 *||Oct 28, 2009||Aug 26, 2014||Varian Semiconductor Equipment Associates, Inc.||Dark currents and reducing defects in image sensors and photovoltaic junctions|
|US20100110239 *||Oct 28, 2009||May 6, 2010||Deepak Ramappa||Dark currents and reducing defects in image sensors and photovoltaic junctions|
|US20140349460 *||May 6, 2014||Nov 27, 2014||Commissariat A L'energie Atomique Et Aux Energies Alternatives||Method for producing a silicon-germanium film with variable germanium content|
|WO2013142688A1 *||Mar 21, 2013||Sep 26, 2013||Varian Semiconductor Equipment Associates, Inc.||Finfet device fabrication using thermal implantation|
|U.S. Classification||257/350, 257/E21.415, 257/E21.431, 257/E21.336, 257/E29.277, 257/E21.324, 257/E21.43, 438/197, 257/E29.085, 257/E29.297, 257/E21.634, 257/E27.112, 257/E21.703|
|Cooperative Classification||H01L29/78684, Y10S438/909, H01L21/324, H01L27/1203, Y10S438/943, H01L29/66636, H01L29/78618, H01L21/84, H01L29/165, H01L21/823814, H01L29/66628, H01L29/66772, H01L21/26513, H01L29/7848|
|European Classification||H01L29/66M6T6F15C, H01L29/66M6T6F11E, H01L29/66M6T6F11D3, H01L29/78R6, H01L27/12B, H01L29/786G, H01L21/84, H01L29/786B4, H01L21/265A2, H01L21/324|
|Jun 21, 2006||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BEDELL, STEPHEN W;DE DOUZA, JOEL P;REN, ZHIBIN;AND OTHERS;REEL/FRAME:017821/0934;SIGNING DATES FROM 20060511 TO 20060517