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Publication numberUS20070262389 A1
Publication typeApplication
Application numberUS 11/828,290
Publication dateNov 15, 2007
Filing dateJul 25, 2007
Priority dateJan 16, 2004
Also published asCN1930671A, CN100550324C, EP1704590A1, US7268058, US20050158970, WO2005071730A1
Publication number11828290, 828290, US 2007/0262389 A1, US 2007/262389 A1, US 20070262389 A1, US 20070262389A1, US 2007262389 A1, US 2007262389A1, US-A1-20070262389, US-A1-2007262389, US2007/0262389A1, US2007/262389A1, US20070262389 A1, US20070262389A1, US2007262389 A1, US2007262389A1
InventorsRobert Chau, Suman Datta, Brian Doyle, Been-Yih Jin
Original AssigneeRobert Chau, Suman Datta, Doyle Brian S, Been-Yih Jin
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Tri-gate transistors and methods to fabricate same
US 20070262389 A1
Abstract
Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.
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Claims(20)
1. An integrated circuit device comprising:
a substrate; and
a plurality of transistors formed upon the substrate, each transistor of the plurality having a semiconductor body, each semiconductor body having a height (Hsi) of less than 20 nm, the height (Hsi) across the plurality of transistors being uniform to within 5%.
2. The integrated circuit device of claim 1, wherein the semiconductor body is adjacent to a dielectric layer on the substrate, the dielectric layer having a thickness uniformity across the substrate that is lower than the uniformity of the height the semiconductor body (Hsi) across the plurality of transistors.
3. The integrated circuit device of claim 2, wherein the semiconductor body has a height (Hsi) of approximately 10 nm and the variation in Hsi across the plurality of transistors no greater than 0.5 nm.
4. The integrated circuit device of claim 1, wherein the semiconductor body further comprises an upper portion of a semiconductor film, the semiconductor film having a thickness uniformity across the plurality of transistors that is lower than the uniformity of the height semiconductor body (Hsi) across the plurality of transistors.
5. The integrated circuit device of claim 1, wherein the semiconductor body is epitaxial single crystalline semiconductor.
6. The integrated circuit device of claim 5, wherein the substrate comprises single crystalline silicon and the epitaxial single crystalline semiconductor body comprises silicon.
7. The integrated circuit device of claim 1 wherein one or more of the plurality of transistors are tri-gate transistors.
8. An integrated circuit device comprising:
a plurality of transistors on a substrate, each transistor of the plurality having a semiconductor body extending a distance from the substrate, wherein the variation in a transistor body height (HSi) across the plurality is less than the variation in the distance, across the plurality, the semiconductor bodies extend from the substrate.
9. The integrated circuit device of claim 8, wherein the variation in the distance, across the plurality, the semiconductor bodies extend from the substrate is greater than 5% of the transistor body height (Hsi).
10. The integrated circuit device of claim 8, wherein each of said plurality of transistors further comprises:
a gate dielectric on a sidewall of the semiconductor body, wherein the sidewall has a height (HSi) that is less than the distance the semiconductor body extends from the substrate;
a gate electrode on the gate dielectric; and
a source and drain region in the semiconductor body on opposite sides of said gate electrode.
11. The integrated circuit device of claim 10, wherein the gate electrode extends over an isolation dielectric adjacent to the semiconductor body, the isolation dielectric having a thickness uniformity across the substrate that is lower than the uniformity of the transistor body height (HSi) across the plurality of transistors.
12. The integrated circuit device of claim 8, wherein each semiconductor body is epitaxial single crystalline semiconductor.
13. The integrated circuit device of claim 12, wherein the substrate is single crystalline silicon and the epitaxial single crystalline semiconductor body is silicon.
14. The integrated circuit device of claim 8, wherein each semiconductor body has a height of less than 20 nm and the height of each semiconductor body (Hsi) of the plurality of transistors is uniform to within 5%.
15. An integrated circuit device comprising:
a first tri-gate transistor having a gate dielectric on a sidewall of a first semiconductor body, the first semiconductor body extending from a substrate by a first distance, wherein the sidewall of the first semiconductor body has a first sidewall height that is less than the first distance;
a second tri-gate transistor having the gate dielectric on a sidewall of a second semiconductor body, the second semiconductor body extending from the substrate by a second distance wherein the sidewall of the second semiconductor body has a second sidewall height that is less than the second distance and wherein the second sidewall height is within 5% of the first sidewall height.
16. The integrated circuit device of claim 15, wherein the second distance is different from the first distance by more than 5% of either the first or second sidewall height.
17. The integrated circuit device of claim 16, wherein the first and second sidewall height are approximately 10 nm.
18. The integrated circuit device of claim 15, further comprising a dielectric isolation layer between the first and second tri-gate transistor, the dielectric isolation layer having a thickness variation of more than 5% of either the first or second sidewall height.
19. The integrated circuit device of claim 15, wherein the first and second semiconductor body comprises epitaxial single crystalline semiconductor.
20. The integrated circuit device of claim 19, wherein the epitaxial single crystalline semiconductor comprises silicon.
Description

This application is a divisional of U.S. patent application Ser. No. 10/760,028 filed Jan. 16, 2004.

FIELD

Embodiments of the invention relate generally to the field of integrated circuit device fabrication and more specifically to tri-gate transistor fabrication.

BACKGROUND

The trend toward increasing the number of functions of an integrated circuit device (IC device) is continuing. As the size of transistors decreases, serious drawbacks in current transistor fabrication processes become evident. For example, typical silicon-on-insulator (SOI) transistors are fabricated by coating a substrate with an insulator (e.g., glass or silicon oxide) layer. A second silicon wafer is then bonded to the insulator layer and thinned to a desired thickness (i.e., as determined by the transistor dimensions). This thinning process is very difficult to control with great accuracy.

FIGS. 1A-1D illustrate a portion of the fabrication process for creating a tri-gate SOI transistor in accordance with the prior art. As shown in FIG. 1A, a carrier wafer 101, typically a silicon substrate, has an insulator layer 102, typically silicon dioxide, disposed upon it. For example, a silicon dioxide layer may be grown on a silicon substrate.

As shown in FIG. 1B, a transfer wafer 103 is then bonded to the insulator layer 102, which may facilitate the bonding. The bonding of the carrier wafer to the insulator layer may be effected though a heat-induced hydrogen bonding process. The transfer wafer, which may be, for example, silicon, is approximately 600 microns thick.

The transfer wafer is then thinned to a desired thickness based upon the transistor dimensions. Typically, this thickness is approximately 50-100 nm. The thinning of the transfer wafer may be accomplished through one of several typical processes. For example, a wet etch and polish process may be used to grind the transfer wafer to the desired thickness. An alternative method for thinning the transfer wafer includes hydrogen implantation of the transfer layer to create a weak section of the transfer wafer. The bonded pair is then heated to effect a high temperature cleave of the hydrogen-doped interface. Subsequently, the transfer wafer surface is polished or treated in other ways to planarize the surface or further reduce the thickness. These methods provide control of the thickness to within approximately several hundred angstroms. As shown in FIG. 1C, the transfer wafer 103 has been thinned to a desired dimension for the silicon body of the transistor, resulting in film layer 104. The thickness of film layer 104 is determined by the desired height of the silicon body (HSi). The film layer 104 is then selectively etched to create silicon bodies for the transistors. As shown in FIG. 1D, selectively etching the film layer 104, using lithography techniques, results in silicon bodies 105 having a desired body width (WSi) and body height (HSi).

For typical transistor design architecture, gate length is proportional to HSi, with HSi equal to about one-third of gate length. For typical transistors with gate lengths of approximately 20-100 nm, the desired HSi is greater than approximately 20 nm. Using the current fabrication method, it is possible to create adequate film layers. However, as the gate length, and hence, the desired HSi decreases, current fabrication methods exhibit serious disadvantages.

The HSi value must be uniform across a wafer in order to produce transistors with uniform characteristics. For example, the transistor threshold voltage, which is directly proportional to HSi, should not vary by more than approximately 10%. Therefore, the film layer thickness that determines HSi, should not vary by more than 10%.

The methods of thinning the transfer layer to obtain the film layer are capable of producing a film layer of approximately 20 nm thickness that does not vary by more than approximately 10%. However, these methods fail to produce the required uniformity for thinner film layers. Therefore, current methods of fabricating SOI transistors are incapable of yielding transistors with gate lengths smaller than approximately 50 nm.

Moreover, the process of bonding the carrier wafer and transfer wafer, and the process of thinning the transfer wafer to the desired thickness, are costly and difficult to control.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be best understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. In the drawings:

FIGS. 1A-1D illustrate a process for creating a tri-gate SOI transistor in accordance with the prior art;

FIG. 2 illustrates a process for providing increased uniformity in silicon body height, HSi, in accordance with one embodiment of the invention; and

FIGS. 3A-3G illustrate the fabrication of a tri-gate transistor in accordance with one embodiment of the invention.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Moreover, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of this invention.

FIG. 2 illustrates a process for providing increased uniformity in silicon body height, HSi, in accordance with one embodiment of the invention. Process 200, shown in FIG. 2, begins with operation 205 in which a trench layer is disposed upon a substrate layer. For one embodiment, the trench layer may be disposed upon the substrate layer using a chemical vapor deposition (CVD) process. For one embodiment, the substrate layer is silicon. For alternative embodiments, the substrate layer may be another semiconductor material such as germanium (Ge) or gallium arsenide (GaAs). For one embodiment, the trench layer thickness is determined based upon the specification of the transistor's gate length. That is, the trench layer thickness is selected to be equal to a desired HSi value.

At operation 210, selected portions of the trench layer are removed, thus forming trenches. For one embodiment, the trench layer is a material that can be selectively etched using conventional etching processes. For various alternative embodiments, the trench layer may be multiple layers of different materials with each material. In one such embodiment, the multiple layers of the trench layer are susceptible to different etching processes.

At operation 215, the trenches formed by operation 210, are filled with a semiconductor material (e.g., silicon). For one embodiment, the trenches are filled with epitaxial silicon using a selective epitaxial process. In an alternative embodiment, the trenches are filled in some other manner. For example, the trenches may be filled with polysilicon using a blanket deposition process.

At operation 220, the excess semiconductor material is removed. That is, semiconductor material filling the trench that extends above the surface of the remainder of the trench layer is removed. For one embodiment, a chemical-mechanical polish (CMP) is employed to planarize the surface of the semiconductor material.

At operation 225, the remainder of the trench layer is removed exposing semiconductor fins (i.e., the semiconductor material filling the trenches). For one embodiment, the height of the semiconductor fins is uniform to within less than 5%.

FIGS. 3A-3G illustrate the fabrication of a tri-gate transistor in accordance with one embodiment of the invention. FIG. 3A shows a silicon substrate 301. A multi-layer trench layer is disposed on the silicon substrate 301. The trench layer is comprised of a first oxide (e.g., SiO2) layer 302, a nitride (e.g., Si3N4) layer 303, and a second oxide (e.g., SiO2) layer 304. Eventually the tri-gate body thickness, HSi, will be determined by the thickness of the second oxide layer, which is a very controllable thickness.

FIG. 3B illustrates the application of a photoresist mask layer 305 to define the transistor bodies. The patterning of the photoresist mask layer 305 determines the width of the silicon body, WSi.

FIG. 3C illustrates the etching of the trench layer to define trenches 306 a and 306 b. For one embodiment, a series of three distinct dry etch processes are employed. In such an embodiment, the second oxide layer 304 is etched using a selective dry etch process in which the nitride layer 303 acts as an etch stop. Then the nitride layer 303 is etched using a different selective dry etch process in which the first oxide layer 302 acts as an etch stop. Finally, the first oxide layer 302 is etched using a dry etch process that is sufficiently selective to stop on the surface of the silicon substrate 301.

FIG. 3D illustrates filling trenches 306 a and 306 b with silicon 307 after the photoresist layer 305 has been stripped away, as indicated. As noted above, the trenches may be filled with silicon through various alternative methods including epitaxial growth or blanket deposition of polysilicon.

FIG. 3E illustrates the silicon 307 planarized to the level of the second oxide layer 304. For one embodiment, the planarization is effected using a CMP process. For one embodiment, the polishing process is used to remove the second oxide layer 304 and the nitride layer 303 is used as a polish stop. For such an embodiment, the polish has a high selectivity between oxide and nitride. For an alternative embodiment, the second oxide layer 304 is selectively etched to the nitride layer 303. Subsequently, the nitride layer 303 is etched using a wet etch process using, for example, phosphoric acid. The first oxide layer 302 acts as an etch stop for such a process.

FIG. 3F illustrates the silicon bodies for the tri-gate transistors exposed with the removal of the trench layer (e.g., second oxide layer 304 and the nitride layer 303). As shown in FIG. 3F, a portion of the trench layer (e.g., first oxide layer 302) may be retained to effect beneficial properties of the transistor as explained below. The silicon 307 forming the gate bodies has a uniform height to within a specified tolerance. For one embodiment, the height, HSi, of silicon 307 is approximately 10 nm and is uniform within 5%.

FIG. 3G illustrates the tri-gate transistor fabricated by forming a gate 308 surrounding the silicon 307. The gate 308 may be, for example, metal or another suitable material as known in the art.

General Matters

Embodiments of the invention include various operations. Many of the methods are described in their most basic form, but operations can be added to or deleted from any of the methods without departing from the basic scope of the invention. For example, the trench layer, described in operation 205 of FIG. 2, may be disposed on the substrate in various alternative matters and may be comprised of more than one layer as illustrated in FIG. 3A. Furthermore, a portion of the trench layer may be retained to effect benefits. As shown in FIGS. 3F and 3G, a portion of the first oxide layer is retained to reduce fringe capacitance in the transistor.

As described above, the trenches formed in the trench layer may be filled with silicon in a number of ways including, for example, blanket deposition of polysilicon. For an embodiment in which a blanket deposition of polysilicon is used, an annealing process is employed after deposition to anneal the silicon into a single crystal.

While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5466621 *Oct 25, 1993Nov 14, 1995Hitachi, Ltd.Method of manufacturing a semiconductor device having silicon islands
US20020036290 *Sep 24, 2001Mar 28, 2002Kabushiki Kaisha ToshibaSemiconductor device having MIS field effect transistors or three-dimensional structure
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8765563 *Sep 28, 2012Jul 1, 2014Intel CorporationTrench confined epitaxially grown device layer(s)
Classifications
U.S. Classification257/365, 257/E21.442, 257/E29.255, 257/E29.275, 257/390
International ClassificationH01L21/336, H01L29/78, H01L29/786
Cooperative ClassificationH01L29/785, H01L29/66795
European ClassificationH01L29/66M6T6F16, H01L29/786D2, H01L29/786S, H01L29/786D