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Publication numberUS20070262395 A1
Publication typeApplication
Application numberUS 11/432,442
Publication dateNov 15, 2007
Filing dateMay 11, 2006
Priority dateMay 11, 2006
Also published asUS8692320, US20120061751
Publication number11432442, 432442, US 2007/0262395 A1, US 2007/262395 A1, US 20070262395 A1, US 20070262395A1, US 2007262395 A1, US 2007262395A1, US-A1-20070262395, US-A1-2007262395, US2007/0262395A1, US2007/262395A1, US20070262395 A1, US20070262395A1, US2007262395 A1, US2007262395A1
InventorsJasper Gibbons, Darren Young, Kunal Parekh, Casey Smith
Original AssigneeGibbons Jasper S, Young Darren V, Parekh Kunal R, Casey Smith
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Memory cell access devices and methods of making the same
US 20070262395 A1
Abstract
Planar access transistor devices and recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode. Access device drivers are also provided which are capable of driving distinct or identical voltages to the gate electrodes.
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Claims(90)
1. A gate electrode, comprising:
a first gate material having a first work function associated therewith; and
a second gate material having a second work function associated therewith.
2. The gate electrode of claim 1, wherein the first work function associated with the first gate material is different than the second work function associated with the second gate material.
3. The gate electrode of claim 1, further comprising a separator between the first gate material and the second gate material.
4. The gate electrode of claim 3, wherein the separator comprises a material selected from the group consisting of a nitride, an oxide, a silicide, a conductive metal, and a metallic alloy.
5. The gate electrode of claim 3, further comprising a conductive strap in contact with the first gate material and the second gate material.
6. The gate electrode of claim 2, further comprising a trench in a semiconductor substrate, wherein the first gate material and at least a portion of the second gate material are deposited in the trench of the semiconductor substrate.
7. The gate electrode of claim 1, further comprising a conductive material separating the first gate material and the second gate material.
8. The gate electrode of claim 7, wherein the conductive material comprises a material selected from the group consisting of metals, doped silicon, doped polysilicon, and conductive silicon materials.
9. The gate electrode of claim 1, wherein the first gate material is electrically isolated from the second gate material.
10. The gate electrode of claim 9, wherein the first work function is different than the second work function.
11. The gate electrode of claim 9, further comprising at least one additional gate material, wherein the at least one additional gate material is electrically isolated from the first gate material and the second gate material.
12. The gate electrode of claim 9, wherein the first gate material and the second gate material each comprise a material selected from the group consisting of polysilicon, doped polysilicon, silicon, and doped silicon.
13. The gate electrode of claim 9, wherein the first gate material is electrically isolated from the second gate material in a trench of a recessed access device.
14. The gate electrode of claim 9, further comprising an insulator positioned between the first gate material and the second gate material, wherein the insulator provides electrical isolation between the first gate material and the second gate material.
15. The gate electrode of claim 14, wherein the insulator comprises a material selected from the group consisting of silicon nitride, and silicon dioxide.
16. The gate electrode of claim 1, wherein the first gate material comprises an anode and the second gate electrode comprises a cathode.
17. The gate electrode of claim 16, wherein the first gate material is a p-type material.
18. The gate electrode of claim 16, wherein the second gate material is an n-type material.
19. A planar access device, comprising:
a semiconductor substrate;
an oxide layer positioned over the semiconductor substrate;
a first gate material overlying the oxide layer;
a second gate material overlying the oxide layer;
an electrical connection between the first gate material and the second gate material; and
an insulator cap overlying the first gate material and the second gate material.
20. The planar access device of claim 19, further comprising at least two sidewall spacers positioned on the sides of the gate stack and isolating the first gate material and the second gate material between the at least two sidewall spacers and under the insulator cap.
21. The planar access device of claim 19, further comprising a separator positioned between the first gate material and the second gate material.
22. The planar access device of claim 19, wherein the first gate material and the second gate material each contact the oxide layer.
23. The planar access device of claim 19, wherein the first gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
24. The planar access device of claim 19, wherein the second gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
25. The planar access device of claim 19, wherein the first gate material comprises a doped polysilicon material and the second gate material comprises a doped polysilicon material, wherein the first gate material and the second gate material are doped with different dopants.
26. The planar access device of claim 19, wherein the electrical connection comprises a conductive strap in contact with the first gate material and the second gate material.
27. The planar access device of claim 26, wherein the conductive strap comprises a conductive material selected from the group consisting of metal, doped polysilicon, doped silicon, and a metal alloy.
28. The planar access device of claim 26, wherein the conductive strap comprises a conductive strap positioned between the first gate material and the second gate material.
29. The planar access device of claim 26, wherein the conductive strap comprises a conductive strap positioned over the first gate material and the second gate material.
30. A recessed access device, comprising:
a semiconductor substrate;
at least one trench in the semiconductor substrate;
an oxide layer positioned over sidewalls of the at least one trench;
a first gate material in a bottom portion of the at least one trench and overlying at least a portion of the oxide layer;
a second gate material in the at least one trench and overlying the first gate material;
an electrical connection between the first gate material and the second gate material; and
an insulator cap overlying the second gate material.
31. The recessed access device of claim 30, further comprising a metal barrier positioned between the first gate material and the second gate material.
32. The recessed access device of claim 30, wherein the first gate material and the second gate material each contact the oxide layer.
33. The recessed access device of claim 30, wherein the first gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
34. The recessed access device of claim 30, wherein the second gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
35. The recessed access device of claim 30, wherein the first gate material comprises a doped polysilicon material and the second gate material comprises a doped polysilicon material, wherein the first gate material and the second gate material are doped with different dopants.
36. The recessed access device of claim 30, wherein the electrical connection comprises a barrier layer in contact with the first gate material and the second gate material.
37. The recessed access device of claim 36, wherein the barrier layer comprises a material selected from the group consisting of metal, doped polysilicon, doped silicon, and an insulator material.
38. The recessed access device of claim 36, wherein the barrier layer comprises a barrier layer positioned between the first gate material and the second gate material.
39. A recessed access device, comprising:
a semiconductor substrate;
at least one trench in the semiconductor substrate;
an oxide layer positioned over sidewalls of the at least one trench;
a first gate material positioned over at least a portion of the sidewalls of the at least one trench;
a second gate material in the at least one trench and at least partially surrounded by the first gate material; and
an insulator cap overlying the first gate material and the second gate material.
40. The recessed access device of claim 39, wherein the first gate material and the second gate material each contact the oxide layer.
41. The recessed access device of claim 39, wherein the first gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
42. The recessed access device of claim 39, wherein the second gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
43. The recessed access device of claim 39, wherein the first gate material comprises a doped polysilicon material and the second gate material comprises a doped polysilicon material, wherein the first gate material and the second gate material are doped with different dopants.
44. The recessed access device of claim 39, wherein the second gate material comprises a material having a higher work function than the first gate material.
45. A planar access device, comprising:
a semiconductor substrate;
an oxide layer positioned over the semiconductor substrate;
a first gate material overlying the oxide layer;
a second gate material overlying the oxide layer;
an insulator between the first gate material and the second gate material; and
an insulator cap overlying the first gate material and the second gate material.
46. The planar access device of claim 45, further comprising at least two sidewall spacers positioned on sides of the gate stack and isolating the first gate material and the second gate material between the at least two sidewall spacers and under the insulator cap.
47. The planar access device of claim 45, wherein the insulator comprises a material selected from the group consisting of silicon nitride and silicon dioxide.
48. The planar access device of claim 45, wherein the first gate material and the second gate material each contact the oxide layer.
49. The planar access device of claim 45, wherein the first gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
50. The planar access device of claim 45, wherein the second gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
51. The planar access device of claim 45, wherein the first gate material comprises a doped polysilicon material and the second gate material comprises a doped polysilicon material, wherein the first gate material and the second gate material are doped with different dopants.
52. The planar access device of claim 45, further comprising:
a first contact between the first gate material and a first voltage supply; and
a second contact between the second gate material and a second voltage supply.
53. The planar access device of claim 52, wherein the first voltage supply and the second voltage supply originate from an access device driver.
54. The planar access device of claim 52, wherein the first voltage supply and the second voltage supply are configured to provide the same or different voltages to the first contact and the second contact.
55. A recessed access device, comprising:
a semiconductor substrate;
at least one trench in the semiconductor substrate;
an oxide layer positioned over sidewalls of the at least one trench;
a first gate material in a bottom portion of the at least one trench and overlying at least a portion of the oxide layer;
an insulator overlying the first gate material;
a second gate material in the at least one trench and overlying the insulator; and
an insulator cap overlying the second gate material.
56. The recessed access device of claim 55, wherein the first gate material and the second gate material each contact the oxide layer.
57. The recessed access device of claim 55, wherein the first gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
58. The recessed access device of claim 55, wherein the second gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, and metal.
59. The recessed access device of claim 55, wherein the first gate material comprises a doped polysilicon material and the second gate material comprises a doped polysilicon material, wherein the first gate material and the second gate material are doped with different dopants.
60. The recessed access device of claim 55, wherein the insulator comprises a material selected from the group consisting of silicon nitride and silicon dioxide.
61. The recessed access device of claim 55, further comprising:
a first contact between the first gate material and a first voltage supply; and
a second contact between the second gate material and a second voltage supply.
62. The recessed access device of claim 61, wherein the first voltage supply and the second voltage supply originate from an access device driver.
63. The recessed access device of claim 61, wherein the first voltage supply and the second voltage supply are configured to provide the same or different voltages to the first contact and the second contact.
64. A planar access device, comprising:
a semiconductor substrate;
an oxide layer positioned over the semiconductor substrate;
a cathode gate material overlying the oxide layer;
an anode gate material overlying the oxide layer and positioned next to the cathode gate material, wherein the anode gate material and the cathode gate material form a diode; and
an insulator cap overlying the cathode gate material and the anode gate material.
65. The planar access device of claim 64, further comprising at least two sidewall spacers positioned on sides of the gate stack and isolating the cathode gate material and the anode gate material between the at least two sidewall spacers and under the insulator cap.
66. The planar access device of claim 64, wherein the cathode gate material and the anode gate material each contact the oxide layer.
67. The planar access device of claim 64, wherein the cathode gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalum nitride.
68. The planar access device of claim 64, wherein the anode gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalum nitride.
69. The planar access device of claim 64, wherein the cathode gate material comprises an n-type cathode material.
70. The planar access device of claim 64, wherein the anode gate material comprises a p-type anode material.
71. The planar access device of claim 64, wherein the cathode gate material comprises a doped polysilicon material and the anode gate material comprises a doped polysilicon material, wherein the cathode gate material and the anode gate material are doped with different dopants.
72. The planar access device of claim 64, further comprising:
a first contact between the cathode gate material and a first voltage supply; and
a second contact between the anode gate material and a second voltage supply.
73. The planar access device of claim 72, wherein the first voltage supply and the second voltage supply originate from an access device driver.
74. The planar access device of claim 72, wherein the first voltage supply and the second voltage supply are configured to provide the same or different voltages to the first contact and the second contact.
75. The gate stack of claim 64, wherein the diode comprises a Schottky-Barrier diode.
76. A recessed access device, comprising:
a semiconductor substrate;
at least one trench in the semiconductor substrate;
an oxide layer positioned over sidewalls of the at least one trench;
an anode gate material in a bottom portion of the at least one trench and overlying at least a portion of the oxide layer;
a cathode gate material in the at least one trench and overlying the anode gate material, wherein the anode gate material and the cathode gate material form a diode; and
an insulator cap overlying the cathode gate material.
77. The recessed access device of claim 76, wherein the anode gate material and the cathode gate material each contact the oxide layer.
78. The recessed access device of claim 76, wherein the anode gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalum nitride.
79. The recessed access device of claim 76, wherein the cathode gate material comprises a material selected from the group consisting of polysilicon, doped polysilicon, metal, ruthenium-tantalum, and tantalum nitride.
80. The recessed access device of claim 76, wherein the anode gate material comprises a doped polysilicon material and the cathode gate material comprises a doped polysilicon material, wherein the anode gate material and the cathode gate material are doped with different dopants.
81. The recessed access device of claim 76, wherein the cathode gate material comprises an n-type cathode material.
82. The recessed access device of claim 76, wherein the anode gate material comprises a p-type anode material.
83. The recessed access device of claim 76, further comprising:
a first contact between the cathode gate material and a first voltage supply; and
a second contact between the anode gate material and a second voltage supply.
84. The recessed access device of claim 83, wherein the first voltage supply and the second voltage supply originate from an access device driver.
85. The recessed access device of claim 83, wherein the first voltage supply and the second voltage supply are configured to provide the same or different voltages to the first contact and the second contact.
86. The recessed access device of claim 76, wherein the diode comprises a Schottky-Barrier diode.
87. A access device driver, comprising an access device driver capable of supplying at least two voltages to an access device.
88. The access device driver of claim 87, wherein the access device driver comprises the access device driver illustrated in FIG. 12.
89. The access device driver of claim 87, wherein the access device driver comprises the access device driver illustrated in FIG. 13.
90. The access device driver of claim 87, further comprising a resistor, wherein the resistor is in electrical communication with at least one of the at least two voltages supplied by the access device driver.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to MOSFET devices and, in particular, to planar access devices and recessed access devices for semiconductor devices and methods of making the same.

2. Technical Background

Semiconductor devices employ access devices to store and retrieve data stored in memory circuits. The access devices may include semiconductor structures such as transistor devices, and can be in the form of planar or recessed access device structures. The gate electrode of an access device is biased, by an access device driver circuit, providing “on” and “off” states for the access device and facilitating the access and storage of data in the memory circuit utilizing the access devices. When the device is “on,” current is allowed to flow through the access device, and therefore the transistor is in inversion. When the device is “off,” current is supposed to be blocked from flowing through the access device, and therefore the transistor is in accumulation.

FIG. 1 illustrates a conventional planar access device (PAD) or transistor device, used with semiconductor memory circuits. A gate stack 60 is formed over a semiconductor substrate 50. The gate stack 60 includes a gate oxide layer 62, a gate electrode 64, an insulator cap 66, and sidewall spacers 68. Source and drain regions 54 are located on either side of the gate stack 60 forming the transistor device.

FIG. 2 illustrates a conventional recessed access device (RAD) used with semiconductor memory circuits. The RAD structure includes a gate stack 70 formed in trenches of a semiconductor substrate 50. The gate stack 70 includes a gate oxide layer 72, a gate electrode 74, an insulator cap 76, and sidewall spacers 78. Source and drain regions 54 are located on either side of the gate stack 70 forming the RAD device.

The PAD and RAD structures illustrated in FIGS. 1 and 2 may be used as access devices for memory circuits. As the dimensional requirements of semiconductor structures continue to diminish in size, fabrication processes are developed to accommodate the shrinking dimensions. For a memory circuit, utilizing either a PAD or RAD structure as the access device, there are three major undesirable leakage paths in the transistor: subthreshold leakage, gate induced drain leakage (GIDL), and junction leakage. Each leakage type occurs when the access device is in accumulation, or the “off” state. Subthreshold leakage is the leakage of charge between the source and drain of the access device and increases with smaller transistor dimensions, specifically the effective length of the gate in an access device. One way of reducing the subthreshold leakage is to apply a more negative voltage to the gate electrode of the access device in the “off” state. For example, in an “off” state, a negative voltage is applied to the PAD gate electrode 64 or the RAD gate electrode 74, illustrated in FIGS. 1 and 2 respectively. However, the application of a more negative voltage to the gate electrode results in higher GIDL current in the access device. Another way of reducing the subthreshold leakage is to apply a more negative voltage to the substrate 50. However, the application of a more negative voltage to the substrate results in increased junction leakage. Subthreshold leakage may also be decreased by employing a high work function difference between the source and drain regions and a gate electrode, for example by employing a P+ gate and an N+ source/drain region. However, GIDL current increases in such cases.

Furthermore, the RAD gate stack 70, and the use of RAD gate stacks 70 with semiconductor devices, increases the effective length of a gate in an access device compared to the PAD gate stack 60. The increased length of the gate tends to decrease the amount of subthreshold leakage in the access device. However, the GIDL current from the RAD gate stack 70 is greater than the GIDL current of PAD gate stack 60. It is believed that the increased amount of GIDL loss in the RAD gate stack 70 is the result of the increased overlap of the source/drain regions 54 with the gate electrode 74.

Therefore, it is desirable to develop an access device for use with memory devices and other semiconductor devices that may be able to reduce subthreshold leakage, junction leakage, and gate induced drain leakage simultaneously. It is also desirable to develop processes for fabricating such devices using conventional semiconductor fabrication processes.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, this invention can be more readily understood and appreciated by one of ordinary skill in the art from the following description of the invention when read in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a cross-sectional view of a conventional planar access device such as a memory access device;

FIG. 2 illustrates a cross-sectional view of a conventional recessed access device such as a memory access device;

FIG. 3 illustrates a cross-sectional view of a planar access device according to embodiments of the invention;

FIGS. 4A-4E illustrate cross-sectional views of various process steps in the fabrication of the planar access device illustrated in FIG. 3 according to embodiments of the invention;

FIG. 5 illustrates a cross-sectional view of a recessed access device structure according to embodiments of the invention;

FIGS. 6A-6E illustrate cross-sectional views of various process steps in the fabrication of the recessed access device structure illustrated in FIG. 5 according to embodiments of the invention;

FIG. 7A illustrates a cross-sectional view of a recessed access device structure according to embodiments of the invention;

FIGS. 7B-7D illustrate cross-sectional views of various process steps in the fabrication of the recessed access device structure illustrated in FIG. 7A according to embodiments of the invention;

FIG. 7E illustrates a cross-sectional view of a spherical recessed access device structure according to embodiments of the invention;

FIG. 8 illustrates a cross-sectional view of a planar access device according to embodiments of the invention;

FIGS. 9A-9D illustrate cross-sectional views of various process steps in the fabrication of the planar access device illustrated in FIG. 8 according to embodiments of the invention;

FIG. 10 illustrates a cross-sectional view of a recessed access device structure according to embodiments of the invention;

FIGS. 11A-11D illustrate cross-sectional views of various process steps in the fabrication of the recessed access device illustrated in FIG. 10 according to embodiments of the invention;

FIG. 12 illustrates an access device driver according to embodiments of the invention which may be used to supply voltages to a planar or recessed access device;

FIG. 13 illustrates an access device driver according to embodiments of the invention which may be used to supply voltages to a planar or recessed access device;

FIG. 14 illustrates a cross-sectional view of a planar access device according to embodiments of the invention;

FIGS. 15A-15D illustrate cross-sectional views of various process steps in the fabrication of the planar access device illustrated in FIG. 14 according to embodiments of the invention;

FIG. 16 illustrates a cross-sectional view of a recessed access device according to embodiments of the invention; and

FIGS. 17A-17D illustrate cross-sectional views of various process steps in the fabrication of the recessed access device of FIG. 16 according to embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the invention relate to planar and recessed access transistor devices used in semiconductor devices. More particularly, embodiments of the invention relate to planar and recessed access devices that may be used with CMOS semiconductor devices or memory devices such as DRAM memory devices. However, the embodiments of the invention are not limited to such devices as the planar and recessed access devices of the invention may be used with any semiconductor device.

According to some embodiments of the invention, a planar or recessed access device may include a gate electrode having two or more gate materials wherein each of the gate materials has a different work function than the other gate materials of the gate electrode. The presence of the two or more work functions in the gate electrode may help to reduce the amount of gate induced drain leakage that occurs in the gate stack or recessed access device. Furthermore, the reduction of the gate induced drain leakage may be accomplished without sacrificing additional losses due to subthreshold leakage or junction leakage, which is controlled by the difference and margin bias provided by the different work function materials in the gate electrode.

According to other embodiments of the invention, a planar or recessed access device may include a gate electrode having two or more electrically isolated regions. The electrically isolated regions of the gate electrode may be supplied by different voltage supplies such that different voltages may be supplied to and across the length of a gate electrode. Further, the same voltage may be supplied to each of the electrically isolated regions. The planar and recessed access devices may be turned into an “on” state or an “off” state depending upon the voltages supplied by the different voltage supplies.

The electrically isolated regions allow different margin biases to be supplied to different portions of the gate electrode, which in turn may be used to control gate induced drain leakage in the planar or recessed access device. In addition, the voltages supplied to the electrically isolated regions during the “on” state and “off” state may be altered to control the subthreshold leakage and junction leakage of the planar or recessed access device. In this manner, the gate induced drain leakage may be controlled or reduced without sacrificing losses to subthreshold leakage and junction leakage.

According to still other embodiments of the invention, a planar or recessed access device may include a gate electrode having a cathode region and an anode region, wherein the cathode and anode form a diode in the gate electrode. Each of the cathode and anode may be connected to separate voltage supplies such that different or similar voltages may be supplied to and across the length of the gate electrode. The voltages supplied to the anode and cathode may be tailored such that when the gate stack or recessed access device is in an “off” state the gate induced drain leakage is minimized. The margin bias provided across the diode may also be used to minimize the subthreshold leakage and junction leakage.

In still other embodiments of the invention, an access device driver is provided, wherein the access device driver may supply two or more voltages to a planar or recessed access device. Access device drivers according to embodiments of the invention may be able to provide dissimilar or similar voltages to a planar or recessed access device having two or more electrically isolated regions in a gate electrode or to a gate electrode comprising a diode. The control of voltages to the planar or recessed access device by the access device driver may facilitate the control of the gate induced drain leakage, subthreshold leakage, and junction leakage of a planar or recessed access device.

According to embodiments of the invention, an access device of a memory cell includes one or more gates in a memory or semiconductor device that are capable of reducing an amount of gate induced drain leakage (GIDL) in the access device. An access device may include a gate electrode or gate diode capable of accepting two voltages simultaneously. In other embodiments, the access device may include gate electrodes comprising two or more materials having different work functions.

According to some embodiments of the invention, gate-induced drain leakage may be reduced by forming an access device or transistor gate stack from materials having differing work functions. For example, an access device or gate stack may be formed from two or more materials having dissimilar work functions. A material having a higher work function may be used to form those portions of the gate stack where sub-threshold leakage is problematic while a material having a lower work function may be used to form those portions of the gate stack where gate-induced drain leakage is a concern. For example, a gate stack having two or more gate materials may be formed such that a gate material closest to a storage capacitor has a lower work function than the gate material closest to the bitline of a memory device. The dissimilar work function materials may be separated by a barrier layer and strapped together by a metal or conductive strap. The barrier layer may comprise a conductive material and may serve as a conductive strap.

Unlike conventional planar access devices which employ a material having a consistent work function to form a gate electrode or gate stack of an access device, embodiments of the present invention may employ one or more materials in the gate stack of an access device to decrease or control GIDL. For example, access devices according to embodiments of the invention may be used in semiconductor devices as planar access devices or transistors incorporated with memory devices. Embodiments of the invention are especially useful in memory devices such as in dynamic random access memory (DRAM) devices but are not limited to such use.

An access device 100 according to embodiments of the invention is illustrated in FIG. 3. The access device 100 may include one or more gate stacks 120 formed over a semiconductor substrate 110. Gate stacks 120 may include an oxide layer 121 and a gate electrode over the oxide layer. The gate electrode may include a first gate material 122 having a first work function associated therewith and a second gate material 124 having a second work function associated therewith. As illustrated in FIG. 3, the gate materials may be separated by a barrier layer 123. One or more straps 126 may overlie the first gate material 122 and second gate material 124. The straps 126 may provide an electrical connection between the first and second gate materials. A gate stack 120 may also include an insulator cap 130 and sidewall spacers 128 as known and used with conventional planar access devices. The gate stacks 120 may overlie source and drain regions 112 in the semiconductor substrate 110.

The semiconductor substrate 110 may include semiconductor substrates conventionally used with or for the fabrication of memory devices, access devices, and other semiconductor devices. In many embodiments, the semiconductor substrate 110 may include a silicon-containing structure such as silicon, silicon-on-insulator structures, and silicon-on-sapphire structures.

Oxide layer 121 may include any oxide material that may be used to form oxide layers 121 capable of being used with conventional gate stacks devices and particularly with gate stacks or other transistor devices integrated with memory devices or semiconductor devices.

The gate electrodes of embodiments of the invention may include multiple gate materials. As illustrated in FIG. 3, a gate electrode may include a first gate material 122 and a second gate material 124. Preferably, the first gate material 122 and the second gate material 124 have differing work functions. Use of gate materials having differing work functions to form the gate electrodes may reduce the effects of gate induced drain leakage (GIDL) in the access device 100. For example, the first gate material 122 of the gate stack 120 illustrated in FIG. 3 may include an N+ doped polysilicon material and the second gate material 124 may include a P+ doped polysilicon material. The N+ doping of the first gate material 122 provides the first gate material 122 with a lower work function than the P+ doped material of the second gate material 124. The P+ second gate material 124 maintains a high threshold voltage Vt for the access device 100, thereby reducing the subthreshold leakage while the N+ first gate material 122 decreases the GIDL in the access device 100.

Although embodiments of the invention have been described having two gate materials it is understood that the gate electrodes may be formed of two or more gate materials. For example, a gate electrode may include gate materials having differing work functions in a horizontal cross-section of the gate electrode as illustrated in FIG. 3 as well as differing work functions in a vertical cross-section of the gate electrode. The first gate material, for example, may include a varying work function across a vertical cross-section from the oxide layer 121 to the insulator cap 130. Similarly, the second gate material 124 may include a varying work function across a vertical cross-section from the oxide layer 121 to the insulator cap 130.

A separator 123 may be positioned between the first gate material 122 and the second gate material 124 and may include insulating materials, conductive materials, metals, or other materials capable of separating the gate materials. For example, separator 123 may be formed of a nitride, an oxide, silicide, a conductive metal, or a metallic alloy. In some embodiments, the separator 123 may prevent cross-diffusion of the first gate material 122 with the second gate material 124 or prevent cross-diffusion of dopants between the gate materials, especially during subsequent heating processes utilized in the fabrication of a semiconductor device.

In some embodiments, the strap 126 may be a conductive strap providing an electrical connection between the first gate material 122 and the second gate material 124. Exemplary materials that may be used as a conductive strap 126 include metals, as well as conductive silicon materials, doped silicon materials including conductively doped polycrystalline silicon, and other conductors. In other embodiments, the strap 126 need not be conductive. For instance, if the separator 123 provides an electrical connection between the first gate material 122 and the second gate material 124, the strap 126 may not provide an electrical connection between the gate materials. In those embodiments where such an electrical connection between the first gate material 122 and the second gate material 124 exists, a conductive strap 126 is not necessary but may be used.

The insulator cap 130 of the gate stacks 120 may include any insulating material that may be used as an insulating layer for conventional planar devices. For instance, the insulator cap 130 may be formed of a nitride or an oxide, such as silicon dioxide.

Similarly, the sidewall spacers 128 may be formed from materials used to form spacers 128 with conventional gate stack devices and access devices 100. For example, the spacers 128 may include materials such as silicon dioxide or other oxides, silicon nitride, or other nitrides, or silicon oxynitride.

The gate stacks 120 of embodiments of the invention may be produced using fabrication processes used to form conventional semiconductor devices and particularly memory devices. For example, the gate stacks illustrated in FIG. 3 may be formed using conventional CMOS or memory device fabrication processes as illustrated in FIGS. 4A-4E. As illustrated in FIG. 4A, a polysilicon layer 122A may be deposited over a gate oxide layer 121 overlying a semiconductor substrate 110. The polysilicon layer 122A may then be masked and etched according to conventional processes to form the first gate material 122 of the gate stack 120 as illustrated in FIG. 4B. A separator layer 123A may be deposited over the first gate material 122 and the semiconductor substrate 110. Etching of the separator layer 123A leaves the separator 123 formed on the sides of the first gate material 122. A second polysilicon material 124A may be deposited over the first gate material 122, the separator 123, and the semiconductor substrate 110 as illustrated in FIG. 4C. Masking and etching of the second polysilicon material 124A may result in the formation of the second gate material 124 of the gate stacks 120 as illustrated in FIG. 4D. A strap material 126A deposited over the first gate material 122, separator 123, and second gate material 124 as illustrated in FIG. 4D may be masked and etched to form the strap 126 illustrated in FIG. 4E. Conventional masking, etching, doping, and deposition processes may be used to complete the formation of the gate stacks 120 including the formation of the insulator caps 130 and sidewall spacers 128, and the doping of the active areas 112.

Although methods for forming the gate stacks 120 of particular embodiments of the invention are illustrated in FIGS. 4A-4E, it is understood that other methods and processes may also be used to fabricate gate stacks 120 according to embodiments of the invention. In addition, it is understood that the order of formation of the first gate material 122, separator 123, and second gate material 124 is only exemplary. The gate materials 122 and 124, and the separator 123, may be formed in any desired order. Furthermore, the first gate material 122 and the second gate material 124 may be formed simultaneously out of the same polysilicon material. Subsequent doping of the first gate material 122 and second gate material 124 may establish a desired difference in work function of the two materials. In addition, the oxide layer 121 overlying the semiconductor substrate 110 may be a continuous oxide layer (not shown) which may be etched or otherwise removed during the fabrication process.

According to other embodiments of the invention, an access device 150 may include one or more recessed access device (RAD) structures 170 wherein the RAD structures 170 include two or more materials having different work functions. For example, exemplary RAD structures 170 according to embodiments of the invention are illustrated in FIG. 5.

The RAD structures 170 may be formed in trenches of a semiconductor substrate 160 between active areas 162 such as source and drain regions or bitlines and storage capacitors for memory devices. The trenches in the semiconductor substrate 160 may be lined with a gate-oxide 171 as used with conventional RAD structures. The RAD structures 170 may include a first gate material 172 overlying a second gate material 174 in a trench of the semiconductor substrate 160. The first gate material 172 and the second gate material 174 may be separated by a metal barrier 173 or other conductive barrier as illustrated in FIG. 5. The RAD structures 170 may also include a strap 176 overlying the first gate material 172 and an insulator cap 180 overlying the strap 176. Gate electrode sidewall spacers 178 may also be formed with the RAD structures 170 to complete the trenched gate stack 170.

According to embodiments of the invention, the second gate material 174 of the RAD structures 170 may be formed of a material having a higher work function than the first gate material 172. For example, the second gate material 174 used to form the RAD structures 170 illustrated in FIG. 5 may include a P+ doped polysilicon material and the first gate material 172 may include an N+ doped polysilicon material. Other materials having differing work functions may also be used to form RAD structures 170 according to embodiments of the invention.

The metal barrier 173 between the first gate material 172 and the second gate material 174 may provide an ohmic contact between the two gate materials. The metal barrier 173 may include metals such as tungsten, aluminum, copper, or titanium. In some embodiments, the metal barrier 173 may be formed from one or more metal layers. The metal layers may include similar or dissimilar metals. In other embodiments, the metal barrier 173 may be substituted with a barrier material (not shown) that may provide an electrical connection or conduction between the first gate material 172 and the second gate material 174. In addition, the barrier material may prevent diffusion of dopants between the two gate materials. The barrier layer may also be an insulator or may include layers of conductors, conductors and insulators, or insulators.

In some embodiments, the strap 176 may be a conductive material, such as a metal, a conductive silicon material, a doped silicon material, or another conductor. In other embodiments, the strap 176 need not be conductive.

The insulator cap 180 of the RAD structures 170 may include any insulating material that may be used as an insulating layer for conventional planar or recessed access devices. For instance, the insulator cap 180 may be formed of a nitride or an oxide such as silicon dioxide.

Similarly, the sidewall spacers 178 may be formed from materials used to form spacers 178 with conventional planar or recessed access devices. For example, the sidewall spacers 178 may include materials such as silicon dioxide or other oxides, silicon nitride, or other nitrides, or silicon oxynitride.

The RAD structures 170 of embodiments of the invention may be produced using fabrication processes used to form conventional semiconductor devices and particularly memory devices. For example, the RAD structures 170 illustrated in FIG. 5 may be formed using conventional CMOS or memory device fabrication processes similar to the steps illustrated in FIGS. 6A-6E. As illustrated in FIG. 6A, a semiconductor substrate 160 having trenches formed therein may be provided. Oxide 171 may be grown in the trenches as used with conventional RAD structures. A polysilicon layer 174A may be deposited over the semiconductor substrate 160 and in the trenches. Masking and/or etching of the polysilicon layer 174A may be performed to form the second gate material 174 in the bottoms of the trenches of the semiconductor substrate 160 as illustrated in FIG. 6B. A barrier layer 173A may be deposited over the second gate material 174 and the semiconductor substrate 160. Masking and/or etching of the barrier layer 173A may form the metal barrier 173 over the second gate material 174 in the bottom of the trenches as illustrated in FIG. 6C. A second polysilicon layer 172A may be deposited over the semiconductor substrate 160 and in the trenches over the metal barrier 173 as illustrated in FIG. 6C. Masking and/or etching of the second polysilicon layer 172A may form the first gate material 172 as illustrated in FIG. 6D. The masking and/or etching of the second polysilicon layer 172A may be performed such that a portion of the first gate material 172 extends above a surface of the semiconductor substrate 160. A strap material 176A deposited over the first gate material 172 may be masked and/or etched to form the strap 176 over the first gate material 172 as illustrated in FIG. 6E. Conventional masking, etching, doping, and deposition processes may be used to complete the formation of the RAD structures 170, including the formation of insulator caps 180 and sidewall spacers 178, and the doping of the active areas 162.

Although methods for forming the RAD structures 170 of particular embodiments of the invention are illustrated in FIGS. 6A-6E, it is understood that other methods and processes may also be used to fabricate RAD structures 170 according to embodiments of the invention.

When employed with access devices, such as memory devices or other semiconductor devices, the gate stacks 120 and RAD structures 170 of embodiments of the invention may reduce GIDL, reduce junction leakage, reduce subthreshold leakage, and increase the drive of the access device. The combination of multiple work functions in the gate electrodes of the gate stack 120 and RAD structures 170 allows sub-threshold leakage to be controlled or reduced using a high work function material while also employing a low work function material to reduce GIDL. The increased margin to GIDL provided by the dual work function gate electrode allows the negative access device bias to be pushed more negative, which in turn may reduce the subthreshold leakage. The decreased subthreshold leakage may allow a less negative substrate bias to be used with embodiments of the invention to decrease junction leakage and increase the drive of the access device.

According to other embodiments of the invention, an access device 150′. having one or more RAD structures 170′ with two or more materials having different work functions may include a RAD structure 170′ having a first gate material 172′ positioned along at least a portion of the sidewalls of the RAD structure 170′ and a second gate material 174′ at least partially surrounded by the first gate material 172′ as illustrated in FIG. 7A. As with other embodiments of the invention, trenches in the semiconductor substrate 160′ may include a gate-oxide 171′ layer on the sidewalls of the trenches. The first gate material 172′ may be positioned along at least a portion of the gate-oxide 171′ layer and the second gate material 174′ may be positioned with respect to the first gate material 172′ as illustrated. A barrier layer (not shown) may be formed between the first gate material 172′ and the second gate material 174′. The RAD structures 170′ may also include a strap 176′ overlying the first gate material 172′ and second gate material 174′ and an insulator cap 180′ overlying the strap 176′. Gate electrode sidewall spacers 178′ may also be formed with the RAD structures 170′ to complete the trenched gate stack 170′.

According to embodiments of the invention, the second gate material 174′ of the RAD structures 170′ may be formed of a material having a higher work function than the first gate material 172′. For example, the second gate material 174′ used to form the RAD structures 170′ illustrated in FIG. 7A may include a p-doped polysilicon material and the first gate material 172′ may include an n-doped polysilicon material. Other materials having differing work functions may also be used to form RAD structures 170′ according to embodiments of the invention.

The RAD structures 170′ of embodiments of the invention may be produced using fabrication processes used to form conventional semiconductor devices and particularly memory devices. For example, the RAD structures 170′ illustrated in FIG. 7A may be formed using conventional CMOS or memory device fabrication processes similar to the steps illustrated in FIGS. 7B-7D. As illustrated in FIG. 7B, a semiconductor substrate 160′ having trenches formed therein may be provided. Oxide 171′ may be grown in the trenches as used with conventional RAD structures. A polysilicon layer 172A′ may be deposited over the semiconductor substrate 160′ and in the trenches. The polysilicon layer 172A′ may be doped n-type according to conventional doping techniques. An isotropic spacer etch selective to the oxide 171′ may be performed to remove the polysilicon layer 172A′ in the bottom of a trench, leaving the n-doped polysilicon layer 172′ on the sidewalls of the trench as illustrated in FIG. 7C. A second gate material layer 174A′ formed of a material having a higher work function than the first gate material 172′ may be deposited over the substrate 160′ and in the trenches as illustrated in FIG. 7C. Masking and/or etching of the second gate material layer 174A′ may be used to form the second gate material 174′ as illustrated in FIG. 7D. Conventional masking, etching, doping, and deposition processes may be used to complete the formation of a RAD structure 170′, including the formation of a strap 176′, formation of insulator caps 180′, and formation of sidewall spacers 178′ as illustrated in FIG. 7A.

Although methods for forming the RAD structures 170′ of particular embodiments of the invention are illustrated in FIGS. 7B-7D, it is understood that other methods and processes may also be used to fabricate RAD structures 170′ according to embodiments of the invention.

When employed with access devices, such as memory devices or other semiconductor devices, the RAD structures 170′ of embodiments of the invention may reduce GIDL, reduce junction leakage, reduce subthreshold leakage, and increase the drive of the access device. The combination of multiple work functions in the gate electrodes allows sub-threshold leakage to be controlled or reduced using a high work function material while also employing a low work function material to reduce GIDL. The increased margin to GIDL provided by the dual work function gate electrode allows the negative access device bias to be pushed more negative, which in turn may reduce the subthreshold leakage. The decreased subthreshold leakage may allow a less negative substrate bias to be used with embodiments of the invention to decrease junction leakage and increase the drive of the access device.

Although the multi-workfunction RAD structures according to embodiments of the invention have been described with respect to conventional RAD structure configurations, it is also understood that embodiments of the invention may be incorporated with spherical recessed access devices (SRAD) as well. For example, an SRAD structure according to embodiments of the invention is illustrated in FIG. 7E. The SRAD structure 170′ illustrated in FIG. 7E may include the same characteristics as a RAD structure and may be formed using similar processes.

According to other embodiments of the invention, a gate electrode in an access device may be separated into two or more electrically isolated regions. The two or more electrically isolated regions may be connected to an access device driver capable of supplying the same or different voltages to each of the two or more electrically isolated regions.

An example of an access device 200 incorporating a gate electrode having two or more electrically isolated regions according to embodiments of the invention is illustrated in FIG. 8. The access device 200 may include one or more gate stacks 220 formed over a semiconductor substrate 210. The gate stacks 220 may be positioned next to or over active areas 212 in the semiconductor substrate 210 just as conventional gate stacks are positioned with conventional planar access devices. The gate stacks 220 may include a gate electrode overlying an oxide layer 241. The gate electrode may include a first gate material 242 and a second gate material 244 separated by an insulator layer 243. An insulator cap 246 may overlie the first gate material 242, the second gate material 244, and the insulator layer 243. The gate stack 220 may also include sidewall spacers 248 as known and used with conventional planar access device structures.

Gate stacks 220 according to embodiments of the present invention may be incorporated with access devices 200 such as memory devices, CMOS structures, or other devices and structures where conventional gate stacks may be used.

The semiconductor substrate 210 may include semiconductor substrates conventionally used with or for the fabrication of memory devices, access devices, and other semiconductor devices. In many embodiments, the semiconductor substrate 210 may include one or more silicon-containing structures such as silicon wafers, silicon-on-insulator structures, or silicon-on-sapphire structures. The active areas 212 of the semiconductor substrate 210 may be doped with an n-type, p-type, or other type dopant similar to active areas associated with conventional gate stack formations.

The first gate material 242 and the second gate material 244 of a gate stack 220 may be formed of the same material, such as polysilicon. In other embodiments, the first gate material 242 and the second gate material 244 may be formed of different materials or they may be formed of the same material but doped with different dopants to alter the characteristics of the gate materials. Although the gate stack 220 illustrated in FIG. 8 illustrate gate stacks 220 having two gate electrode regions—the first gate material 242 defining a first region and the second gate material 244 defining a second region—it is understood that two or more regions may be defined and incorporated with embodiments of the present invention. In such instances, two or more gate material regions may be separated by two or more insulator layers 243 positioned in the gate material regions.

The insulator layer 243 positioned between the first gate material 242 and the second gate material 244 may include any dielectric layer or suitable material capable of acting as an insulator between the two gate materials. For example, the insulator layer 243 may include a layer of silicon nitride (SiN), silicon dioxide (SiO2), or other similar insulating material.

Insulator caps 246 and sidewall spacers 248 are used with conventional planar access devices and the insulator caps 246 and sidewall spacers 248 incorporated with the gate stacks 220 of various embodiments of the invention may include conventional insulator caps and sidewall spacers formed according to conventional fabrication processes.

The gate stacks 220 according to embodiments of the invention may be formed using conventional gate stack fabrication processes, with the formation of the second gate material 244 and the insulator layer 243 being added to such processes. For example, processes that may be used for the fabrication of the gate stack 220 illustrated in FIG. 8 are illustrated in FIGS. 9A-9D. As illustrated in FIG. 9A, a polysilicon layer 242A may be deposited over a gate-oxide layer 241 overlying a semiconductor substrate 210. The polysilicon layer 242A may be masked and etched such that one or more first gate material 242 formations remain positioned over the oxide layer 241 as illustrated in FIG. 9B. An insulator layer 243A may be deposited over the first gate material 242 formations. The insulator layer 243A may be etched to remove all but the insulator layer 243 portions next to the first gate material 242 formations as illustrated in FIG. 9C. For example, a vertical isotropic etch may be used to etch the insulator layer 243A such that only insulator layer 243 remains on the sides of the first gate material 242. A second polysilicon layer 244A may be formed over the structure as illustrated in FIG. 9C. The second polysilicon layer 244A may be masked and etched to form the second gate material 244 formations as illustrated in FIG. 9D. Conventional masking, etching, doping, and deposition processes may be used to complete the formation of the gate stack 220 including the formation of the insulator caps 246 and sidewall spacers 248, and the doping of the active areas 212.

Although the fabrication processes illustrated in FIGS. 9A-9D show an oxide layer formed over the semiconductor substrate 210 it is understood that the oxide layer 241 may include a continuous oxide layer (not shown) across the expanse of the semiconductor substrate 210 that may be etched to the desired form during the processing steps. For example, a continuous oxide layer (not shown) may be deposited across the entire portion of a semiconductor substrate 210 where a gate stack 220 is to be formed. The components of the gate stack such as the first gate material 242, insulator layer 243, second gate material 244, and insulator cap 246 may be formed over the continuous oxide layer. The gate stack 220 and the continuous oxide layer may then be etched to form the structures illustrated in FIG. 9D.

Although methods for forming the gate stack 220 of the invention are described with respect to FIGS. 9A-9D, it is understood that other methods and processes may also be used to fabricate the gate stack 220 of the invention and that embodiments of the invention are not limited by the fabrication processes described.

The gate stacks 220 according to embodiments of the invention may be driven by an access device driver capable of providing two or more voltages to the different electrically isolated regions of the gate stacks 220 simultaneously. For instance, the gate stacks 220 illustrated in FIG. 8 may be driven by a access device driver capable of supplying a first voltage to the first gate material 242 and a second voltage to the second gate material 244. The voltages supplied by the access device driver may be selected such that the voltages applied to the first gate material 242 and the second gate material 244 are the same or different, depending on the desired “on” or “off” state of the gate stack 220.

In some embodiments, a gate stack 220 may include two or more gate materials. In such instances, an access device driver may be adapted to deliver voltages to each of the gate materials to control the operations of the gate stack 220.

According to other embodiments of the invention, a RAD structure 270 may be incorporated into an access device 250. A RAD structure 270 according to embodiments of the invention may be similar to a conventional RAD structure having a single gate material. The RAD structures 270 of particular embodiments of the invention, however, may include a first gate material 272 and a second gate material 274 separated by an insulator layer 273. For example, a RAD structure 270 according to particular embodiments of the invention is illustrated in FIG. 10.

The RAD structure 270 illustrated in FIG. 10 includes two gate materials, a first gate material 272 and a second gate material 274, positioned in a trench in a semiconductor substrate 210. A gate oxide layer 271 may coat or overlie the sides of the trench in the semiconductor substrate 210. The first gate material 272 and the second gate material 274 may be separated by an insulator layer 273. The RAD structures 270 may be positioned next to or over active areas 262 in the semiconductor substrate 210 just as RAD structures are positioned with conventional access devices. An insulator cap 276 may overlie the gate materials of a RAD structure 270 and sidewall spacers 278 may border the sides of the RAD structure 270 as illustrated in FIG. 10. The insulator cap 276 and sidewall spacers 278 may be similar to insulator caps and sidewall spacers employed with conventional RAD devices.

Although the RAD structure 270 illustrated in FIG. 10 shows a first gate material 272 and a second gate material 274 separated by an insulator layer 273, embodiments of the invention may include two or more gate materials separated by two or more insulator layers.

RAD structures 270 according to embodiments of the invention may be incorporated with access devices 250 such as memory devices, CMOS structures, or other devices and structures where RAD structures 270 may be used.

Semiconductor substrates 210 may include semiconductor substrates conventionally used with or for the fabrication of memory devices, access devices, and other semiconductor devices. In many embodiments, the semiconductor substrate 210 may include one or more silicon-containing structures such as silicon wafers, silicon-on-insulator structures, or silicon-on-sapphire structures. The active areas 262 of the semiconductor substrate 210 may be doped with an n-type, p-type, or other type dopant similar to active areas associated with conventional RAD structure formations.

The gate materials forming the first gate material 272 and the second gate material 274 may include materials used to form conventional gate electrodes. For example, the gate materials used with the RAD structures 270 according to embodiments of the invention may include materials such as polysilicon materials. The same gate material may be used to form the first gate material 272 and the second gate material 274 or the two gate materials may be formed from different gate materials. In other embodiments, the first gate material 272 and the second gate material 274 may be doped with different dopants to alter the characteristics of the gate materials.

The insulator layer 273 positioned between the first gate material 272 and the second gate material 274 may include any dielectric layer or suitable material capable of acting as an insulator between the two gate materials. For example, the insulator layer 273 may include a layer of silicon nitride (Si3N4), silicon dioxide (SiO2), or other similar insulating material.

The RAD structures 270 according to embodiments of the invention may be formed using conventional RAD structure fabrication processes. For example, a process that may be used to fabricate a RAD structure according to embodiments of the invention is illustrated in FIGS. 11A-11D.

RAD structures 270 according to embodiments of the invention may be formed in a trench in a semiconductor device wherein the trench includes a gate-oxide layer as may be fabricated for conventional RAD structures. As illustrated in FIG. 11A, a polysilicon layer 272A may be deposited over a semiconductor substrate 210 having trenches lined with a gate oxide 271 material. The polysilicon layer 272A may be etched, leaving a first gate material 272 deposited over the gate oxide layer 271 in the bottom of a trench as illustrated in FIG. 11B. An insulator material layer 273A deposited over the first gate material 272 and the gate oxide layer 271 may be etched to form the insulator layer 273 over the first gate material 272. The etching of the insulator material layer 273A may be performed so that the gate oxide layer 271 remains on the surface of the trenches in the semiconductor substrate 210. A second polysilicon layer 274A may be deposited over the semiconductor substrate 210 and in the trenches, covering the insulator layer 273 and filling the trenches as illustrated in FIG. 11C. Selective masking and etching of the second polysilicon layer 274A forms the second gate material 274 formations as illustrated in FIG. 11D.

Conventional masking, etching, doping, and deposition processes may be used to complete the formation of the RAD structures 270 including the formation of the insulator caps 276 and sidewall spacers 278, and the doping of the active areas 262. In addition, masking of the trenches, contacts between RAD structures, and metal layers above the RAD structures may be performed such that contact may be made to the bottom portion of the RAD structure 270, and the first gate material 272, as well as to the top portion of the RAD structure 270 and the second gate material 274. The contact may be connected to an access device driver capable of supplying desired voltages to the first gate material 272 and second gate material 274.

Although methods for fabricating RAD structures 270 of the invention are described with respect to FIGS. 11A-11D, it is understood that other methods and processes may also be used to fabricate the RAD structures 270 of the invention and that embodiments of the invention are not limited by the fabrication processes described.

The RAD structures 270 according to embodiments of the invention may be driven by an access device driver capable of providing two or more voltages to the RAD structure 270 simultaneously. For example, the RAD structure 270 illustrated in FIG. 10 may be driven by an access device driver capable of supplying a first voltage to the first gate material 272 and a second voltage to the second gate material 274. The voltages supplied by the access device driver may be selected such that the voltages applied to the first gate material 272 and the second gate material 274 are the same or different, depending on the desired “on” or “off” state of the RAD structure 270.

In some embodiments, the RAD structures 270 may include two or more gate materials. In such instances, an access device driver may be adapted to deliver voltages to each of the gate materials to control the operations of the RAD structures 270.

The gate stacks 220 and RAD structures 270 having multiple electrically isolated regions according to embodiments of the invention may reduce the amount of gate induced drain leakage (GIDL), junction leakage, and subthreshold leakage while increasing the drive of the access device. The gate stacks 220 and RAD structures 270 reduce the amount of GIDL while preserving a negative gate electrode bias. This may be accomplished by applying different voltages to the first and second gate electrodes of the gate stacks 220 and RAD structures 270. Therefore, in the “off” state, one of the negative gate electrode bias may be made more negative while the other remains “off,” but at a less negative bias—thereby decreasing GIDL current. The more negative word line bias on one portion of the gate results in decreased subthreshold leakage. Further, a less negative substrate bias may be used, which would decrease junction leakage and increase the drive of the access device.

According to still other embodiments of the invention, planar or recessed access devices may also include gate electrodes comprised of diodes. The incorporation of a diode structure with the gate electrode would allow two voltages to be applied to the electrode structure: a first voltage across the anode of the diode and a second voltage across the cathode of the diode.

An access device 300 utilizing a gate stack 320 constructed of a diode according to embodiments of the invention is illustrated in FIG. 14. The access device 300 may include one or more gate stacks 320 formed over a semiconductor substrate 310. The gate stacks 320 maybe positioned next to or over active areas such as storage capacitors 312 and bitline contacts 313 in the semiconductor substrate 310 just as conventional gate stacks are positioned with conventional access devices. The gate stacks 320 may include a gate electrode overlying an oxide layer 321, wherein the gate electrode comprises an anode 324 and a cathode 322. The anode 324 may be positioned closest to a bitline contact 313 active area while the cathode 322 may be positioned closest to the storage capacitor 312 active areas. An insulator cap 330 may overlie the gate electrode and sidewall spacers 328 may be positioned on the sides of the gate stack 320 in a manner similar to conventional gate stacks.

The gate stacks 320 may be incorporated with access devices 300 such as memory devices, CMOS structures, or other devices and structures where gate stacks 320 may be used.

The semiconductor substrate 310 may include semiconductor substrates conventionally used with or for the fabrication of memory devices, access devices, and other semiconductor devices. In many embodiments, the semiconductor substrate 310 may include, but is not limited to, one or more silicon containing materials such as silicon, silicon-on-insulator structures, or silicon-on-sapphire structures. The bitline contacts 313 and storage capacitor 312 of the semiconductor substrate 310 may be doped with an n-type, p-type, or other type dopant to form the desired active areas, which are similar to those formed in conventional gate stack formations.

The insulator caps 330 and sidewall spacers 328 may include materials used to form the insulator caps and sidewall spacers of conventional gate stack devices.

The anode 324 of the gate stack 320 may be formed of materials conventionally used to form anodes in semiconductor devices. The anode 324 may also be formed of a doped material such as a p-type doped material. In some embodiments, the anode 324 may be formed of a Ruthenium-Tantalum (RuxTay) metal alloy or a tantalum nitride (TaN) metal alloy.

The cathode 322 of the gate stack 320 may be formed of materials conventionally used to form cathodes in semiconductor devices. The cathode 322 may also be formed of a doped material such as an n-type doped material. In some embodiments, the cathode 322 may be formed of a Ruthenium-Tantalum (RuxTay) metal alloy or a tantalum nitride (TaN) metal alloy.

According to some embodiments of the invention, a gate stack 320 of an access device 300, such as the gate stack 320 illustrated in FIG. 14, may be fabricated according to the steps illustrated in FIGS. 15A- 15D. The gate stacks 320 of embodiments of the present invention may be formed over semiconductor substrates 310 having oxide layers 321 formed thereon as with a conventional gate stack fabrication method. The oxide layer 321 may be a discontinuous oxide layer 321 as illustrated in FIG. 15A or a continuous oxide layer which is etched or otherwise partially removed to form the oxide layer 321 illustrated in FIG. 15A. As illustrated in FIG. 15A, an anode material 324A may be deposited over a semiconductor substrate 310 having oxide layers 321. The anode material 324A may be masked and etched according to conventional techniques to form anode 324 portions of the gate stack 320 as illustrated in FIG. 15B. A cathode material 322A may be deposited over the anode 324 portions of the gate stack 320 as well as the semiconductor substrate 310 having oxide layers 321 as illustrated in FIG. 15C. The cathode material 322A and anode portions may be masked and etched to form the anode 324 and cathode 322 diode structures of the gate stacks 320 as illustrated in FIG. 15D. Conventional gate stack fabrication techniques may then be used to form the insulator cap 330 and sidewall spacers 328, completing the formation of the gate stacks 320. The active areas in the semiconductor substrate 310, such as the bitline contacts 313 and storage capacitors 312, may also be formed using conventional methods of fabrication. For example, the bitline contacts 313 and the storage capacitors 312 may be doped with an n-type dopant to form N+ doped active areas.

Although the anode 324 portions of the gate stacks 320 illustrated in FIGS. 15A-15D are shown as being fabricated before the cathode 322 portions of the gate stacks 320, it is understood that the order of formation of the cathode 322 portions and anode 324 portions is not critical. Therefore, the cathode 322 portions may be formed before the anode 324 portions according to embodiments of the invention.

In addition, after the initial formation of the anode 324 portions and cathode 322 portions of the gate electrode, the structures may be masked, etched, polished, or otherwise formed such that the center of the gate stack 320 is positioned at the interface of the anode 324 portions and the cathode portions 322 of the gate stack. For instance, chemical mechanical planarization (CMP) processes may be used to form the gate stack 320 to the desired height and masking and etching processes may be used to ensure that the center of the gate stack 320 structure is located at the boundary of the anode 324 and the cathode 322.

According to embodiments of the invention, the anode material 324A and cathode material 322A may be selected such that the work function of the two materials is different. For example, in some embodiments the cathode material 322A and anode material 324A may each comprise Ruthenium-Tantalum which may be represented by the chemical formula RuxTay wherein x and y may be selected according to the desired work functions for the diode. For example, the anode 324 may be formed of an RuxTay material wherein x and y are selected such that the anode 324 exhibits a work function of about 5.0 eV. The cathode 322 may be formed of an RuxTay material wherein x and y are selected such that the cathode 322 exhibits a work function of about 4.2 eV. Other values of x and y may be selected such that the work functions of the two materials is different.

The gate stacks 320 according to embodiments of the invention may be formed as one long diode having approximately equal cathode 322 and anode 324 regions within the gate stack 320. The anode 324 regions may be positioned closest to the bitline contacts 313 while the cathode 322 regions may be positioned closest to the storage capacitors 312. In an “off” state, the anode 324 of a gate stack 320 is held at a negative word line voltage while the cathode 322 is held at a higher voltage than the anode 324. The difference in voltages between the cathode 322 and anode 324 creates a reverse bias across the diode. The bias level of the cathode 322 may be determined by the breakdown voltage of the reversed biased diode gate. The cathode 322 region bias level may decrease the voltage difference between the storage capacitors 312 and the gate stack 320, which in turn may decrease the electric field in the gate stack 320 area. The decreased electric field in the gate stack 320 area may help to reduce the gate-induced drain leakage in a gate stack 320 formed according to embodiments of the invention. In an “on” state, the anode 324 and the cathode 322 of the gate electrode or gate stack 320 are both driven to the same positive level as with conventional gate stack devices.

In still other embodiments of the invention, the diode of the gate stacks 320 may include a Schottky-Barrier type diode. In such instances, the anode 324 may be a metal layer and the cathode 322 may be a polysilicon material that is doped, for example a polysilicon material that is slightly doped N+. Embodiments of the invention may also include gate stacks 320 formed of Schottky-Barrier type diodes.

In other embodiments of the invention, an access device 350 may include one or more recessed access device (RAD) structures 370 comprising diodes as illustrated in FIG. 16. The RAD structures 370 may include a diode comprised of an anode 374 and a cathode 372 formed in a trench in a semiconductor substrate 360. The anode 374 may be formed in the bottom of a trench and the cathode 372 may lie on top of the anode 374 and may extend beyond the surface of the semiconductor substrate 360. The RAD structures 370 may be positioned in trenches in a semiconductor substrate 360 just as conventional RAD structures are positioned. The trenches in the semiconductor substrate 360 may be lined with oxide 371 layers such that the cathode 372 and anode 374 may be in contact with the oxide 371 layer rather than a wall of a trench. The RAD structures 370 may also include an insulator cap 376 and sidewall spacers 378 similar to those used with conventional RAD structures.

The RAD structures 370 may be incorporated with access devices 350 such as memory devices, CMOS structures, or other conventional devices and structures employing the use of RAD structures 370.

The semiconductor substrate 360 may include semiconductor substrates conventionally used with or for the fabrication of memory devices, access devices, and other semiconductor devices. In many embodiments, the semiconductor substrate 360 may include one or more silicon-containing structures such as silicon wafers, silicon-on-insulator structures, or silicon-on-sapphire structures. The bitline contacts 363 and storage capacitors 362 of the semiconductor substrate 360 may be doped with an n-type, p-type, or other type dopant to form the desired active areas, which are similar to those formed with conventional RAD structure formations.

The insulator caps 376 and sidewall spacers 378 may include materials used to form the insulator caps and sidewall spacers of conventional gate stack devices.

The anode 374 of the RAD structure 370 may be formed of materials conventionally used to form anodes in semiconductor devices. The anode 374 may also be formed of a doped material such as a p-type doped material. In some embodiments, the anode 374 may be formed of a Ruthenium-Tantalum (RuxTay) metal alloy or a tantalum nitride (TaN) metal alloy.

The cathode 372 of the RAD structure 370 may be formed of materials conventionally used to form cathodes in semiconductor devices. The cathode 372 may also be formed of a doped material such as an n-type doped material. In some embodiments, the cathode 372 may be formed of a Ruthenium-Tantalum (RuxTay) metal alloy or a tantalum nitride (TaN) metal alloy.

According to some embodiments of the invention, a RAD structure 370, such as that illustrated in FIG. 16, may be fabricated according to the processes illustrated in FIGS. 17A-17D. A RAD structure 370 may be fabricated in the trenches of a simiconductor substrate 360 as with conventional RAD structures. The trenches may include an oxide 371 layer, such as a gate oxide layer, covering the surfaces of the trenches. As illustrated in FIG. 17A, an anode material 374A may be deposited over and in an oxide 371 layered trench in a semiconductor substrate 360. The anode material 374A may then be masked and etched according to conventional processes to leave a portion of the anode material 374A in the trenches which forms the anode 374 of the RAD structure 370 as illustrated in FIG. 17B. The etching of the anode material 374A to form the anode 374 may be selective to the oxide 371 layer such that the oxide 371 layer remains on the walls of the trenches. As illustrated in FIG. 17C, a cathode material 372A may then be deposited over the semiconductor substrate 360 and in the trenches over the anode 374. Deposition of the cathode material 372A may be accomplished using conventional deposition processes. The cathode material 372A may be masked and etched according to conventional processes to form the cathode 372 structure illustrated in FIG. 17D. Conventional RAD structure fabrication processes may be employed to form an insulator cap 376 and sidewall spacers 378 of the RAD structure 370 according to embodiments of the invention. The active areas in the semiconductor substrate 360, such as the bitline contacts 363 and storage capacitors 362, may also be formed using conventional processes for forming active areas. For example, the bitline contacts 363 and the storage capacitors 362 may be doped with an n-type dopant to form N+ doped active areas.

According to embodiments of the invention, the anode material 374A and cathode material 372A may be selected such that the work function of the two materials is different. For example, in some embodiments the cathode material 372A and anode material 374A may each comprise Ruthenium-Tantalum which may be represented by the chemical formula RuxTay wherein x and y may be selected according to the desired work functions for the diode. The anode 374 may be formed of an RuxTay material wherein x and y are selected such that the anode 374 exhibits a work function of about 5.0 eV. The cathode 372 may be formed of an RuxTay material wherein x and y are selected such that the cathode 372 exhibits a work finction of about 4.2 eV. Other values of x and y may be selected such that the work functions of the formed materials are different.

The gate electrodes formed by the RAD structures 370 of particular embodiments of the invention may be formed as long diodes in the trenches of the semiconductor substrate 360. The bottom portion of the RAD structure 370 in the trenches of the semiconductor substrate 360 is the anode 374 and the top portion is the cathode 372 of the diode. When the recessed access device 350 is in an “off” state, the anode 374 may be held at a negative word line voltage while the cathode 372 may be held at a higher voltage to create a reverse biased diode. The difference in voltages between the cathode 372 and the anode 374 may create a reverse bias across the diode. The bias level of the cathode 372 may be determined by the breakdown voltage of the reversed biased diode gate. The cathode 372 region bias level may decrease the voltage difference between storage capacitors 362 and the RAD structure 370, which in turn may decrease the electric field in the gate electrode area. The decreased electric field in the RAD structure 370 area may help to reduce the gate-induced drain leakage in a RAD structure 370 formed according to embodiments of the invention. In an “on” state, both the anode 374 and the cathode 372 may be driven to the same positive level as with conventional recessed access devices.

In still other embodiments of the invention, the diode of the RAD structure 370 may be formed such that a Schottky-Barrier diode is formed in the RAD structure 370. In such instances, the anode 374 may be a metal layer deposited in the trenches of the semiconductor substrate 360 and recessed so that it only remains in the bottom of the trenches. The cathode 372 may be a polysilicon material deposited over the metal anode 374 that is doped, for example a polysilicon material that is slightly doped N+ Embodiments of the invention may also include RAD structures 370 formed of other Schottky-Barrier type diodes.

The gate stacks 320 and RAD structures 370 according to embodiments of the invention may use two separate access device voltages to bias the diode formed by the anodes 374 and cathodes 372 of the gate electrodes. An access device driver, such as those described herein, capable of providing multiple voltage levels may be combined with the gate stacks 320 and RAD structures 370 to carry out particular embodiments of the invention.

According to other embodiments of the invention, an access device driver may be capable of driving the devices and structures of embodiments of the invention. Access device drivers and driver circuits used with embodiments of the invention may be able to turn two or more portions of the gate electrodes of a gate stack or recessed access device “on” and “off.” The access device drivers of embodiments of the invention are modified to provide separate bias levels onto the anode and cathode regions of a diode in a gate electrode or onto the electrically isolated regions of a gate electrode for a planar or recessed access device.

For example, access device drivers according to embodiments of the invention may be capable of applying a negative gate electrode voltage to one portion of a gate electrode and a ground voltage to another portion of the gate electrode. Thus, the driver would be able to supply two or more voltages to the gate electrode of a planar or recessed access device.

An example of an access device driver that may be used according to embodiments of the invention is illustrated in FIG. 13. The access device driver may include two outputs which may accommodate one or more diodes connected between the outputs as illustrated in FIG. 13.

For example, the access device driver illustrated in FIG. 13 may be incorporated with an access device to operate the gate stacks 220 or RAD structures 270 having two or more electrically isolated regions such as those illustrated in FIGS. 7 and 9. The contact of the access device driver labeled 1 may be connected to the second gate materials of a gate stack 220 or a RAD structure 270, while the contact of the access device driver labeled 2 may be connected to the first gate material of the same gate stack 220 or RAD structure 270. In this manner, differing bias levels may be applied by the access device driver to the first gate material and second gate material of a gate stack 220 or RAD structure 270.

In another embodiment, an access device driver such as that illustrated in FIG. 12 may be used to supply separate bias levels to a gate stack or gate electrode of a planar or recessed access device, having a diode in the gate electrode. For example, the access device driver illustrated in FIG. 12 may be used to supply voltages to the anodes and cathodes of the planar and recessed gates electrodes illustrated in FIGS. 13 and 16, respectively.

The access device drivers according to embodiments of the invention may also include resistive devices (not shown) positioned between one of the outputs of the access device driver and the access device, such as a recessed or planar access device. In case of a defect or short between two, or more, electrically isolated regions of an access device, the presence of a resistive device between one of the outputs of the access device driver and one of the electrically isolated regions in the access device may limit the current path between the two, or more, separate power supplies utilized by the driver.

The ability to apply different bias levels to the different portions of the planar or recessed access device gate electrodes allows the amount of gate induced drain leakage (GIDL) to be controlled. Furthermore, the ability to turn one portion of the gate electrode “off” at a lower voltage than the other ensures that subthreshold leakage may be minimized. Furthermore, if subthreshold leakage is minimized, the substrate bias may be reduced to decrease junction leakage.

The access device drivers according to embodiments of the invention may be used with CMOS applications, memory devices such as DRAM, and with any other semiconductor devices where it may be desirable to turn different portions of a gate electrode to different “off” or “on” states to control or reduce GIDL, subthreshold leakage, or junction leakage.

Having thus described certain currently preferred embodiments of the present invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are contemplated without departing from the spirit or scope thereof as hereinafter claimed.

Referenced by
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Classifications
U.S. Classification257/392
International ClassificationH01L29/94
Cooperative ClassificationH01L21/823425, H01L29/66621, H01L21/82345
European ClassificationH01L29/66M6T6F11D2, H01L21/8234D2, H01L21/8234G4
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