US 20070287219 A1
A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.
24. A method of forming a memory device, comprising:
providing a first electrode;
forming a chalcogenide glass layer over said first electrode;
sputtering a plurality of alternating tin chalcogenide layers and silver layers over said chalcogenide glass layer; and
providing a second electrode over said plurality of alternating tin chalcogenide layers and silver layers.
25. The method of
26. The method of
27. The method of
28. The method of
29. The method of
30. The method of
31. The method of
forming a second chalcogenide glass layer over said plurality of alternating tin chalcogenide and silver layers;
forming a metal layer over said second chalcogenide glass layer, said metal layer comprising silver; and
forming a third chalcogenide glass layer over said metal layer.
32. A method of forming a memory device, comprising:
providing a first electrode;
providing a first germanium selenide layer over said first electrode;
sputtering a plurality of alternating tin selenide layers and silver layers over said first germanium selenide layer;
providing a second germanium selenide layer over said plurality of alternating tin selenide layers and silver layers;
providing a metal layer over said second germanium selenide layer, said metal layer comprising silver;
providing a third germanium selenide layer over said metal layer; and
providing a second electrode over said third germanium selenide layer.
33. The method of
34. The method of
35. The method of
36. The method of
The invention relates to the field of random access memory (RAM) devices formed using a resistance variable material.
Resistance variable memory elements, which include chalcogenide-based programmable conductor elements, have been investigated for suitability as semi-volatile and non-volatile random access memory devices. A typical such device is disclosed, for example, in U.S. Pat. No. 6,849,868 to Campbell, which is incorporated by reference.
In a typical chalcogenide-based programmable conductor memory device, a conductive material, such as silver, is incorporated into a chalcogenide glass. The resistance of the chalcogenide glass can be programmed to stable higher resistance and lower resistance states. An unprogrammed chalcogenide-based programmable conductor memory device is normally in a higher resistance state. A write operation programs the chalcogenide-based programmable conductor memory device to a lower resistance state by applying a voltage potential across the chalcogenide glass. The chalcogenide-based programmable conductor memory device may then be read by applying a voltage pulse of a lesser magnitude than required to program it; the resistance across the memory device is then sensed as higher or lower to define the ON and OFF states.
The programmed lower resistance state of a chalcogenide-based programmable conductor memory device can remain intact for an indefinite period, typically ranging from hours to weeks, after the voltage potentials are removed. The chalcogenide-based programmable conductor memory device can be returned to its higher resistance state by applying a reverse voltage potential of about the same order of magnitude as used to write the device to the lower resistance state. Again, the higher resistance state is maintained in a semi- or non-volatile manner once the voltage potential is removed. In this way, such a device can function as a variable resistance memory having at least two resistance states, which can define two respective logic states, i.e., at least a bit of data.
One exemplary chalcogenide-based programmable conductor memory device uses a germanium selenide (i.e., GexSe100-x) chalcogenide glass as a backbone. The germanium selenide glass has, in the prior art, incorporated silver (Ag) and silver selenide (Ag2Se).
Previous work by the inventor, Kristy A. Campbell, has been directed to chalcogenide-based programmable conductor memory devices incorporating a silver-chalcogenide material as a layer of silver selenide (e.g., Ag2Se) or silver sulfide (e.g., Ag2S) in combination with a silver-metal layer and a chalcogenide glass layer. The silver-chalcogenide materials are suitable for assisting in the formation of a conducting channel through the chalcogenide glass layer for silver ions to move into to form a conductive pathway.
Tin (Sn) has a reduced thermal mobility in GexSe100-x compared to silver and the tin-chalcogenides are less toxic than the silver-chalcogenides, therefore tin-chalcogenides (e.g., SnSe) have also been found to be useful in chalcogenide-based programmable conductor memory devices to replace silver selenide. However, sputtering of tin selenide to form such devices has proven difficult due to the increased density of the sputtered layers. This increased density (e.g., ˜6 g/cm3 sputtered compared to ˜3 g/cm3 evaporated) can prevent the motion of silver ions into the chalcogenide glass, thereby preventing the memory device from functioning. Therefore, evaporative deposition techniques have been used to deposit such material, which is generally a less efficient, more costly, slower, and less controlled technique for deposition. However, evaporation deposition of tin selenide and silver also incorporates some oxygen into the resulting layer, which provides for the lower density and allows for more mobility of silver ions.
In an exemplary embodiment, the invention provides a chalcogenide-based programmable conductor memory device having a layered stack with a region containing tin-chalcogenide and silver proximate a chalcogenide glass layer. The device comprising a chalcogenide glass layer and the region of tin-chalcogenide and silver is formed between two conductive layers or electrodes. The tin-chalcogenide and silver region is formed by sputter deposition of tin-chalcogenide and silver.
In an exemplary embodiment of the invention, the chalcogenide-based programmable conductor memory device contains alternating layers of tin selenide (e.g., SnxSe, where x is between about 0 and 2) and silver.
In an exemplary embodiment of the invention, the tin-chalcogenide and silver region is formed by alternation of sputtering of tin selenide and silver layers over the chalcogenide glass layer.
The above and other features and advantages of the invention will be better understood from the following detailed description, which is provided in connection with the accompanying drawings.
In the following detailed description, reference is made to various specific embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention. It is to be understood that other embodiments may be employed, and that various structural, logical and electrical changes may be made without departing from the spirit or scope of the invention.
The term “substrate” used in the following description may include any supporting structure including, but not limited to, a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon, epitaxial silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. When reference is made to a semiconductor substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation. The substrate need not be semiconductor-based, but may be any support structure suitable for supporting an integrated circuit, including, but not limited to, metals, alloys, glasses, polymers, ceramics, and any other supportive materials as is known in the art.
The term “silver” is intended to include not only elemental silver, but silver with other trace metals or in various alloyed combinations with other metals as known in the semiconductor industry, as long as such silver alloy is conductive, and as long as the physical and electrical properties of the silver remain unchanged.
The term “tin” is intended to include not only elemental tin, but tin with other trace metals or in various alloyed combinations with other metals as known in the semiconductor industry, as long as such tin alloy is conductive, and as long as the physical and electrical properties of the tin remain unchanged.
The term “tin-chalcogenide” is intended to include various alloys, compounds, and mixtures of tin and chalcogens (e.g., sulfur (S), selenium (Se) tellurium (Te), polonium (Po), and oxygen (O)), including some species which have an excess or deficit of tin. For example, tin selenide, a species of tin-chalcogenide, is a preferred material for use in the invention and may be represented by the general formula Sn+/−Se. Though not being limited by a particular stoichiometric ratio between Sn and Se, devices of the present invention typically comprise an SnxSe species where x ranges between about 0 and about 2, e.g., SnSe.
The term “chalcogenide glass” is intended to include glasses that comprise at least one element from group VIA (also know as group 16) of the periodic table. Group VIA elements (e.g., O, S, Se, Te, and Po) are also referred to as chalcogens.
The invention is now explained with reference to the figures, which illustrate exemplary embodiments and throughout which like reference numbers indicate like features.
The conductive address line 12 can be any material known in the art as being useful for providing an interconnect line, such as doped polysilicon, silver (Ag), gold (Au), copper (Cu), tungsten (W), nickel (Ni), aluminum (Al), platinum (Pt), titanium (Ti), and other materials. Over the address line 12 is a first electrode 16, which can be defined within an insulating layer 14, if desired, and which is also over the address line 12. This electrode 16 can be any conductive material that will not migrate into chalcogenide glass, but is preferably tungsten (W). The insulating layer 14 should not allow the migration of silver (or other metal, e.g., copper) ions and can be an insulating nitride, such as silicon nitride (Si3N4), a low dielectric constant material, an insulating glass, or an insulating polymer, but is not limited to such materials.
A memory element, i.e., the portion of the memory device 100 which stores information, is formed over the first electrode 16. In the embodiment shown in
Over the chalcogenide glass layer 18 is a region 20 of tin-chalcogenide; preferably tin selenide (SnxSe, where x is between about 0 and 2), and silver, which are layered as shown in
Still referring to
In accordance with the embodiment shown at
The optional second chalcogenide glass layer 18 a is formed over the tin selenide and silver region 20, is preferably Ge2Se3, and is preferably about 150 Å thick. Over this optional second chalcogenide glass layer 18 a is a metal layer 22, which is preferably silver (Ag) and is preferably about 500 Å thick. Over the metal layer 22 is an optional third chalcogenide glass layer 18 b, which is preferably Ge2Se3 and is preferably about 100 Å thick. The optional third chalcogenide glass layer 18 b provides an adhesion layer for subsequent electrode formation. As with layer 18 of
Over the optional third chalcogenide glass layer 18 b is a second electrode 24, which may be any conductive material, but is preferably not one that will migrate into the memory element stack and alter memory operation (e.g., not Cu or Ag), as discussed above for the preceding embodiments. Preferably, the second electrode 24 is tungsten (W).
As shown by
Still referring to
Still referring to
Again, the thickness of region 20 is selected based, in part, on the thickness of layer 18; therefore, where the chalcogenide glass layer 18 is preferably about 300 Å thick, the alternating tin selenide layers 20 a and silver layers 20 b should make for a region 20 that is about 1,000 Å to about 2,000 Å thick. It should be noted that, as the processing steps outlined in relation to
Still referring to
Still referring to
Now referring to
A conditioning step is performed by applying a voltage pulse of a given duration and magnitude to incorporate material from the tin selenide and silver region 20 into the chalcogenide glass layer 18 to form a conducting channel in the chalcogenide glass layer 18. The conducting channel will support a conductive pathway during operation of the memory device 101, the presence or lack of which provides at least two detectable resistance states for the memory device 101.
The embodiments described above refer to the formation of only a few possible chalcogenide-based programmable conductor memory device in accordance with the invention, which may be part of a memory array. It must be understood, however, that the invention contemplates the formation of other memory structures within the spirit of the invention, which can be fabricated as a memory array and operated with memory element access circuits.
In the case of a computer system, the processor system may include peripheral devices, such as a floppy disk drive 454 and a compact disc (CD) ROM drive 456, which also communicate with CPU 444 over the bus 452. Memory circuit 448 is preferably constructed as an integrated circuit, which includes one or more resistance variable memory devices, e.g., device 101. If desired, the memory circuit 448 may be combined with the processor, for example CPU 444, in a single integrated circuit.
The above description and drawings should only be considered illustrative of exemplary embodiments that achieve the features and advantages of the invention. Modification and substitutions to specific process conditions and structures can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.