|Publication number||US20080014533 A1|
|Application number||US 11/487,246|
|Publication date||Jan 17, 2008|
|Filing date||Jul 14, 2006|
|Priority date||Jul 14, 2006|
|Also published as||US8367303, US9082721, US20130164659|
|Publication number||11487246, 487246, US 2008/0014533 A1, US 2008/014533 A1, US 20080014533 A1, US 20080014533A1, US 2008014533 A1, US 2008014533A1, US-A1-20080014533, US-A1-2008014533, US2008/0014533A1, US2008/014533A1, US20080014533 A1, US20080014533A1, US2008014533 A1, US2008014533A1|
|Inventors||David J. Keller, Alex Schrinsky|
|Original Assignee||Keller David J, Alex Schrinsky|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (28), Classifications (17), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to semiconductor fabrication processes and, more particularly, to dry develop processes with improved tunability of critical dimensions during semiconductor fabrication.
2. State of the Art
A common process requirement in semiconductor device fabrication is the removal of material layers or films to form features of a semiconductor device. For example, semiconductor fabrication may include the etching and formation of structures and openings such as trenches, contacts and vias in the material layers overlying conductive or semiconductive substrates. The patterning and formation of such structures is generally accomplished through the use of a patterned photolithographic mask and often, a hard mask or resist.
During semiconductor fabrication, it is preferable for sidewalls of the mask and resist used to define desired features to remain perpendicular to the surface of the underlying substrate. However, as feature dimensions are ever-decreasing and desired feature densities are ever-increasing, it is more and more difficult to create complex circuit structures on a small size chip using conventional etching processes. For example, as the size of the photoresist or photomask patterns are reduced, the thickness of the photomask must also decrease, in order to control pattern resolution in the underlying layers. The thinner photomask is not very rigid and may be eroded away during the etching process, which may lead to sidewall bowing (i.e., concave sidewalls) in the photomask and to poor line and profile control, as well as loss of the critical dimension of the mask and underlying substrate.
One approach to solve this problem of mask erosion is to include an antireflective coating (ARC) beneath the photomask. The ARC is formed over the substrate layers to be etched to prevent non-uniform reflection of radiation during the patterning of the photomask and, thus, inhibit defects in the photomask. Subsequently, the ARC may be etched using the photomask layer as a mask to remove those layers of the ARC which correspond to the openings in the photomask. However, even with the use of an ARC, there may still be lateral etching and sidewall bowing using conventional etching processes.
In another approach to the mask erosion problem, a carbon-based mask may be formed above an underlying semiconductor substrate and beneath the photomask and/or ARC as an etch-stop layer in order to improve the fidelity of the masking layers during etching of the underlying substrate layers. The carbon-based mask is more rigid and etch resistant than the photomask layer, thus providing for good etch selectivity for fabrication of openings in the semiconductor device.
Conventional plasma dry etch gas chemistries include CHF3+CF4+O2+Ar, N2+He+O2, N2+O2, N2+He, O2+CO2, O2+SO2, and C2F6+Ar. This type of plasma etching is called a “dry develop” process. Dry develop process chemistries, such as O2+SO2, are known in the art and work well, as they give good selectivity to the mask material and the underlying layer. However, conventional dry develop process chemistries lack sufficient ability to tune the critical dimension (CD) of the mask by preferentially growing, trimming or slanting the sidewall profile of a carbon-based mask. Furthermore, when the critical dimension of the mask falls below 120 nm, it becomes advantageous or even necessary to use advanced patterning and etching techniques. The critical dimension of a mask includes the profile and dimensions of the features of a mask such as the dimensions of the patterned solid regions as well as the dimensions of the exposed and removed areas of the mask. For example, it may be advantageous to grow (i.e., add material to), to trim (i.e., remove material from) and/or slant a surface defining a critical dimension of the carbon-based mask and, as such, tune the critical dimension thereof.
Therefore, there is a need for a dry develop process providing the ability to tune and control critical dimensions of a carbon-based mask during the fabrication of semiconductor devices.
While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the features and advantages of the claimed invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:
Reference will now be made in detail to various embodiments of a method of fabricating a semiconductor device, examples of which are illustrated in the accompanying drawings. Although the following description refers to the illustrated embodiments, it is to be understood that these embodiments are presented by way of example and not by way of limitation. The following detailed description encompasses such modifications, alternatives, and equivalents as may fall within the spirit and scope of the invention as defined by the claims.
It is to be understood that the processes described herein do not cover a complete process flow for the fabrication of a semiconductor device. Processes that incorporate teachings of the present invention may be practiced with various semiconductor device fabrication techniques that are conventionally used in the art, and only so much of the commonly practiced process acts are included herein as are necessary or desirable to provide an understanding of the present invention. Thus, for example, the following description does not address the interconnection of the transistors formed or other subsequent processing, generally referred to as “back end” processing.
In one aspect, the invention includes methods of tuning the critical dimension of semiconductor device features formed during the semiconductor fabrication process. The methods may include the use of a dry develop chemistry comprising O2, SO2 and a hydrogen halide. The methods may further include supporting a semiconductor device in a dry develop reactor and forming a carbon-based mask 15 m over the semiconductor device. As illustrated in
Additionally, the methods of one aspect of the invention may include removing the exposed areas 18 of the initial mask structure 20 with an appropriate removal process in order to expose an area of the carbon-based layer 15, as shown in
In another particular aspect of the invention, a dry develop chemistry comprising O2, SO2 and HBr may be used to remove the exposed areas 18 of the carbon-based mask 15 m to create openings 45 (see
Conventional dry develop chemistries containing O2 and SO2 without HBr often result in the lateral etching and bowing of sidewalls 40 and loss of the critical dimension. The term “critical dimension loss,” as used herein, includes the erosion of feature dimensions during the etching process such as bowing of feature sidewalls and lateral etching of the overlying mask structure. This phenomenon is caused, at least in part, by the higher reactivity of alternate dry develop chemistries with reactants such as O−, Cl−, and F− that will etch the sidewall 40 without providing sufficient passivation of the sidewall 40. However, using the O2, SO2, HBr dry develop chemistry allows for a user to tune the profiles of sidewalls 40 and provides for passivation of sidewalls 40, thus limiting lateral etching and sidewall bowing typically exhibited by the use of dry develop chemistries without HBr.
Passivation of the carbon-based mask 15 m, such as passivation of the sidewalls 40, occurs as the Br− ions react with the sidewalls 40 of the carbon-based mask 15 m forming a passivation layer, such as a layer of CBr4, on the surface of the sidewalls 40 (see,
Examples of processes of the present invention may be carried out by a dry develop process run in a dry develop reactor or a plasma etch reactor, such as a Lam 2300 KIYO etcher (Lam Research Corporation, Fremont, Calif.). Furthermore, particular embodiments may use low or high density systems. According to one aspect of the invention, the dry develop process may begin with an initial structure 5 (
In another embodiment, an intermediate mask layer 60 may, for purposes of example only and not as a limitation of the present invention, comprise one or more oxide 61, polysilicon 62, oxide 63 hard mask layers (
The carbon-based mask 15 m may be formed by dry etching a carbon-based material using an etch chemistry comprising O2, SO2, and HBr. Such a chemistry may be referred to as a dry develop process. As the dry develop process proceeds, as shown in
In another embodiment of the present invention, the O2, SO2, HBr dry develop chemistry may be used in processes for forming an intermediate hard mask that may provide for even greater dimensional control when forming a carbon-based mask from which one or more features of a semiconductor device are to be defined.
For purposes of example only and not by way of limitation of the present invention, the O2, SO2, HBr dry develop chemistry may be used for a so-called “pitch doubling” process during the formation of semiconductor devices. Pitch doubling is generally used to increase the number of features on a semiconductor device by making a mask with double the linear density that may conventionally be obtained with photolithographic processes.
During a pitch doubling process, an initial negative mask layer 50 (see,
As shown in
The general pattern of photomask 52 may be transferred to the underlying negative carbon-based layer 51 by etching the ARC 49, as illustrated in
The exposed areas of the negative carbon-based layer 51 may be removed using an O2, SO2, HBr dry develop chemistry process. The O2, SO2, HBr dry develop chemistry provides a high etch rate of the negative carbon-based layer 51 and high selectivity to the one or more ARCs 49 layer. Furthermore, the O2, SO2, HBr dry develop chemistry is superior to the typical O2 and SO2 chemistry because of the ability to tune and control the critical dimension and form vertical sidewalls 40 (
Once an initial negative mask layer 50, comprising the negative carbon-based mask 51 m, has been formed, any remnants of photomask 52 may be removed, as known in the art (e.g., with a suitable mask stripper) and shown in
Next, as depicted in
After oxide layer 54 is formed, a spacer etch may be conducted, as illustrated in
The remaining regions of the negative carbon-based mask 51 m (
Thereafter, also as depicted in
In order to demonstrate the effects of the O2, SO2, HBr dry develop chemistry on the critical dimension of a carbon-based mask, tests were carried out in a chamber 102 of a Lam 623 dry etch reactor 100, schematically depicted in
As shown by TABLE 1 and
While the present invention has been described in terms of certain illustrated embodiments and variations thereof, it will be understood and appreciated by those of ordinary skill in the art that the invention is not so limited. Rather, additions, deletions and modifications to the illustrated embodiments may be effected without departing from the spirit and scope of the invention as defined by the claims that follow.
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|U.S. Classification||430/311, 257/E21.257, 257/E21.253, 430/5, 257/E21.038, 257/E21.039|
|International Classification||G03F1/00, G03C5/00|
|Cooperative Classification||G03F1/00, H01L21/31122, H01L21/0338, H01L21/0337, H01L21/31144|
|European Classification||H01L21/033F6, H01L21/033F4, H01L21/311B2B2, H01L21/311D|
|Jul 14, 2006||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KELLER, DAVID J.;SCHRINSKY, ALEX;REEL/FRAME:018062/0387
Effective date: 20060629