US20080029782A1 - Integrated ESD protection device - Google Patents
Integrated ESD protection device Download PDFInfo
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- US20080029782A1 US20080029782A1 US11/499,576 US49957606A US2008029782A1 US 20080029782 A1 US20080029782 A1 US 20080029782A1 US 49957606 A US49957606 A US 49957606A US 2008029782 A1 US2008029782 A1 US 2008029782A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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Abstract
An integrated electrostatic discharge (ESD) device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also comprises a diffusion region that is shared by each of the first ESD structure and the second ESD structure, such that the shared diffusion region forms a portion of at least one semiconductor junction associated with each of the first ESD structure and the second ESD structure.
Description
- This invention relates to integrated circuits, and more specifically relates to an integrated electrostatic discharge (ESD) protection device.
- As semiconductor technology has constantly been improving, the use of field effect transistors (FETs) has become more prevalent in all facets of computer and communications technology. This technological improvement has allowed for faster operation and more compact arrangement of FETs within integrated circuit (IC) chips. IC chips are widely used in all electronic equipment, including equipment that is manufactured and operated in harsh environments. However, such harsh environments increase the likelihood of exposure of IC chips to high-voltage electrostatic discharge (ESD) events, to which IC chips are vulnerable. The high current that results from ESD events breaks down the internal semiconductor material of the FETs, resulting in damage to the IC chip. The vulnerability of IC chips to ESD events has created an important need for ESD protection circuits.
- Typically, ESD circuits are designed to protect a given device from ESD events that occur from a given terminal or node to ground. However, in some applications, a ground potential can experience a voltage shift or a pin can have a negative voltage transient relative to a substrate, which could be grounded. For example, in an automotive environment, ground can shift approximately 2 volts across the body of a car. Such negative voltage events can result in significant leakage current from ground to a given terminal through the ESD protection device, which may result in damage to the ESD protection device.
- One solution to this and other negative voltage shifts is the implementation of ESD protection devices in series with each other, each providing a respective direction of ESD protection. However, providing series connected ESD protection devices may not be able to provide the desired voltage characteristics for ESD protection in both directions. For example, the ESD current may not flow uniformly through the device, such that one of the ESD protection devices may break down during an ESD event in one or both directions. In addition, such an arrangement can be both cumbersome and costly. Another potential solution can include a resistor connected in series with the ESD protection device. However, such an arrangement can create an unacceptable voltage drop in the typical operation of the IC and can potentially degrade the ESD protection capability.
- One embodiment of the present invention provides an integrated electrostatic discharge (ESD) device. The integrated ESD device includes a first ESD structure coupled to a pad terminal of the integrated ESD device and a second ESD structure coupled to a ground terminal of the integrated ESD device. The integrated ESD device also includes a diffusion region that is shared by each of the first ESD structure and the second ESD structure, such that the shared diffusion region forms a portion of at least one semiconductor junction associated with each of the first ESD structure and the second ESD structure.
- Another embodiment of the present invention provides an integrated ESD device. The integrated ESD device includes means for providing ESD protection against an ESD event on a pad terminal of the integrated ESD device relative to a ground terminal of the integrated ESD device, the means for providing ESD protection being coupled between the ground terminal and a node. The integrated ESD device also includes means for providing leakage current protection against a leakage current associated with a negative voltage potential on the pad terminal relative to a substrate voltage, the means for providing leakage current protection being coupled between the node and the pad terminal. The integrated ESD device also includes shared means for providing a portion of at least one semiconductor junction in both the means for providing ESD protection and the means for providing leakage current protection.
- Another embodiment of the present invention provides an integrated ESD device. The integrated ESD device includes a substrate and a semiconductor well formed in the substrate to define a shared well. A first plurality of doped, shallow semiconductor wells are formed in the shared well to form portions of a first ESD structure, at least some first regions of the first plurality of shallow wells being coupled to a pad terminal of the integrated ESD device, and at least some second regions of the first plurality of shallow wells being coupled to a node. At least one second doped, shallow semiconductor well is formed in the shared well to form a portion of a second ESD structure. At least one region of the at least one second shallow well is electrically coupled to a ground terminal of the integrated ESD device, and another region of the at least one second shallow well is electrically coupled with the node, such that the first and second ESD structures are electrically connected in series between the pad terminal and the ground terminal.
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FIG. 1 illustrates an example of a schematic block diagram of an integrated ESD device in accordance with an aspect of the invention. -
FIG. 2 illustrates an example of a circuit diagram of an integrated ESD device in accordance with an aspect of the invention. -
FIG. 3 illustrates an example of a cross-sectional diffusion layout of the integrated ESD device ofFIG. 2 in accordance with an aspect of the invention. -
FIG. 4 illustrates an example of a circuit diagram of another integrated ESD device in accordance with an aspect of the invention. -
FIG. 5 illustrates an example of a cross-sectional diffusion layout of the integrated ESD device ofFIG. 4 in accordance with an aspect of the invention. - The present invention relates to integrated circuits, and more specifically relates to an integrated electrostatic discharge (ESD) protection device. Two or more separate ESD structures can be integrated together to form an integrated ESD device having a common diffusion region. For instance, one ESD structure could be parallel connected diodes, with an anode of each being connected to a cathode of the other. Alternatively, the first ESD structure could be a bi-directional semiconductor-controlled (or silicon-controlled) rectifier (SCR) circuit. The second ESD structure could be a Zener diode. The common diffusion region in the ESD device could form a portion of at least one semiconductor junction associated with each of the two separate ESD structures. In addition, the merging of the two ESD structures that share the common diffusion region could enable electrical protection characteristics that differ from a series connection of individual devices. Furthermore, by merging the two ESD structures to share the common diffusion region, the integrated ESD device could have desirable ESD activation characteristics without a voltage breakdown of either individual ESD structure.
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FIG. 1 illustrates an example of a diagram of an integratedESD device 10 in accordance with an aspect of the invention. The integratedESD device 10 is interconnected between apad terminal 12 and a low voltage supply terminal, illustrated in the example ofFIG. 1 as aground terminal 14. Thepad terminal 12 and theground terminal 14 could each correspond to pins on an integrated circuit (IC). Therefore, the integratedESD device 10 is operative to protect associated circuitry (e.g., on the IC) from damage resulting from an ESD event between thepad terminal 12 and theground terminal 14. For example, a vulnerable circuit device (not shown, but part of the IC) could be coupled to thepad terminal 12, such that an ESD event could cause damage and possibly failure of the vulnerable circuit device. As used herein, the term “vulnerable” refers to the exposure of such circuitry to ESD events at thepad terminal 12, which might be detrimental to such circuitry. The vulnerable circuitry might be in the IC, or otherwise electrically coupled (directly or indirectly) with thepad terminal 12. The integratedESD device 10 can activate upon the occurrence of the ESD event to divert current from thepad terminal 12 to theground terminal 14 through the integratedESD device 10. In this way, current does not flow through the vulnerable circuitry, thus preventing damage to the more vulnerable circuitry. - The integrated ESD device includes a
first ESD structure 16 and asecond ESD structure 18. For example, the first ESD structure could be a pair of parallel connected diodes, such that an anode of each diode is connected to a cathode of the other diode. Such an arrangement can provide a low-resistance current flow from the given pad terminal to the given ground terminal or from the given ground terminal to the given pad terminal. As an alternative, the first ESD structure could be a bi-directional SCR circuit, such that the first ESD structure could activate based on a given positive voltage potential at either the given pad terminal or the given ground terminal. The bi-directional SCR circuit could thus clamp and dissipate current flowing in either direction. As another example, the second ESD structure can include a Zener diode configured to operate in a reverse-bias state relative to a given pad terminal, or an NPN transistor operating in an emitter-collector rejection (ECR) mode. - The
first ESD structure 16 and thesecond ESD structure 18 are coupled together via acommon diffusion region 20. Thecommon diffusion region 20 can be a semiconductor layer or well within the integratedESD device 10 that is shared by each of thefirst ESD structure 16 and thesecond ESD structure 18. For example, thecommon diffusion region 20 could form a portion of one or more semiconductor junctions associated with each of thefirst ESD structure 16 and thesecond ESD structure 18. In other words, thecommon diffusion region 20 can provide a doped semiconductor material that forms a portion of at least one PN (or NP) junction associated with both thefirst ESD structure 16 and thesecond ESD structure 18. - By sharing the
common diffusion region 20, thefirst ESD structure 16 and thesecond ESD structure 18 can be merged to form theintegrated ESD device 10. As such, an ESD event occurring at thepad terminal 12 can be diverted throughintegrated ESD device 10 via thefirst ESD structure 16 and thesecond ESD structure 18. Thecommon diffusion region 20 helps to ensure that current flows uniformly through the entirety of theintegrated ESD device 10 from thepad terminal 12 to theground terminal 14 without breaking down either thefirst ESD structure 16 or thesecond ESD structure 18. For example, thecommon diffusion region 20, along with a substrate (not shown) of theintegrated ESD device 10, can create a parasitic diode having a reverse-bias breakdown voltage that is sufficient to prevent breakdown of theintegrated ESD device 10 during an ESD event. This integrated configuration can be contrasted with potential ESD breakdown of a reverse-bias parasitic diode that may be applicable to thefirst ESD structure 16 and/or thesecond ESD structure 18 if each structure were implemented individually as separate, electrically coupled devices. In addition, integrating thefirst ESD structure 16 and thesecond ESD structure 18 can afford a much smaller IC package than if the structures were formed individually. Therefore, theintegrated ESD device 10 is consistent with the demand for smaller electronic packages. - The
first ESD structure 16, when configured as part of theintegrated ESD device 10, can also afford protection against leakage current resulting from a negative voltage potential at thepad terminal 12 relative to the voltage of the substrate of theintegrated ESD device 10, which could be electrically coupled to (or be at the same voltage as) theground terminal 14. For example, thefirst ESD structure 16 can prevent leakage current flow through theintegrated ESD device 10 such as for changes in voltage at theground terminal 14 up to a negative voltage shift protection voltage. Such a leakage current can flow from the substrate, which could be grounded, to the pad terminal, for example, in response to a negative shift in the voltage of the substrate that exceeds the negative voltage shift protection voltage. Thefirst ESD structure 16 can be configured to have an additive effect on the capability of thesecond ESD structure 18 regarding the negative voltage shift protection voltage that operate to prevent current flow from theground terminal 14 to thepad terminal 12 for negative voltage shifts that are within the negative voltage shift protection voltage. The first andsecond ESD structures first ESD structure 16, by sharing thecommon diffusion region 20 with thesecond ESD structure 18, can provide the protection against leakage current without a detrimental effect on the ESD protection capability of theintegrated ESD device 10. For example, connecting a resistor in series with thesecond ESD structure 18 can create a voltage drop that could be unacceptable for certain ESD protection specifications and can degrade operation of the respective IC. -
FIG. 2 illustrates an example of a circuit diagram of anintegrated ESD device 50 in accordance with an aspect of the invention. Theintegrated ESD device 50 is interconnected between apad terminal 52 and a negative supply voltage terminal, illustrated in the example ofFIG. 2 as aground terminal 54. Thepad terminal 52 and theground terminal 54 could each be pins on an IC. Therefore, theintegrated ESD device 50 is operative to protect an associated circuit on the IC (or otherwise coupled to the pad terminal) from damage resulting from an ESD event between thepad terminal 52 and ground. - The integrated ESD device includes a
first ESD structure 56, illustrated in the example ofFIG. 2 as a first diode D1 connected in parallel with a second diode D2. The first diode D1 has an anode coupled to a cathode of the second diode D2 and to thepad terminal 52. The first diode D1 also has a cathode coupled to an anode of the second diode D2. The cathode of the first diode D1 and the anode of D2 are also coupled to asecond ESD structure 58 at anode 60. In the example ofFIG. 2 , thesecond ESD structure 58 is implemented as a Zener diode ZD1. Thefirst ESD structure 56 can provide a low-resistance current flow path from thepad terminal 52 to thenode 60, or from thenode 60 to thepad terminal 52. For example, each of the first diode D1 and the second diode D2 could have a forward-bias activation voltage characteristic of approximately 1 volt. Therefore, current flowing in either direction through thefirst ESD structure 56 can flow through a diode operating in a forward-bias state. - The Zener diode ZD1 is configured with an anode coupled to the
ground terminal 54 and a cathode coupled to thenode 60. It is to be understood that the example ofFIG. 2 is not limited to the use of the Zener diode ZD1 as thesecond ESD structure 58, but that other types of ESD devices can be used in accordance with an aspect of the invention. For example, thesecond ESD structure 58 could be implemented as an NPN transistor operating in an ECR mode. As another example, other types of applicable ESD structures can include metal oxide varistors (MOVs), transient voltage suppression (TVS) diodes, and regular complementary metal oxide semiconductor (CMOS) devices, bipolar clamp diodes, and combinations thereof. - In the example of
FIG. 2 , current resulting from an ESD event at thepad terminal 52 relative to theground terminal 54 can flow through the Zener diode ZD1 in a reverse-bias state, such as if the voltage exceeds the breakdown or Zener voltage. Similarly, leakage current resulting from a negative voltage shift can flow from theground terminal 54 to thepad terminal 52 through the Zener diode ZD1 in a forward-bias state. However, because the Zener diode ZD1 can operate in a reverse-bias state during an ESD event, thesecond ESD structure 58 has an ESD activation voltage that can be significantly greater than the forward-bias activation resulting from a negative voltage shift. As an example, the second ESD structure 58 (by itself) could have an ESD activation voltage of greater than or equal to 40 volts at thenode 60 relative to theground terminal 54 and a 1V forward-bias negative voltage shift protection voltage from theground terminal 54 to thenode 60. -
FIG. 3 illustrates an example of a cross-sectional diffusion layout of theintegrated ESD device 50 in the example ofFIG. 2 in accordance with an aspect of the invention. It is to be understood that the following discussion is in reference to bothFIGS. 2 and 3 . Therefore, like reference numbers will be used in the description of the example ofFIG. 3 to refer to structure previously introduced with respect toFIG. 2 . In the example ofFIG. 3 , a dashedline 62 illustrates the separation between thefirst ESD structure 56, depicted on the left of the dashedline 62, and thesecond ESD structure 58, depicted on the right of the dashedline 62. Thefirst ESD structure 56 and thesecond ESD structure 58 are illustrated in the example ofFIG. 3 as being formed in acommon diffusion region 64. In the example ofFIG. 3 , thecommon diffusion region 64 is demonstrated as an N-type well (hereinafter “DN_well”). Thecommon diffusion region 64 is formed in a P-type substrate 66. Thefirst ESD structure 56 includes a shallow N-type well (hereinafter “SN_well”) 68 and a shallow P-type well (hereinafter “SP_well”) 70 formed in thecommon diffusion region 64. N+ and P+ regions are doped in each of the respective SN_well 68 andSP_well 70. Thepad 52 is electrically connected (e.g., by metallization or other connections) to the P+ region of theSN_well 68 and to the N+ region of theSP_well 70. The N+ region of theSN_well 68 and the P+ region of theSP_well 70 are electrically connected with thenode 60. - The
second ESD structure 58 is defined by a SP_well 72 and anN+ region 74 formed in thecommon diffusion region 64, as well as aP+ region 76 formed in the P-type substrate 66. P+ and N+ regions are also doped into theSP_well 72. Aresistor 73 can electrically couple the P+ and N+ regions, with the N+ region being further electrically connected with theground terminal 54. TheN+ region 74 further can be coupled to thenode 60 and the other N+ region of thesecond ESD structure 58 can be coupled to theground terminal 54. It is to be understood thatFIG. 3 is merely an example of a diffusion layout of theintegrated ESD device 50, and that other arrangements of theintegrated ESD device 50 are possible, such as relative positioning of thefirst ESD structure 56 and thesecond ESD structure 58, as well as relative doping of the semiconductor regions. It is also to be understood that, in the example ofFIG. 3 , semiconductor regions of a like type (i.e., N-type or P-type) can be doped at the same or similar levels of concentrations using known dopants. Alternatively, different dopant concentrations can be utilized. - The
first ESD structure 56 and thesecond ESD structure 58 are formed as part of an integrated structure together within the DN_well that forms thecommon diffusion region 64. It is to be understood that, in the example ofFIG. 2 , thecommon diffusion region 64 is not shown, asFIG. 2 depicts a circuit diagram representation for theintegrated ESD device 50. In the example ofFIG. 3 , by virtue of the relative N-type doping between theSP_well 70 and the DN_well (the common diffusion region) 64 being at the same voltage potential, thecommon diffusion region 64 forms part of a PN junction associated with both the first diode D1 and with the Zener diode ZD1. That is, thecommon diffusion region 64 is shared by thefirst ESD structure 56 and thesecond ESD structure 58, such that it forms a portion of a semiconductor PN junction for both thefirst ESD structure 56 and thesecond ESD structure 58. - By sharing the
common diffusion region 64, thefirst ESD structure 56 and thesecond ESD structure 58 can be merged to form theintegrated ESD device 50. As such, an ESD event occurring at thepad terminal 52 can be diverted throughintegrated ESD device 50 via cooperation of thefirst ESD structure 56 and thesecond ESD structure 58. For example, current resulting from an ESD event can flow from thepad terminal 52, through the first diode D1 operating in a forward-bias state, through the Zener diode ZD1 operating in a reverse-bias state, and to theground terminal 54. The integration of thefirst ESD structure 56 and thesecond ESD structure 58 could provide an ESD activation voltage of, for example, greater than or equal to +41 volts for theintegrated ESD device 50, resulting from the ESD activation voltage of greater than or equal to +40 volts of the Zener diode ZD1 and the +1 volt forward-bias activation voltage of the first diode D1. - In addition, the shared
common diffusion region 64 helps to ensure that current flows uniformly through the entirety of theintegrated ESD device 50 from thepad terminal 52 to theground terminal 54 without breaking down either thefirst ESD structure 56 or thesecond ESD structure 58. In the example ofFIG. 2 , a parasitic diode PD1 is configured with a cathode coupled to thenode 60 and an anode coupled to theground terminal 54. The parasitic diode PD1 results from the semiconductor junction between the P-type substrate 66 and the N-typecommon diffusion region 64, such as depicted in the example ofFIG. 3 . Because thefirst ESD structure 56 and thesecond ESD structure 58 share thecommon diffusion region 64, the parasitic diode PD1 exhibits a reverse-bias breakdown voltage that is sufficient to prevent breakdown of theintegrated ESD device 50 during an ESD event. In the example ofFIG. 2 , the parasitic diode PD1 is configured in a reverse-bias state such that current flow from thepad 52 to theground terminal 54 is forced through the entireintegrated ESD device 50. Without a sufficient reverse-bias breakdown voltage of the parasitic diode PD1, an ESD event could breakdown the parasitic diode PD1 and ESD current could bypass either thefirst ESD structure 56 of thesecond ESD structure 58. Such a breakdown could be damaging to theintegrated ESD device 50, and as such is undesirable. To substantially prevent breakdown of the parasitic diode PD1, thecommon diffusion region 64 can, for example, be configured as sufficiently spacing theshallow wells type substrate 66 to provide a substantially higher reverse-bias breakdown voltage of the parasitic diode PD1 (e.g., 60 volts or more). For example, thecommon diffusion region 64 can be a deep well relative to theshallow wells pad terminal 52 flows uniformly through thefirst ESD structure 56 and thesecond ESD structure 58, as opposed to breaking down the parasitic diode PD1. This occurs because the parasitic diode PD1 is configured to have a reverse-bias breakdown voltage that is substantially greater than the ESD activation voltage of theintegrated ESD device 50. - Absent the shared
common diffusion region 64, each of thefirst ESD structure 56 and thesecond ESD structure 58 could have a separate, individual parasitic diode, each with a separate reverse-bias breakdown voltage. For example, thefirst ESD structure 56, standing alone, may not have the shallow wells spaced-apart enough from the substrate, and could thus have a parasitic diode with a reverse-bias breakdown voltage of about 20 volts. Therefore, an ESD event of at least 40 volts occurring at thepad terminal 52, resulting in current flow through the individually connectedfirst ESD structure 56 andsecond ESD structure 58, could breakdown thefirst ESD structure 56, thus resulting in damage to the device. Accordingly, by integrating thefirst ESD structure 56 and thesecond ESD structure 58 to share thecommon diffusion region 64, the parasitic diode PD1 has a sufficient reverse-bias voltage to substantially prevent breakdown during an ESD event. Since this reverse-bias breakdown voltage of the parasitic diode PD1 is greater than the activation voltage of theintegrated ESD structure 50, current can flow uniformly through theintegrated ESD device 50 via thefirst ESD structure 56 and thesecond ESD structure 58. - The
first ESD structure 56, as part of theintegrated ESD device 50, can also provide leakage current protection resulting from a negative voltage at thepad terminal 52 relative to the P-type substrate 66. Such a leakage current can result, in the example ofFIG. 3 , from a negative voltage shift occurring at theground terminal 54. For example, the leakage current can flow from theground terminal 54, through the Zener diode ZD1 operating in a forward-bias state, through the second diode D2 operating in a forward-bias state, and to thepad terminal 52. As such, thefirst ESD structure 56 is configured to have an additive effect on the capability of thesecond ESD structure 58 regarding a negative voltage shift protection voltage due to fluctuations in the voltage at theground terminal 54. For example, the 1 volt forward-bias activation voltage of the Zener diode ZD1 can be combined with the 1 volt forward-bias activation voltage of the second diode D2, such that theintegrated ESD device 50 has a negative voltage shift protection voltage of 2 volts. The negative voltage shift protection voltage of theintegrated ESD device 50 enables prevention of leakage current flow associated with a negative voltage shift that resides within the 2V, such that neither of theESD structures integrated ESD device 50. Continuing with the above example ofFIGS. 2 and 3 , theintegrated ESD device 50 can thus be implemented to have an ESD activation voltage from thepad terminal 52 to theground terminal 54 of greater than or equal to +41 volts, and a negative voltage shift protection voltage of approximately −2V. -
FIG. 4 illustrates another example of a circuit diagram of anintegrated ESD device 100 in accordance with an aspect of the invention. Theintegrated ESD device 100 is interconnected between apad terminal 102 and a negative supply voltage terminal, illustrated in the example ofFIG. 4 as aground terminal 104. Thepad terminal 102 and theground terminal 104 could each be pins on an IC. Theintegrated ESD device 100 is configured to protect associated circuitry (e.g., in the IC) from damage resulting from an ESD event that occurs between thepad terminal 102 and theground terminal 104. - The
integrated ESD device 100 includes afirst ESD structure 106, illustrated in the example ofFIG. 4 as a bi-directional SCR circuit, and asecond ESD structure 108, illustrated in the example ofFIG. 4 as a Zener diode ZD2. Thefirst ESD structure 106 includes afirst SCR structure 110 and asecond SCR structure 112 interconnected in parallel between thepad terminal 102 and anode 114. Thefirst SCR structure 110 includes a PNP bipolar junction transistor (BJT) P1, an NPN BJT N1, a resistor R1, and a Zener diode ZD3 connected as shown inFIG. 4 . Thesecond SCR structure 112 includes a PNP BJT P2, an NPN BJT N2, a resistor R2, and a Zener diode ZD4 connected as shown inFIG. 4 . In the example ofFIG. 4 , thefirst SCR structure 110 and thesecond SCR structure 112 are identical and oriented opposite each other with respect to thepad terminal 102 and thenode 114. It is to be understood, however, that other types of ESD structures could be utilized instead of the structures in the example ofFIG. 4 . It is to be further understood that thefirst SCR structure 110 and thesecond SCR structure 112 need not be identical, but that different types of SCR structures can be implemented in the bi-directional SCR circuit of thefirst ESD structure 106. - The
first SCR structure 110 can be configured to pass current flow from thepad terminal 102 to thenode 114, and thesecond SCR structure 112 can be configured to pass current flow from thenode 114 to thepad terminal 102. For example, each of thefirst SCR structure 110 and thesecond SCR structure 112 can each have an activation voltage of approximately 5 volts. It is to be understood, however, that each of thefirst SCR structure 110 and thesecond SCR structure 112 could each have an activation voltage of between approximately 1 and 10 volts, depending on how each is configured. Accordingly, at approximately 5 volts, a given one of thefirst SCR structure 110 and thesecond SCR structure 112 clamps and passes current until a lower voltage threshold (e.g., 1 volt) is achieved. Therefore, current can flow in either direction through thefirst ESD structure 106 based on the relative voltage potential between thepad 102 and thenode 114. - The Zener diode ZD2 of
second ESD structure 108 is configured with an anode coupled to theground terminal 104 and a cathode coupled to thenode 114. It is to be understood that the example ofFIG. 4 is not limited to the use of the Zener diode ZD2, but that other types of ESD devices, such as an NPN transistor operating in an ECR mode, can be implemented in accordance with an aspect of the invention. In the example ofFIG. 4 , current resulting from an ESD event at thepad terminal 102 relative to theground terminal 104 can flow through the Zener diode ZD2 in a reverse-bias state according to the breakdown voltage of the Zener diode ZD2. Similarly, leakage current resulting from a negative voltage shift can flow from theground terminal 104 to thepad terminal 102 through the Zener diode ZD2 in a forward-bias state. However, because the Zener diode ZD2 can operate in a reverse-bias state during an ESD event, thesecond ESD structure 108 has an ESD activation voltage that can be significantly greater than the forward-bias state resulting from a negative voltage shift. As an example, the second ESD structure 58 (by itself) could have an ESD activation voltage of greater than or equal to 40 volts at thenode 114 relative to theground terminal 104 and a 1V forward-bias negative voltage shift protection voltage from theground terminal 104 to thenode 114. -
FIG. 5 illustrates an example of a cross-sectional diffusion layout of theintegrated ESD device 100 in the example ofFIG. 4 in accordance with an aspect of the invention. It is to be understood that the following discussion is in reference to bothFIGS. 4 and 5 . Therefore, like reference numbers will be used in the description of the example ofFIG. 5 to refer to structure previously introduced with respect toFIG. 4 . In the example ofFIG. 5 , a dashedline 116 represents a separation between thefirst ESD structure 106, depicted on the left of the dashedline 116, and thesecond ESD structure 108, depicted on the right of the dashedline 116. Thefirst ESD structure 106 and thesecond ESD structure 108 are illustrated in the example ofFIG. 5 as shallow doped wells in acommon diffusion region 118. Thecommon diffusion region 118 is illustrated as a DN_well formed in a P-type substrate 120. Thefirst ESD structure 106 includes aSP_well 122, aSN_well 124, aSN_well 126, aSP_well 128, and anN+ region 132 formed in thecommon diffusion region 118. It is to be understood that theN+ region 132, as demonstrated in the example ofFIG. 5 , substantially surrounds theSP_well 122, theSN_well 124, theSN_well 126, and theSP_well 128 as a loop. Each of theSP_wells SN_wells SP_well 128. Similarly, the resistor R2 electrically connects the P+ and N+ regions of theSP_well 122. The P+ region of theSN_well 124 and the N+ region of theSN_well 124 are electrically coupled directly to thepad 102. The P+ region of theSN_well 126, the N+ region of theSP_well 128 and theN+ region 132 are electrically coupled directly to thenode 114. The resistors R1 and R2 can be poly-silicon resistors. - The
second ESD structure 108 includes aSP_well 132, anN+ region 134, and theN+ contact 132 formed in thecommon diffusion region 118, as well as aP+ region 136 in the P-type substrate 120. It is to be understood that theN+ region 132 is common to both thefirst ESD structure 106 and thesecond ESD structure 108. A P+ region and an N+ region are formed in theSP_well 134. Aresistor 137 interconnects the P+ and N+ regions of theSP_well 134. TheP+ region 136 and the N+ region of theSP_well 134 are electrically coupled directly toground 104. As mentioned above thecommon N+ region 132 is coupled to thenode 114. - It is also to be understood that
FIG. 5 is merely an example of a diffusion layout of theintegrated ESD device 100, and that other configurations of theintegrated ESD device 100 are possible. For instance the relative positioning of thefirst ESD structure 106 and thesecond ESD structure 108, as well as relative doping of the semiconductor regions can vary from that shown and described herein. It is to be further understood that, in the example ofFIG. 5 , semiconductor regions of a like type (i.e., N-type or P-type) can be doped at the same or different levels of concentrations, and the particular dopant concentrations may vary according to design specifications. - As illustrated in
FIG. 5 , thefirst ESD structure 106 and thesecond ESD structure 108 are formed in thecommon diffusion region 118. It is to be understood that thecommon diffusion region 118 is not shown, asFIG. 4 is merely a circuit representation of theintegrated ESD device 100. In the example ofFIG. 5 , thecommon diffusion region 118 defines a portion of the PN junctions associated with the transistors N1, N2, P1, and P2, as well as the Zener diodes ZD2, ZD3, and ZD4. Thus, thecommon diffusion region 118 is shared by thefirst ESD structure 106 and thesecond ESD structure 108, such that it forms a portion of semiconductor PN junctions associated with both thefirst ESD structure 106 and thesecond ESD structure 108. - By sharing the
common diffusion region 118, thefirst ESD structure 106 and thesecond ESD structure 108 can be merged to form theintegrated ESD device 100. As such, an ESD event occurring at thepad terminal 102 can be diverted through theintegrated ESD device 100 via cooperation between thefirst ESD structure 106 and thesecond ESD structure 108. For example, current resulting from an ESD event can flow from thepad terminal 102, through thefirst SCR structure 110, through the Zener diode ZD2 operating in a reverse-bias state, and to theground terminal 104. The integration of thefirst ESD structure 106 and thesecond ESD structure 108 could provide an ESD activation voltage of greater than or equal to +40 volts for theintegrated ESD device 100, which is approximately the same as thesecond ESD structure 108 alone. It is to be understood that, due to the sharing of thecommon diffusion region 118 as demonstrated in the example ofFIG. 5 , thefirst ESD structure 106 does not have an additive effect on the ESD activation voltage of theintegrated ESD device 100. Thus, the addition of thefirst ESD structure 106 to thesecond ESD structure 108 via the sharedcommon diffusion region 118 has substantially no detrimental effect on the ESD protection capability of thesecond ESD structure 108. - In addition, the shared
common diffusion region 118 helps to ensure that current flows uniformly through the entirety of theintegrated ESD device 100 from thepad terminal 102 to theground terminal 104 without breaking down either thefirst ESD structure 106 or thesecond ESD structure 108. For the example ofFIG. 4 , a parasitic diode PD2 has a cathode coupled to thenode 114 and an anode coupled to theground terminal 104. The parasitic diode PD2 results from the semiconductor junction between the P-type substrate 120 and the N-typecommon diffusion region 118, as demonstrated in the example ofFIG. 5 . Because thefirst ESD structure 106 and thesecond ESD structure 108 share thecommon diffusion region 118, the parasitic diode PD2 could have a reverse-bias breakdown voltage that is sufficient to prevent breakdown of theintegrated ESD device 100 during an ESD event. In the example ofFIG. 4 , the parasitic diode PD2 is configured in a reverse-bias state such that current flow from thepad 102 to theground terminal 104 is forced through the entireintegrated ESD device 100. Therefore, as illustrated in the example ofFIG. 5 , by implementing thecommon diffusion region 118 as sufficiently spacing theshallow wells type substrate 120, a substantially higher reverse-bias breakdown voltage can exist for the parasitic diode PD2 (e.g., 60 volts or more). For example, thecommon diffusion region 118 can be a deep well relative to theshallow wells pad terminal 102 flows uniformly through thefirst ESD structure 106 and thesecond ESD structure 108, as opposed to breaking down the parasitic diode PD2, because the parasitic diode PD2 has a reverse-bias breakdown voltage that is substantially greater than the ESD activation voltage of theintegrated ESD device 100. - Absent the shared
common diffusion region 118, each of thefirst ESD structure 106 and thesecond ESD structure 108 could have separate, individual parasitic diodes, each with a separate reverse-bias breakdown voltage. For example, thefirst ESD structure 106, standing alone, may not have the shallow wells spaced-apart enough from the substrate, and could thus have a parasitic diode with a reduced reverse-bias breakdown voltage (e.g., approximately 20 volts). Therefore, an ESD event of at least 40 volts occurring at thepad terminal 102, resulting in current flow through the individually connectedfirst ESD structure 106 andsecond ESD structure 108, could breakdown thefirst ESD structure 106, thus resulting in damage to the device. Accordingly, by integrating thefirst ESD structure 106 and thesecond ESD structure 108 to share the common diffusion region 118 (as shown inFIG. 5 ), the parasitic diode PD2 has a sufficient reverse-bias voltage to substantially prevent breakdown during an ESD event. The parasitic diode is further configured to have a reverse-bias breakdown voltage that exceeds the activation voltage of theintegrated ESD device 100 to allow uniform current flow through theintegrated ESD device 100 during ESD events. - The
first ESD structure 106, if configured as part of theintegrated ESD device 100, can also provide protection against leakage current resulting from a negative voltage at thepad terminal 102 relative to the P-type substrate 120. Such a leakage current can result, in the example ofFIG. 5 , from a negative voltage shift occurring at theground terminal 104. For example, the leakage current can flow from theground terminal 104, through the Zener diode ZD2 operating in a forward-bias state, through the second SCR structure, and to thepad terminal 102. As described above, thesecond SCR structure 112 can have an activation voltage of approximately 5 volts. As also described above, the Zener diode ZD2 can have a 1V activation voltage in the forward-bias, such as may result from a negative voltage shift. However, due to the clamping nature of a given SCR structure, as well as the sharing of thecommon diffusion region 118 by thefirst ESD structure 106 and thesecond ESD structure 108, the 5 volt activation voltage of thesecond SCR structure 112 is applicable to the entireintegrated ESD device 100. That is, the 5 volt activation forfirst ESD structure 106 effectively dominates or overrides the 1 volt negative voltage shift protection voltage of thesecond ESD structure 108 with the 5V activation voltage for a negative leakage current associated with theintegrated ESD device 100. Therefore, theintegrated ESD device 100 can prevent leakage current resulting from up to a negative voltage shift protection voltage of approximately 5V (corresponding to −5V relative to the pad terminal) without causing damage to the integrated device. In the example just described, theintegrated ESD device 100 can be implemented to have an ESD activation voltage from thepad terminal 102 to theground terminal 104 of greater than or equal to +40 volts, and a negative voltage shift protection voltage of approximately −5V. - What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. For example, while example voltages and operating characteristics have been described herein, those skilled in the art will understand and appreciate that integrated ESD devices can be implemented with other voltage operating characteristics in accordance with present invention. Accordingly, the present invention is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.
Claims (21)
1. An integrated electrostatic discharge (ESD) device comprising:
a first ESD structure coupled to a pad terminal of the integrated ESD device;
a second ESD structure coupled to a ground terminal of the integrated ESD device; and
a diffusion region that is shared by each of the first ESD structure and the second ESD structure, such that the shared diffusion region forms a portion of at least one semiconductor junction associated with each of the first ESD structure and the second ESD structure.
2. The integrated ESD device of claim 1 , wherein the first ESD structure comprises a first diode and a second diode, an anode of the first diode and a cathode of the second diode being coupled to the pad terminal and a cathode of the first diode and an anode of the second diode being coupled to the second ESD structure
3. The integrated ESD device of claim 2 , wherein the integrated ESD device has a pad terminal to ground terminal ESD activation voltage that is approximately equal to a sum of a forward bias voltage of the first diode and an activation voltage of the second ESD structure from the node to the ground terminal, and wherein the integrated ESD device has a negative voltage shift protection voltage that is approximately equal to a sum of a bias voltage of the second ESD structure from the ground terminal to the node and a forward bias voltage of the second diode.
4. The integrated ESD device of claim 1 , wherein the first ESD structure comprises a bi-directional silicon-controlled rectifier (SCR) circuit.
5. The integrated ESD device of claim 5 , wherein the integrated ESD device has a pad terminal to ground terminal ESD activation voltage that is approximately equal to an ESD activation voltage associated with the second ESD structure from the node to the ground terminal, and wherein the integrated ESD device has a negative voltage shift protection voltage that is approximately equal to an SCR activation voltage of the first ESD structure from the node to the pad terminal.
6. The integrated ESD device of claim 5 , wherein the bi-directional SCR circuit comprises a first SCR structure and a second SCR structure, the first SCR structure and the second SCR structure being configured in opposite current flow directions and each comprising a PNP-type bipolar junction transistor (BJT) and an NPN-type BJT, the PNP-type BJT having a base coupled to a collector of the NPN-type BJT and the NPN-type BJT having a base coupled to a collector of the PNP-type BJT.
7. The integrated ESD device of claim 1 , wherein the second ESD structure further comprises a Zener diode having an anode coupled to the ground terminal and a cathode coupled to the first ESD structure.
8. The integrated ESD device of claim 1 , wherein the shared diffusion region comprises a deep semiconductor well formed in a substrate, each of the first ESD structure and the second ESD structure comprising a plurality of shallow semiconductor wells formed in the deep semiconductor well.
9. The integrated ESD device of claim 8 , wherein the deep semiconductor well and the substrate cooperate to provide a parasitic diode having a reverse-bias breakdown voltage characteristic that is greater than a pad-to-ground ESD activation voltage of the integrated ESD device.
10. The integrated ESD device of claim 1 , wherein the first ESD structure and the second ESD structure cooperate to provide a pad terminal to ground terminal activation voltage that is greater than about 40 volts and to provide a negative voltage shift protection voltage that prevents leakage current from the ground terminal to the pad terminal for negative shifts in voltage at a substrate of the integrated ESD device up to the negative voltage shift protection voltage, the negative voltage shift protection voltage being at least about −1 volt at the pad terminal relative to the ground terminal.
11. An integrated electrostatic discharge (ESD) device comprising:
means for providing ESD protection against an ESD event on a pad terminal of the integrated ESD device relative to a ground terminal of the integrated ESD device, the means for providing ESD protection being coupled between the ground terminal and a node;
means for providing leakage current protection against a leakage current associated with a negative voltage potential on the pad terminal relative to a substrate voltage of the integrated ESD device, the means for providing leakage current protection being coupled between the node and the pad terminal; and
shared means for providing a portion of at least one semiconductor junction in both the means for providing ESD protection and the means for providing leakage current protection.
12. The integrated ESD device of claim 11 , wherein the means for providing leakage current protection comprises first and second diodes connected in parallel between the pad terminal and the node, each of the first and second diodes having a semiconductor junction that includes the shared means.
13. The integrated ESD device of claim 11 , wherein the means for providing leakage current protection comprises a bi-directional semiconductor-controlled rectifier circuit coupled between the pad terminal and the node.
14. The integrated ESD device of claim 11 , wherein the means for providing leakage current protection comprises a Zener diode having an anode coupled to the ground terminal and a cathode coupled to the node.
15. The integrated ESD device of claim 14 , further comprising parasitic means for providing a reverse-bias breakdown voltage characteristic that is greater than a pad terminal-to-ground terminal ESD activation voltage of the integrated ESD device.
16. An integrated electrostatic discharge (ESD) device comprising:
a substrate;
a semiconductor well formed in the substrate to define a shared well;
a first plurality of doped, shallow semiconductor wells formed in the shared well to form portions of a first ESD structure, at least some first regions of the first plurality of shallow wells being coupled to a pad terminal of the integrated ESD device, and at least some second regions of the first plurality of shallow wells being coupled to a node; and
at least one second doped, shallow semiconductor well formed in the shared well to form a portion of a second ESD structure, at least one region of the at least one second shallow well being electrically coupled to a ground terminal of the integrated ESD device, another region of the at least one second shallow well being electrically coupled with the node, such that the first and second ESD structures are electrically connected in series between the pad terminal and the ground terminal.
17. The integrated ESD device of claim 16 , wherein the first ESD structure comprises a first diode and a second diode, each of the first diode and the second diode being configured such that an anode of the first diode and a cathode of the second diode are coupled to the pad terminal and a cathode of the first diode and an anode of the second diode are coupled to the node.
18. The integrated ESD device of claim 17 , wherein the integrated ESD device has a pad terminal to ground terminal ESD activation voltage that is approximately equal to a sum of a forward bias voltage of the first diode and an activation voltage of the second ESD structure from the node to the ground terminal, and wherein the integrated ESD device has a negative voltage shift protection voltage that is approximately equal to a sum of a bias voltage of the second ESD structure from the ground terminal to the node and a forward bias voltage of the second diode.
19. The integrated ESD device of claim 16 , wherein the first ESD structure is configured as a bi-directional semiconductor-controlled rectifier (SCR) circuit coupled between the pad terminal and the node, wherein the integrated ESD device has a pad terminal to ground terminal ESD activation voltage that is approximately equal to an ESD activation voltage associated with the second ESD structure from the node to the ground terminal, and wherein the integrated ESD device has a negative voltage shift protection voltage that is approximately equal to an SCR activation voltage of the first ESD structure from the node to the pad terminal.
20. The integrated ESD device of claim 16 , wherein the second ESD structure is configured as a Zener diode having an anode coupled to the ground terminal and a cathode coupled to the node.
21. The integrated ESD device of claim 16 , wherein the shared well and the substrate provide a parasitic diode having a reverse-bias breakdown voltage characteristic that is greater than a pad-to-ground ESD activation voltage of the integrated ESD device.
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US12/471,948 US7995316B2 (en) | 2006-08-04 | 2009-05-26 | Integrated ESD protection device |
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Cited By (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090242991A1 (en) * | 2008-03-27 | 2009-10-01 | Nec Electronics Corporation | Semiconductor device |
US20100155775A1 (en) * | 2008-12-23 | 2010-06-24 | International Business Machines Corporation | Design Structure and Method for an Electrostatic Discharge (ESD) Silicon Controlled Rectifier (SCR) Structure |
US20100177554A1 (en) * | 2008-10-20 | 2010-07-15 | Seagate Technology Llc | Bipolar cmos select device for resistive sense memory |
US20100210095A1 (en) * | 2008-11-07 | 2010-08-19 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US20110007546A1 (en) * | 2009-07-13 | 2011-01-13 | Seagate Technology Llc | Anti-Parallel Diode Structure and Method of Fabrication |
US20110006276A1 (en) * | 2009-07-13 | 2011-01-13 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
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US20110058409A1 (en) * | 2008-10-20 | 2011-03-10 | Seagate Technology Llc | Mram diode array and access method |
US20110068364A1 (en) * | 2009-09-21 | 2011-03-24 | International Business Machines Corporation | Bidirectional electrostatic discharge protection structure for high voltage applications |
US7936023B1 (en) * | 2006-09-26 | 2011-05-03 | Cypress Semiconductor Corporation | High voltage diode |
US7974119B2 (en) | 2008-07-10 | 2011-07-05 | Seagate Technology Llc | Transmission gate-based spin-transfer torque memory unit |
US8110878B2 (en) * | 2008-05-09 | 2012-02-07 | Renesas Electronics Corporation | Semiconductor device having a plurality of shallow wells |
US8159856B2 (en) | 2009-07-07 | 2012-04-17 | Seagate Technology Llc | Bipolar select device for resistive sense memory |
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US8178864B2 (en) | 2008-11-18 | 2012-05-15 | Seagate Technology Llc | Asymmetric barrier diode |
US8203869B2 (en) | 2008-12-02 | 2012-06-19 | Seagate Technology Llc | Bit line charge accumulation sensing for resistive changing memory |
US20130049067A1 (en) * | 2011-08-31 | 2013-02-28 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method for the same and esd circuit |
US20130128399A1 (en) * | 2011-11-22 | 2013-05-23 | Micron Technology, Inc. | Apparatuses, circuits, and methods for protection circuits for dual-direction nodes |
US8648426B2 (en) | 2010-12-17 | 2014-02-11 | Seagate Technology Llc | Tunneling transistors |
US8946766B2 (en) * | 2013-02-27 | 2015-02-03 | International Business Machines Corporation | Bi-directional silicon controlled rectifier structure |
KR101489328B1 (en) * | 2008-03-13 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | ESD protection device having a stack type SCR with high holding voltage |
KR101492861B1 (en) * | 2013-08-05 | 2015-02-12 | 서울대학교산학협력단 | Semiconductor device and method for fabricating thereof |
US20150137305A1 (en) * | 2007-05-24 | 2015-05-21 | Infineon Technologies Ag | Protective structure and method for producing a protective structure |
US9929142B2 (en) | 2015-03-04 | 2018-03-27 | Analog Devices, Inc. | Apparatus and methods for overvoltage switches with active leakage current compensation |
US20180348428A1 (en) * | 2017-06-06 | 2018-12-06 | Sifotonics Technologies Co., Ltd. | Silicon Photonic Integrated Circuit With Electrostatic Discharge Protection |
US20190164951A1 (en) * | 2017-11-24 | 2019-05-30 | Upi Semiconductor Corporation | Transient voltage suppressor |
US20190165089A1 (en) * | 2017-11-24 | 2019-05-30 | Upi Semiconductor Corporation | Transient voltage suppressor |
US10424950B2 (en) | 2015-05-14 | 2019-09-24 | Texas Instruments Incorporated | USB controller ESD protection apparatus and method |
US11181966B2 (en) | 2015-11-13 | 2021-11-23 | Texas Instruments Incorporated | USB interface circuit and method for low power operation |
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US20220254771A1 (en) * | 2021-02-05 | 2022-08-11 | Macronix International Co., Ltd. | Semiconductor circuit and manufacturing method for the same |
TWI792915B (en) * | 2022-01-11 | 2023-02-11 | 晶焱科技股份有限公司 | Bidirectional electrostatic discharge (esd) protection device |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7910951B2 (en) * | 2008-06-18 | 2011-03-22 | National Semiconductor Corporation | Low side zener reference voltage extended drain SCR clamps |
US9520486B2 (en) | 2009-11-04 | 2016-12-13 | Analog Devices, Inc. | Electrostatic protection device |
US8455950B2 (en) | 2010-06-04 | 2013-06-04 | Texas Instruments Incorporated | ESD diode with PSD partially overlying P-Epi circumferential of PSD |
US8432651B2 (en) | 2010-06-09 | 2013-04-30 | Analog Devices, Inc. | Apparatus and method for electronic systems reliability |
US8665571B2 (en) | 2011-05-18 | 2014-03-04 | Analog Devices, Inc. | Apparatus and method for integrated circuit protection |
US8416543B2 (en) * | 2010-07-08 | 2013-04-09 | Analog Devices, Inc. | Apparatus and method for electronic circuit protection |
US8553380B2 (en) | 2010-07-08 | 2013-10-08 | Analog Devices, Inc. | Apparatus and method for electronic circuit protection |
US8587073B2 (en) * | 2010-10-15 | 2013-11-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | High voltage resistor |
US10199482B2 (en) | 2010-11-29 | 2019-02-05 | Analog Devices, Inc. | Apparatus for electrostatic discharge protection |
US8466489B2 (en) | 2011-02-04 | 2013-06-18 | Analog Devices, Inc. | Apparatus and method for transient electrical overstress protection |
US8592860B2 (en) | 2011-02-11 | 2013-11-26 | Analog Devices, Inc. | Apparatus and method for protection of electronic circuits operating under high stress conditions |
US8536012B2 (en) | 2011-07-06 | 2013-09-17 | International Business Machines Corporation | Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases |
US8680620B2 (en) | 2011-08-04 | 2014-03-25 | Analog Devices, Inc. | Bi-directional blocking voltage protection devices and methods of forming the same |
US8901647B2 (en) * | 2011-12-08 | 2014-12-02 | Infineon Technologies Ag | Semiconductor device including first and second semiconductor elements |
US8530964B2 (en) * | 2011-12-08 | 2013-09-10 | Infineon Technologies Ag | Semiconductor device including first and second semiconductor elements |
US8947841B2 (en) | 2012-02-13 | 2015-02-03 | Analog Devices, Inc. | Protection systems for integrated circuits and methods of forming the same |
US8829570B2 (en) | 2012-03-09 | 2014-09-09 | Analog Devices, Inc. | Switching device for heterojunction integrated circuits and methods of forming the same |
US8946822B2 (en) | 2012-03-19 | 2015-02-03 | Analog Devices, Inc. | Apparatus and method for protection of precision mixed-signal electronic circuits |
US8610251B1 (en) | 2012-06-01 | 2013-12-17 | Analog Devices, Inc. | Low voltage protection devices for precision transceivers and methods of forming the same |
US8637899B2 (en) | 2012-06-08 | 2014-01-28 | Analog Devices, Inc. | Method and apparatus for protection and high voltage isolation of low voltage communication interface terminals |
US8692289B2 (en) * | 2012-07-25 | 2014-04-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fast turn on silicon controlled rectifiers for ESD protection |
US9331470B1 (en) | 2012-10-10 | 2016-05-03 | Reliance Controls Corporation | Line side circuit protection system |
US8796729B2 (en) | 2012-11-20 | 2014-08-05 | Analog Devices, Inc. | Junction-isolated blocking voltage devices with integrated protection structures and methods of forming the same |
US9093491B2 (en) | 2012-12-05 | 2015-07-28 | International Business Machines Corporation | Bipolar junction transistors with reduced base-collector junction capacitance |
US8860080B2 (en) | 2012-12-19 | 2014-10-14 | Analog Devices, Inc. | Interface protection device with integrated supply clamp and method of forming the same |
US9006781B2 (en) | 2012-12-19 | 2015-04-14 | Analog Devices, Inc. | Devices for monolithic data conversion interface protection and methods of forming the same |
US9123540B2 (en) | 2013-01-30 | 2015-09-01 | Analog Devices, Inc. | Apparatus for high speed signal processing interface |
US8956945B2 (en) | 2013-02-04 | 2015-02-17 | International Business Machines Corporation | Trench isolation for bipolar junction transistors in BiCMOS technology |
US9275991B2 (en) | 2013-02-13 | 2016-03-01 | Analog Devices, Inc. | Apparatus for transceiver signal isolation and voltage clamp |
US9136693B1 (en) | 2013-02-26 | 2015-09-15 | Reliance Controls Corporation | Generator with selectively bonded neutral connection |
US9147677B2 (en) | 2013-05-16 | 2015-09-29 | Analog Devices Global | Dual-tub junction-isolated voltage clamp devices for protecting low voltage circuitry connected between high voltage interface pins and methods of forming the same |
US9171832B2 (en) | 2013-05-24 | 2015-10-27 | Analog Devices, Inc. | Analog switch with high bipolar blocking voltage in low voltage CMOS process |
US9484739B2 (en) | 2014-09-25 | 2016-11-01 | Analog Devices Global | Overvoltage protection device and method |
US9478608B2 (en) | 2014-11-18 | 2016-10-25 | Analog Devices, Inc. | Apparatus and methods for transceiver interface overvoltage clamping |
US10068894B2 (en) | 2015-01-12 | 2018-09-04 | Analog Devices, Inc. | Low leakage bidirectional clamps and methods of forming the same |
US10181719B2 (en) | 2015-03-16 | 2019-01-15 | Analog Devices Global | Overvoltage blocking protection device |
US9673187B2 (en) | 2015-04-07 | 2017-06-06 | Analog Devices, Inc. | High speed interface protection apparatus |
US9831233B2 (en) | 2016-04-29 | 2017-11-28 | Analog Devices Global | Apparatuses for communication systems transceiver interfaces |
US10734806B2 (en) | 2016-07-21 | 2020-08-04 | Analog Devices, Inc. | High voltage clamps with transient activation and activation release control |
US9748339B1 (en) * | 2017-01-06 | 2017-08-29 | Vanguard International Semiconductor Corporation | Semiconductor device and method for fabricating the same |
US10600775B2 (en) | 2017-05-02 | 2020-03-24 | Macronix International Co., Ltd. | Electrostatic discharge protection device |
US10249609B2 (en) | 2017-08-10 | 2019-04-02 | Analog Devices, Inc. | Apparatuses for communication systems transceiver interfaces |
US10037988B1 (en) * | 2017-08-24 | 2018-07-31 | Globalfoundries Singapore Pte. Ltd. | High voltage PNP using isolation for ESD and method for producing the same |
US10700056B2 (en) | 2018-09-07 | 2020-06-30 | Analog Devices, Inc. | Apparatus for automotive and communication systems transceiver interfaces |
US11387648B2 (en) | 2019-01-10 | 2022-07-12 | Analog Devices International Unlimited Company | Electrical overstress protection with low leakage current for high voltage tolerant high speed interfaces |
US11101264B2 (en) | 2019-08-14 | 2021-08-24 | Nxp B.V. | Electrostatic discharge protection circuit and structure thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780905A (en) * | 1996-12-17 | 1998-07-14 | Texas Instruments Incorporated | Asymmetrical, bidirectional triggering ESD structure |
US20040026728A1 (en) * | 2002-05-21 | 2004-02-12 | Kazuhiko Yoshida | Semiconductor device and combined IC using the same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5225702A (en) * | 1991-12-05 | 1993-07-06 | Texas Instruments Incorporated | Silicon controlled rectifier structure for electrostatic discharge protection |
US6610262B1 (en) * | 2002-03-04 | 2003-08-26 | Taiwan Semiconductor Manufacturing Company | Depletion mode SCR for low capacitance ESD input protection |
US7285458B2 (en) * | 2004-02-11 | 2007-10-23 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an ESD protection circuit |
-
2006
- 2006-08-04 US US11/499,576 patent/US20080029782A1/en not_active Abandoned
-
2007
- 2007-08-06 WO PCT/US2007/075246 patent/WO2008019332A2/en active Application Filing
-
2009
- 2009-05-26 US US12/471,948 patent/US7995316B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5780905A (en) * | 1996-12-17 | 1998-07-14 | Texas Instruments Incorporated | Asymmetrical, bidirectional triggering ESD structure |
US20040026728A1 (en) * | 2002-05-21 | 2004-02-12 | Kazuhiko Yoshida | Semiconductor device and combined IC using the same |
Cited By (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7936023B1 (en) * | 2006-09-26 | 2011-05-03 | Cypress Semiconductor Corporation | High voltage diode |
US20150137305A1 (en) * | 2007-05-24 | 2015-05-21 | Infineon Technologies Ag | Protective structure and method for producing a protective structure |
US9177950B2 (en) * | 2007-05-24 | 2015-11-03 | Infineon Technologies Ag | Protective structure and method for producing a protective structure |
KR101489328B1 (en) * | 2008-03-13 | 2015-02-06 | 페어차일드코리아반도체 주식회사 | ESD protection device having a stack type SCR with high holding voltage |
US8008723B2 (en) * | 2008-03-27 | 2011-08-30 | Renesas Electronics Corporation | Semiconductor device including a plurality of diffusion layers and diffusion resistance layer |
US20090242991A1 (en) * | 2008-03-27 | 2009-10-01 | Nec Electronics Corporation | Semiconductor device |
US8110878B2 (en) * | 2008-05-09 | 2012-02-07 | Renesas Electronics Corporation | Semiconductor device having a plurality of shallow wells |
US7974119B2 (en) | 2008-07-10 | 2011-07-05 | Seagate Technology Llc | Transmission gate-based spin-transfer torque memory unit |
US8199563B2 (en) | 2008-07-10 | 2012-06-12 | Seagate Technology Llc | Transmission gate-based spin-transfer torque memory unit |
US8416615B2 (en) | 2008-07-10 | 2013-04-09 | Seagate Technology Llc | Transmission gate-based spin-transfer torque memory unit |
US9030867B2 (en) | 2008-10-20 | 2015-05-12 | Seagate Technology Llc | Bipolar CMOS select device for resistive sense memory |
US20110058409A1 (en) * | 2008-10-20 | 2011-03-10 | Seagate Technology Llc | Mram diode array and access method |
US20100177554A1 (en) * | 2008-10-20 | 2010-07-15 | Seagate Technology Llc | Bipolar cmos select device for resistive sense memory |
US8514605B2 (en) | 2008-10-20 | 2013-08-20 | Seagate Technology Llc | MRAM diode array and access method |
US7936580B2 (en) | 2008-10-20 | 2011-05-03 | Seagate Technology Llc | MRAM diode array and access method |
US8289746B2 (en) | 2008-10-20 | 2012-10-16 | Seagate Technology Llc | MRAM diode array and access method |
US20110058404A1 (en) * | 2008-10-30 | 2011-03-10 | Seagate Technology Llc | Variable resistive memory punchthrough access method |
US8098510B2 (en) | 2008-10-30 | 2012-01-17 | Seagate Technology Llc | Variable resistive memory punchthrough access method |
US8508981B2 (en) | 2008-10-30 | 2013-08-13 | Seagate Technology Llc | Apparatus for variable resistive memory punchthrough access method |
US20110156115A1 (en) * | 2008-10-30 | 2011-06-30 | Seagate Technology Llc | Apparatus for variable resistive memory punchthrough access method |
US7936583B2 (en) | 2008-10-30 | 2011-05-03 | Seagate Technology Llc | Variable resistive memory punchthrough access method |
US8199558B2 (en) | 2008-10-30 | 2012-06-12 | Seagate Technology Llc | Apparatus for variable resistive memory punchthrough access method |
US20110026307A1 (en) * | 2008-10-30 | 2011-02-03 | Seagate Technology Llc | Variable resistive memory punchthrough access method |
US7961497B2 (en) | 2008-10-30 | 2011-06-14 | Seagate Technology Llc | Variable resistive memory punchthrough access method |
US8072014B2 (en) | 2008-11-07 | 2011-12-06 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US20110032748A1 (en) * | 2008-11-07 | 2011-02-10 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US8508980B2 (en) | 2008-11-07 | 2013-08-13 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US20100210095A1 (en) * | 2008-11-07 | 2010-08-19 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US7935619B2 (en) | 2008-11-07 | 2011-05-03 | Seagate Technology Llc | Polarity dependent switch for resistive sense memory |
US8178864B2 (en) | 2008-11-18 | 2012-05-15 | Seagate Technology Llc | Asymmetric barrier diode |
US8638597B2 (en) | 2008-12-02 | 2014-01-28 | Seagate Technology Llc | Bit line charge accumulation sensing for resistive changing memory |
US8203869B2 (en) | 2008-12-02 | 2012-06-19 | Seagate Technology Llc | Bit line charge accumulation sensing for resistive changing memory |
US8373267B2 (en) | 2008-12-23 | 2013-02-12 | International Business Machines Corporation | Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure |
US9029206B2 (en) | 2008-12-23 | 2015-05-12 | International Business Machines Corporation | Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure |
US8637900B2 (en) | 2008-12-23 | 2014-01-28 | International Business Machines Corporation | Electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure |
US20100155775A1 (en) * | 2008-12-23 | 2010-06-24 | International Business Machines Corporation | Design Structure and Method for an Electrostatic Discharge (ESD) Silicon Controlled Rectifier (SCR) Structure |
US8039868B2 (en) * | 2008-12-23 | 2011-10-18 | International Business Machines Corporation | Structure and method for an electrostatic discharge (ESD) silicon controlled rectifier (SCR) structure |
US8514608B2 (en) | 2009-07-07 | 2013-08-20 | Seagate Technology Llc | Bipolar select device for resistive sense memory |
US8159856B2 (en) | 2009-07-07 | 2012-04-17 | Seagate Technology Llc | Bipolar select device for resistive sense memory |
US8158964B2 (en) | 2009-07-13 | 2012-04-17 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
US7911833B2 (en) * | 2009-07-13 | 2011-03-22 | Seagate Technology Llc | Anti-parallel diode structure and method of fabrication |
US20110006276A1 (en) * | 2009-07-13 | 2011-01-13 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
US8198181B1 (en) | 2009-07-13 | 2012-06-12 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
US20110122678A1 (en) * | 2009-07-13 | 2011-05-26 | Seagate Technology Llc | Anti-Parallel Diode Structure and Method of Fabrication |
US8288749B2 (en) | 2009-07-13 | 2012-10-16 | Seagate Technology Llc | Schottky diode switch and memory units containing the same |
US20110007546A1 (en) * | 2009-07-13 | 2011-01-13 | Seagate Technology Llc | Anti-Parallel Diode Structure and Method of Fabrication |
US8203875B2 (en) | 2009-07-13 | 2012-06-19 | Seagate Technology Llc | Anti-parallel diode structure and method of fabrication |
US20110068364A1 (en) * | 2009-09-21 | 2011-03-24 | International Business Machines Corporation | Bidirectional electrostatic discharge protection structure for high voltage applications |
US7968908B2 (en) | 2009-09-21 | 2011-06-28 | International Business Machines Corporation | Bidirectional electrostatic discharge protection structure for high voltage applications |
US8648426B2 (en) | 2010-12-17 | 2014-02-11 | Seagate Technology Llc | Tunneling transistors |
US8648386B2 (en) * | 2011-08-31 | 2014-02-11 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method for the same and ESD circuit |
US20140106532A1 (en) * | 2011-08-31 | 2014-04-17 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method for the same and esd circuit |
US8878241B2 (en) * | 2011-08-31 | 2014-11-04 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method for the same and ESD circuit |
US20130049067A1 (en) * | 2011-08-31 | 2013-02-28 | Macronix International Co., Ltd. | Semiconductor structure and manufacturing method for the same and esd circuit |
US9391062B2 (en) * | 2011-11-22 | 2016-07-12 | Micron Technology, Inc. | Apparatuses, circuits, and methods for protection circuits for dual-direction nodes |
US20130128399A1 (en) * | 2011-11-22 | 2013-05-23 | Micron Technology, Inc. | Apparatuses, circuits, and methods for protection circuits for dual-direction nodes |
CN102437156A (en) * | 2011-12-13 | 2012-05-02 | 杭州士兰集成电路有限公司 | Ultralow capacitance transient voltage suppression device and manufacturing method thereof |
US8946766B2 (en) * | 2013-02-27 | 2015-02-03 | International Business Machines Corporation | Bi-directional silicon controlled rectifier structure |
KR101492861B1 (en) * | 2013-08-05 | 2015-02-12 | 서울대학교산학협력단 | Semiconductor device and method for fabricating thereof |
US10269665B2 (en) | 2013-08-05 | 2019-04-23 | Seoul National University R&Db Foundation | Semiconductor device for sensor application using contacts located on top surface and bottom surface and method for fabricating thereof |
US10629503B2 (en) | 2013-08-05 | 2020-04-21 | Seoul National University R&Db Foundation | Semiconductor device containing integrated circuit communicating with external apparatus via two terminals |
WO2015020392A1 (en) * | 2013-08-05 | 2015-02-12 | 서울대학교산학협력단 | Semiconductor device and method for manufacturing same |
US9929142B2 (en) | 2015-03-04 | 2018-03-27 | Analog Devices, Inc. | Apparatus and methods for overvoltage switches with active leakage current compensation |
US10424950B2 (en) | 2015-05-14 | 2019-09-24 | Texas Instruments Incorporated | USB controller ESD protection apparatus and method |
US11181966B2 (en) | 2015-11-13 | 2021-11-23 | Texas Instruments Incorporated | USB interface circuit and method for low power operation |
US10578800B2 (en) * | 2017-06-06 | 2020-03-03 | Sifotonics Technologies Co., Ltd. | Silicon photonic integrated circuit with electrostatic discharge protection mechanism for static electric shocks |
US20180348428A1 (en) * | 2017-06-06 | 2018-12-06 | Sifotonics Technologies Co., Ltd. | Silicon Photonic Integrated Circuit With Electrostatic Discharge Protection |
US10580764B2 (en) * | 2017-11-24 | 2020-03-03 | Upi Semiconductor Corp. | Transient voltage suppressor |
US20190165089A1 (en) * | 2017-11-24 | 2019-05-30 | Upi Semiconductor Corporation | Transient voltage suppressor |
US10607983B2 (en) * | 2017-11-24 | 2020-03-31 | Upi Semiconductor Corp. | Transient voltage suppressor |
US20190164951A1 (en) * | 2017-11-24 | 2019-05-30 | Upi Semiconductor Corporation | Transient voltage suppressor |
TWI733957B (en) * | 2017-11-24 | 2021-07-21 | 源芯半導體股份有限公司 | Transient voltage suppressor |
US20220254771A1 (en) * | 2021-02-05 | 2022-08-11 | Macronix International Co., Ltd. | Semiconductor circuit and manufacturing method for the same |
CN114374196A (en) * | 2021-12-24 | 2022-04-19 | 芯耀辉科技有限公司 | Electrostatic protection clamping circuit, interface module and electronic equipment |
TWI792915B (en) * | 2022-01-11 | 2023-02-11 | 晶焱科技股份有限公司 | Bidirectional electrostatic discharge (esd) protection device |
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US20090230426A1 (en) | 2009-09-17 |
US7995316B2 (en) | 2011-08-09 |
WO2008019332A3 (en) | 2016-06-09 |
WO2008019332A2 (en) | 2008-02-14 |
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