Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS20080029792 A1
Publication typeApplication
Application numberUS 11/905,746
Publication dateFeb 7, 2008
Filing dateOct 3, 2007
Priority dateDec 29, 2004
Also published asCN1819242A, CN100466279C, DE102005062952A1, DE102005062952B4, US7294522, US20060138471
Publication number11905746, 905746, US 2008/0029792 A1, US 2008/029792 A1, US 20080029792 A1, US 20080029792A1, US 2008029792 A1, US 2008029792A1, US-A1-20080029792, US-A1-2008029792, US2008/0029792A1, US2008/029792A1, US20080029792 A1, US20080029792A1, US2008029792 A1, US2008029792A1
InventorsHee Shim
Original AssigneeShim Hee S
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Cmos image sensor and method for fabricating the same
US 20080029792 A1
Abstract
A CMOS image sensor and a method for fabricating the same are disclosed, in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth. The CMOS image sensor includes a first conductive type semiconductor substrate, a second conductive type impurity ion area, a gate electrode, an insulating film formed on an entire surface of the semiconductor substrate including the gate electrode and excluding the second conductive type impurity ion area, and a silicon epitaxial layer formed on the second conductive type impurity ion area and doped with first conductive type impurity ions.
Images(16)
Previous page
Next page
Claims(8)
1. A CMOS image sensor comprising:
a first conductive type semiconductor substrate defined by a photodiode area and a transistor area;
a second conductive type impurity ion area formed in the semiconductor substrate of the photodiode area;
a gate electrode formed on the semiconductor substrate of the transistor area;
an insulating film formed on an entire surface of the semiconductor substrate including the gate electrode and excluding the second conductive type impurity ion area; and
a silicon epitaxial layer formed on the second conductive type impurity ion area and doped with first conductive type impurity ions.
2. The CMOS image sensor of claim 1, wherein the silicon epitaxial layer is formed on the second conductive type impurity ion area using a selective epitaxial growth process.
3. The CMOS image sensor of claim 1, wherein the gate electrode is isolated from the silicon epitaxial layer by the insulating film formed at sidewalls of the gate electrode.
4. The CMOS image sensor of claim 1, further comprising spacers formed at sidewalls of the gate electrode.
5. The CMOS image sensor of claim 4, wherein the spacers formed at the sidewalls of the gate electrode are adjacent to the silicon epitaxial layer and are formed on the silicon epitaxial layer at the sidewalls of the gate electrode.
6. The CMOS image sensor of claim 1, wherein the silicon epitaxial layer is higher than the surface of the semiconductor substrate below the gate electrode.
7. The CMOS image sensor of claim 1, further comprising a first conductive type impurity ion area formed on surfaces of the photodiode area and the transistor area.
8-12. (canceled)
Description
  • [0001]
    This application claims the benefit of Korean Patent Application No. 10-2004-114784, filed on Dec. 29, 2004, which is hereby incorporated by reference for all purposes as if fully set forth herein.
  • BACKGROUND OF THE INVENTION
  • [0002]
    1. Field of the Invention
  • [0003]
    The present invention relates to a complementary metal-oxide semiconductor (CMOS) image sensor and a method for fabricating the same, and more particularly, to a CMOS image sensor and a method for fabricating the same in which a dead zone and a dark current are simultaneously reduced.
  • [0004]
    2. Discussion of the Related Art
  • [0005]
    Generally, an image sensor is a semiconductor device that converts optical images to electrical signals. The image sensor can be classified as a charge coupled device (CCD) and a CMOS image sensor.
  • [0006]
    The CCD has drawbacks in its fabricating process because of a complicated driving mode, high power consumption, and multistage photolithographic processes. Also, it is difficult for a control circuit, a signal processing circuit, and an analog-to-digital converter to be integrated in a CCD chip. Thus, the CCD is not suitable for use in slim sized products. However, CMOS image sensors have received attention as the next generation technology for overcoming the drawbacks of CCDs.
  • [0007]
    The CMOS image sensor employs a switching mode that sequentially detects outputs of unit pixels using MOS transistors by forming the MOS transistors to correspond to the number of the unit pixels on a semiconductor substrate. CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits is employed.
  • [0008]
    The CMOS image sensor has advantages in that power consumption is low because of the CMOS technology. Also, a fabricating process is simple because of a relatively small number of photolithographic processing steps. Further, since the CMOS image sensor allows a control circuit, a signal processing circuit and an analog-to-digital converter to be integrated in its chip, it has an advantage in that a slim sized product can be obtained. Therefore, the CMOS image sensor is widely used for various application fields such as digital still cameras and digital video cameras.
  • [0009]
    A related art CMOS image sensor will be described with reference to FIGS. 1 and 2. FIG. 1 is a layout illustrating a unit pixel of a 4 T type CMOS image sensor including four transistors, and FIG. 2 is an equivalent circuit 100 diagram illustrating the unit pixel of the CMOS image sensor shown in FIG. 1.
  • [0010]
    In the unit pixel of the 4 T type CMOS image sensor, as shown in FIGS. 1 and 2, a photodiode (PD) 20 is formed in a wide portion of an active area 10, and gate electrodes 110, 120, 130, and 140 of four transistors, are formed to respectively overlap the other portions of the active area 10. A transfer transistor Tx, a reset transistor Rx, a drive transistor Dx, and a selection transistor Sx are respectively formed by the gate electrodes 110, 120, 130 and 140.
  • [0011]
    Impurity ions are implanted into the active area 10 of each transistor except portions below the gate electrodes 110, 120, 130 and 140, so that source and drain areas of each transistor are formed. Thus, a power voltage Vdd is applied to the source and drain areas between the reset transistor Rx and the drive transistor Dx, and a power voltage Vss is applied to the source and drain areas at one side of the selection transistor Sx.
  • [0012]
    The transfer transistor Tx transfers optical charges generated by the photodiode to a floating diffusion (FD) layer. The reset transistor Rx controls and resets the potential of the floating diffusion layer. The drive transistor Dx serves as a source follower. The selection transistor Sx serves as a switching transistor to read a signal of the unit pixel.
  • [0013]
    A method for fabricating the aforementioned related art CMOS image sensor will be described with reference to FIG. 3A to FIG. 3G. FIG. 3A to FIG. 3G are sectional views taken along line I-I′ of the unit pixel of the CMOS image sensor shown in FIG. 1.
  • [0014]
    First, as shown in FIG. 3A, a lightly doped P type (P-) epitaxial layer 2 is formed on a P type semiconductor substrate 1 defined by an active area and a device isolation area using a mask. Then, the lightly doped P type epitaxial layer 2 is etched at a predetermined depth by exposing and developing processes using the mask to form a trench. An oxide film is formed on the epitaxial layer 2. The trench is filled with the oxide film by a chemical mechanical polishing (CMP) process so as to form a device isolation film 3 in the device isolation area.
  • [0015]
    Impurity ions are implanted into the surface of the epitaxial layer 2 to correspond to the active area to form a P type impurity ion area 4. The P type impurity ion area 4 is used to control a threshold voltage in a channel area of the transfer transistor and to pin a surface voltage in the photodiode.
  • [0016]
    As shown in FIG. 3B, a gate insulating film and a conductive layer are sequentially formed on the entire surface of the substrate and then selectively dry-etched to form a gate insulating film 5 and a gate electrode 6 of each transistor including the transfer transistor.
  • [0017]
    As shown in FIG. 3C, an insulating film 7 such as an oxide film is formed on the entire surface of the substrate including the gate electrode 6 to recover a damaged corner of the gate insulating film 5 and protect the surface of the epitaxial layer 2 during a later ion implantation process.
  • [0018]
    As shown in FIG. 3D, a photoresist film is coated on the entire surface and then removed by exposing and developing processes to form a photoresist pattern 8 that exposes the photodiode. The photoresist pattern 8 is formed to partially cover the active area adjacent the device isolation film 3 and to partially expose the gate electrode 6. N type impurity ions are implanted into the epitaxial layer 2 of the exposed photodiode by high energy ion implantation to form a photodiode N type impurity ion area 9.
  • [0019]
    As shown in FIG. 3E, after the photoresist pattern 8 is removed, a photoresist pattern 10 is formed to expose the photodiode. P type impurity ions are implanted into the surface of the photodiode N type impurity ion area 9 to form a P type impurity ion area 11. The P type impurity ion area 11 has a doping level obtained by adding a doping level of the P type impurity ion area 4 thereto.
  • [0020]
    Instead of the process shown in FIG. 3E, as shown in FIG. 3F, an insulating film may be deposited on the entire surface and then removed by an anisotropic etching process to form spacers 12 at sidewalls of the gate electrode 6. After the photoresist pattern 10 is formed to expose the photodiode, P type impurity ions may be implanted into the surface of the photodiode N type impurity ion area 9 to form the P type impurity ion area 11.
  • [0021]
    As shown in FIG. 3G, the photoresist pattern 10 is removed, and N type impurity ions are heavily implanted into the drain area at one side of the gate electrode 6 using a mask to form a heavily doped N type impurity ion area 13.
  • [0022]
    In the related art CMOS image sensor, the photodiode converts signals of light into electrical signals to generate optical charges. The generated optical charges move to the floating diffusion layer so as to gate the drive transistor Dx if the transfer transistor Tx is turned on. However, as shown in FIG. 3E, if the P type impurity ions are implanted before the spacers are formed, the epitaxial layer below the spacers is pinned. Characteristics of a dark current may be improved but the P type impurity ion doping level increases. As the P type impurity ion doping level increases, a potential barrier of the source area of the transfer transistor increases to reduce transfer efficiency of the optical charges. A problem then occurs in that a dead zone is formed. In the dead zone no signal is generated for a certain time period after light enters the sensor.
  • [0023]
    Furthermore, as shown in FIG. 3F, if the P type impurity ions are implanted after the spacers are formed at the sidewalls of the gate electrode, transfer efficiency of the optical charges may be improved. However, the surface of the photodiode is damaged during the dry-etching process that forms the spacers. Dark current is thereby increased.
  • SUMMARY OF THE INVENTION
  • [0024]
    Accordingly, the present invention is directed to a CMOS image sensor and a method for fabricating the same that substantially obviates one or more problems due to limitations and disadvantages of the related art.
  • [0025]
    An advantage of the present invention is to provide a CMOS image sensor and a method for fabricating the same in which a dead zone and a dark current are simultaneously reduced by selective epitaxial growth.
  • [0026]
    Additional features and advantages of the invention will be set forth in the description which follows, and will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure and method particularly pointed out in the written description and claims hereof as well as the appended drawings.
  • [0027]
    To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, a CMOS image sensor includes a first conductive type semiconductor substrate defined by a photodiode area and a transistor area, a second conductive type impurity ion area formed in the semiconductor substrate of the photodiode area, a gate electrode formed on the semiconductor substrate of the transistor area, an insulating film formed on an entire surface of the semiconductor substrate including the gate electrode and excluding the second conductive type impurity ion area, and a silicon epitaxial layer formed on the second conductive type impurity ion area and doped with first conductive type impurity ions.
  • [0028]
    In another aspect of the present invention, a method for fabricating a CMOS image sensor includes forming a first conductive type first impurity ion area in an active area of a semiconductor substrate defined by the active area and a field area, forming a gate electrode on a transistor area of the active area, forming an insulating film on an entire surface of the semiconductor substrate including the gate electrode, forming a second conductive type impurity ion area in a photodiode area of the active area, selectively removing the insulating film on the second conductive type impurity ion area, growing a silicon epitaxial layer on a surface of the second conductive type impurity ion area, and forming a first conductive type second impurity ion area in the silicon epitaxial layer.
  • [0029]
    It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0030]
    The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiment(s) of the invention and together with the description serve to explain the principles of the invention. In the drawings:
  • [0031]
    FIG. 1 is a layout illustrating a unit pixel of a 4 T type CMOS image sensor including four transistors according to the related art;
  • [0032]
    FIG. 2 is an equivalent circuit diagram illustrating the unit pixel of the CMOS image sensor shown in FIG. 1;
  • [0033]
    FIG. 3A to FIG. 3G are sectional views of a CMOS image sensor fabricated by a method according to related art methods; and
  • [0034]
    FIG. 4A to FIG. 4H are sectional views of a CMOS image sensor fabricated by a method according to an exemplary embodiment of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0035]
    Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts.
  • [0036]
    As shown in FIG. 4A, a lightly doped P type (P-) epitaxial layer 32 is formed on a P type semiconductor substrate 31 defined by an active area and a device isolation area using a mask. Then, the lightly doped P type epitaxial layer 32 is etched at a predetermined depth by exposing and developing processes using the mask to form a trench. An oxide film is formed on the substrate so that the trench is filled with the oxide film. The oxide film is patterned by a chemical mechanical polishing (CMP) process to remain in the trench, so that a device isolation film 33 is formed in the device isolation area.
  • [0037]
    Impurity ions are implanted into a surface of the epitaxial layer 32 corresponding to the active area so as to form a P type impurity ion area 34. The P type impurity ion area 34 is used to control a threshold voltage in a channel area of a transfer transistor and to pin a surface voltage in a photodiode area.
  • [0038]
    As shown in FIG. 4B, a gate insulating film and a conductive layer are sequentially formed on the entire surface of the substrate and then selectively dry-etched to form a gate insulating film 35 and a gate electrode 36 of each transistor including the transfer transistor.
  • [0039]
    As shown in FIG. 4C, an insulating film 37, such as an oxide film, is formed on the entire surface of the substrate including the gate electrode 36 to recover a damaged corner of the gate insulating film 35 and to protect the surface of the epitaxial layer 32 during a later ion implantation process.
  • [0040]
    As shown in FIG. 4D, a photoresist film is coated on the entire surface and then removed by exposing and developing processes to form a photoresist pattern 38 that exposes the photodiode area. The photoresist pattern 38 is formed to partially cover the active area adjacent the device isolation film 33 and the gate electrode 36. The insulating film 37 exposed from the photoresist pattern 38 is selectively removed by a wet-etching process. The insulating film 37 at sidewalls of the gate electrode 36 and on the gate electrode 36 may not removed. Then, N type impurity ions are implanted into the epitaxial layer 32 of the exposed photodiode area by high energy ion implantation to form an N type impurity ion area 39 in the photodiode area.
  • [0041]
    As shown in FIG. 4E, after the photoresist pattern 38 is removed, a silicon epitaxial layer 40 is grown using a selective epitaxial growth process on the surface of the photodiode area from which the insulating film 37 is removed. The silicon epitaxial layer 40 is electrically isolated from the gate electrode 36 by the insulating film 37.
  • [0042]
    As shown in FIG. 4F, a photoresist film 42 is coated on the entire surface and then patterned by exposing and developing processes to expose the photodiode area. P type impurity ions are implanted into the silicon epitaxial layer 40 to form a P type impurity ion area 41 using the patterned photoresist film 42 as a mask.
  • [0043]
    As shown in FIG. 4G, after the photoresist film 42 is removed, an insulating film is deposited on the entire surface and then removed by an anisotropic etching process to form spacers 43 at the sidewalls of the gate electrode 36.
  • [0044]
    As shown in FIG. 4H, N type impurity ions are heavily implanted into a drain area at one side of the gate electrode 36 using a mask to form a heavily doped N type impurity ion area 44.
  • [0045]
    In the CMOS image sensor according to an exemplary embodiment of present invention, the P type epitaxial layer 32 defined by the photodiode area and a transistor area is provided to form the N type impurity ion area 39 in the photodiode area of the P type epitaxial layer 32. The silicon epitaxial layer 41, into which the P type impurity ions are implanted, is selectively formed on the P type epitaxial layer 32 of the photodiode area. The gate insulating film 35 and the gate electrode 36 are formed on the P type epitaxial layer 32 of the transistor area, and the P type impurity ion area 34 is formed in the P type epitaxial layer 32 below the gate electrode 36.
  • [0046]
    The silicon epitaxial layer 41 into which the P type impurity ions are implanted is isolated from the gate electrode 36 by the insulating film 37. The spacers 43 are formed at the sidewalls of the gate electrode 36 on the silicon epitaxial layer 41 into which the P type impurity ions are implanted.
  • [0047]
    As described above, the CMOS image sensor and the method for fabricating the same have the following advantages. Since the P type impurity ion area shown in FIG. 4A is extended to the portion below the spacers of the transfer transistor, it is possible to reduce the dark current of the image sensor. In addition, since the silicon epitaxial layer is formed on the surface of the photodiode area using the selective epitaxial growth process and the P type impurity ion area is formed on the silicon epitaxial layer to pin the surface voltage of the photodiode area, the P type impurity ion area of the photodiode area is higher than the channel area of the transfer transistor. The potential barrier in the source area of the transfer transistor does not increase, and transfer efficiency of the optical charges can be improved.
  • [0048]
    It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US7420207 *Dec 19, 2005Sep 2, 2008Samsung Electronics Co., Ltd.Photo-detecting device and related method of formation
US20030127666 *Dec 30, 2002Jul 10, 2003Won-Ho LeeImage sensor and method for fabricating the same
US20050205904 *May 11, 2005Sep 22, 2005Sungkwon HongMethod of forming an elevated photodiode in an image sensor
US20050277239 *Jun 9, 2005Dec 15, 2005Dongbuanam Semiconductor Inc.Method for manufacturing CMOS image sensor
US20060138483 *Dec 28, 2005Jun 29, 2006Shim Hee SCMOS image sensor and method for manufacturing the same
US20060138493 *Dec 28, 2005Jun 29, 2006Shim Hee SCMOS image sensor and method for fabricating the same
US20060141692 *Dec 28, 2005Jun 29, 2006Dongbuanam Semiconductor Inc.Method of fabricating CMOS image sensor
US20070018269 *Jul 21, 2005Jan 25, 2007Omnivision Technologies, Inc.Raised silicon photodiode
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US8132334Nov 23, 2010Mar 13, 2012Leica Geosystems AgRotating construction laser with a dual grade mechanism
US8450780 *Jan 13, 2010May 28, 2013Sony CorporationSolid-state imaging sensor, method of manufacturing the same, and image pickup apparatus
US20100181602 *Jan 13, 2010Jul 22, 2010Sony CorporationSolid-state image sensor, method of manufacturing the same, and image pickup apparatus
US20110119937 *Nov 23, 2010May 26, 2011Leica Geosystems AgRotating construction laser with a dual grade mechanism
Classifications
U.S. Classification257/290, 257/E27.133, 257/E31.083
International ClassificationH01L27/146, H04N5/374, H04N5/361, H04N5/335, H04N5/369, H01L31/062
Cooperative ClassificationH01L27/14643, H01L27/14689, H01L27/1463, H01L27/14601
European ClassificationH01L27/146A12, H01L27/146V6, H01L27/146F, H01L27/146A
Legal Events
DateCodeEventDescription
Oct 3, 2007ASAssignment
Owner name: DONGBUANAM SEMICONDUCTOR INC., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SHIM, HEE SUNG;REEL/FRAME:019971/0561
Effective date: 20051227
Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: CHANGE OF NAME;ASSIGNOR:DONGBUANAM SEMICONDUCTOR INC.;REEL/FRAME:019971/0323
Effective date: 20060324