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Publication numberUS20080066039 A1
Publication typeApplication
Application numberUS 11/531,398
Publication dateMar 13, 2008
Filing dateSep 13, 2006
Priority dateSep 13, 2006
Also published asUS7469399
Publication number11531398, 531398, US 2008/0066039 A1, US 2008/066039 A1, US 20080066039 A1, US 20080066039A1, US 2008066039 A1, US 2008066039A1, US-A1-20080066039, US-A1-2008066039, US2008/0066039A1, US2008/066039A1, US20080066039 A1, US20080066039A1, US2008066039 A1, US2008066039A1
InventorsChristopher J. Berry, Christopher M. Carney, David L. Rude, Eddy St. Juste
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semi-Flattened Pin Optimization Process for Hierarchical Physical Designs
US 20080066039 A1
Abstract
In a hierarchical semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement wherein locating each input terminal provides access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access
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Claims(20)
1. In a hierarchal semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal, the improvement comprising:
locating each input terminal providing access to a single leaf cell at a legal location proximate the leaf cell to which the input terminal provides access.
2. In a hierarchal semiconductor digital unit as in claim 1 the improvement further comprising locating each input terminal providing access to a plurality of leaf cells at a legal position proximate the geometric center of said plurality of leaf cells.
3. In a hierarchal semiconductor digital unit as in claim 1 the improvement further comprising locating each output terminal providing access to a leaf cell at a legal location proximate the leaf cell to which the output terminal provides access.
4. In a hierarchal semiconductor digital unit as in claim 2 the improvement further comprising locating each output terminal providing access to a leaf cell at a legal location proximate the leaf cell to which the output terminal provides access.
5. A hierarchal semiconductor digital unit comprising in combination:
a plurality of macro functional logic blocks within a perimeter, each of said macro functional logic blocks comprised of a plurality of leaf cells, each of said leaf cells accessed via an input terminal and an output terminal;
each input terminal providing access to a single leaf cell located at a legal location inboard of said perimeter proximate the leaf cell to which the input terminal provides access.
6. A hierarchal semiconductor digital unit as in claim 5 further including each input terminal providing access to a plurality of leaf cells located at a legal location inboard of said perimeter proximate the geometric center of said plurality of leaf cells.
7. A hierarchal semiconductor digital unit as in claim 5 further including each output terminal providing access to a leaf cell located at a legal location inboard of said perimeter proximate the leaf cell to which the output terminal provides access.
8. A hierarchal semiconductor digital unit as in claim 6 further including each output terminal providing access to a leaf cell located at a legal location inboard of said perimeter proximate the leaf cell to which the output terminal provides access.
9. A hierarchal semiconductor digital unit as in claim 5 wherein said legal location is nearest the leaf cell to which the input terminal provides access.
10. A hierarchal semiconductor digital unit as in claim 6 wherein said legal location is nearest the geometric center of said plurality of leaf cells.
11. A hierarchal semiconductor digital unit as in claim 7 wherein said legal location is nearest the leaf cell to which the output terminal provides access.
12. A hierarchal semiconductor digital unit as in claim 8 wherein said legal location is nearest the leaf cell to which the output terminal provides access.
13. A method for designing a hierarchal semiconductor digital unit comprised of a plurality of macro functional logic blocks, each of said blocks comprised of leaf cells accessed via input/output pins, including the steps of
synthesizing each macro functional block without regard to location of said input/output pins;
determining a grid of legal input/output pin locations for the macro functional block synthesized in the previous step;
locating an input pin that provides access to a single leaf cell at a legal location proximate the leaf cell to which the input pin provides access.
14. A method for designing a hierarchal semiconductor digital unit as in claim 13 including the step of locating an input pin that provides access to a plurality of leaf cells at a legal position proximate the center of said plurality of leaf cells.
15. A method for designing a hierarchal semiconductor digital unit as in claim 13 including the step of locating an output pin that provides access to a leaf cell at a legal location proximate the leaf cell to which the output pin provides access.
16. A method for designing a hierarchal semiconductor digital unit as in claim 14 including the step of locating an output pin that provides access to a leaf cell at a legal location proximate the leaf cell to which the output pin provides access.
17. A method for designing a hierarchal semiconductor digital unit as in claim 13 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin location.
18. A method for designing a hierarchal semiconductor digital unit as in claim 14 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin location.
19. A method for designing a hierarchal semiconductor digital unit as in claim 15 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin locations.
20. A method for designing a hierarchal semiconductor digital unit as in claim 16 including the step eliminating re-powering circuitry resulting from the first synthesizing step made un-necessary by the pin locations.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an improved hierarchical semiconductor digital chip design and method for implementing the design, and more particularly to a chip design that optimizes pin locations for internal timing of a functional block.

2. Description of Background

Designers of the physical embodiment a semiconductor chip to carry out a logic function traditionally divide the overall chip structure into functional blocks that are small components of the overall function. These functional blocks are treated as abstractions at the top level. The first level of abstracted blocks are further divided into yet smaller physical blocks that are themselves abstracted and this process of dividing into bocks and treating them as abstracts continues until at the lowest level the content of the physical block is a reasonable small enough portion of the of the logic so that people and or programs can work with it. FIG. 1 illustrates this hierarchical approach to the design of complex digital electronic components such as computer components. A functional block referred to here as a macro is comprised of standard semiconductor circuit elements lc commonly referred to as leaf cells. These macros are combined and interconnected (not shown) to form the overall chip structure unit.

The logical functions executed by the leaf cells that make up an abstract determine the need for terminals called pins associated with the abstract along with need for points that can be connected together to form a specific network. A typical prior art design is illustrated in FIG. 2. The enclosing rectangular frame is meant to represent the abstract. The abstract can be thought of as the bounding box of the logical block. Input pins and output pins are normally placed on the edge of the abstract as shown in the FIG. 2. Leaf cells A, B, C, and D formed in the semiconductor are connected to corresponding input pins A, C, and D (input pin A serves leaf cells A and B in this illustration) and output pins A, B, C, and D. These connection points to the leaf cells called pins are usually placed around the peripheral border of an abstract, usually on the side or corner or combination thereof that results in the shortest distance to the next pin in the same network in a manner similar to how one would construct a logical flow diagram. However, this prior art pin placement design can create a problem. The wiring paths among pins and the placement of leaf cells within an abstracted functional block may be critical to an efficient implementation of its logical function and if not considered can be critical to the success of the network. One of the problems encountered with the prior art pin placement design are the need for additional re-powering circuit and wire delay—the location of the pins has an effect on the circuit delays within the abstracted functional block. In FIG. 2 the small boxes labeled i represent re-powering circuits required because of the distance between the leaf cell lc and the input/output pins located on the border of the macro. For example, the re-power circuitry is comprised of a pair of serial connected inventors needed to drive the distance between the leaf cell driver and an output pin. Another problem is perimeter crowding—the perimeter of the physical abstracted functional block can limit the number of pins that can be placed.

For example, pin placement affects circuit delay when the input pin is on one side of an abstracted functional block and the output pin is on the opposite side. The physical distance between pins may be so great that additional buffering may be required to transmit the signal or form the logic, thereby introducing additional circuit delay. The prior art techniques do not consider information about the logic within the abstracted entity when placing pins, but merely the connection between the pin and the next level of the hierarchy. The additional delay within an abstracted functional block is a result not only of the addition of extra circuits to implement the this functional block, but also because metal that comprises the wiring between the pins and the circuits of the abstracted functional block often has a higher delay characteristic than a similar connection at the next level in the hierarchy. Hierarchical designs often allocate metal layers to each level of abstraction in the hierarchy such that the lowest level of hierarchy gets the metal layers with a larger resistance per unit length, resulting in a larger delay per unit length. Therefore, as a general rule, any distance that can be traversed across an abstracted functional block on a higher level of metal (usually available at the next level of the hierarchy) rather than at the lower level of the hierarchy will take less time.

For any given pin geometry a fixed number of pins will fit per unit length of the perimeter of the abstracted functional block. In some cases the abstract's perimeter is not long enough to contain the number of pins required by that abstract. In the prior art designs, the abstract's area is increased until its perimeter is sufficiently long to accommodate the number of pins required. But this increases the distance between pins and consequentially the delay among paths. In addition, there is a non-linear increase in abstract area with increase in perimeter length, taking up silicon space merely for the sake of pin placement.

SUMMARY OF THE INVENTION

Briefly, this invention contemplates the provision of a hierarchical chip design in which pins are located at or near the physical leaf cell to which the pin connects. The invention optimizes the placement of the physical leaf circuits and uses this to determine where a pin is to be placed. This chip design results in circuits that are optimally placed based on only timing and network considerations (physical and logical), without pin placement as a factor. Pins are then placed optimally based on the circuits that they connect to, resulting in better wiring with less delay to those pins and to subsequent circuits. This design also results in an environment where it is desired to reuse the design, since it is not clear in advance to which side of an abstracted functional block access should be provided.

The invention is a process of building a physical circuit implementation of logic within an abstracted functional block, which will be referred to as a macro. The process has three fundamental steps. The initial step is to synthesize the macro without considering the locations of its input and output pins. This allows the synthesizer and placer computer aided design software to agglomerate a physical design of the circuit that best implements the specified logic function. That is to say, the location of any leaf cell is not influenced by the position of pin to which it must connect. This can be accomplished by setting the input/output (i/o) net weights in the computer aided design program to zero. The next step is to identify those leaf cells that connect to a pin and then place that pin over the leaf cell or if the pin connects to more than one leaf cell, at the centroid of the leaf cell to which it connects. Finally, an unnecessary circuitry between the pin and the logic circuitry that may have been included because of a pin's initial remote location from its logic circuitry is identified and eliminated. This can be accomplished by re-synthesizing the design with the pin locations established in accordance with the teachings of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter, which is regarded as the invention, is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic block diagram illustrating the hierarchical design of a typical electronic device such as a computer component.

FIG. 2 is a schematic block diagram illustrating the prior art design of a macro in which the input/output pins a located on the periphery of the macro.

FIG. 3 is a flow diagram of the steps in the design of functional block in accordance with the teachings of this invention.

FIG. 4 is a schematic block diagram of the macro shown in FIG. 2 but with input/output pin locations in accordance with the teachings of this invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 3 of the drawings, the initial step in the design of a macro in accordance with the teachings of this invention is to set to zero the input/output pin net weights in a suitable prior art computer automated design program used to design functional block macros. The result of this initial step is a synthesized block of leaf cells lc to implement the macro function. As explained above, in prior art synthesized designs, pin placement is determined prior to synthesizing the logical block via the abstract. The synthesis tool uses the abstract fed to it to create a synthesized block that attempts to meet logical and timing constraints based on the pin placement. In the process of this invention, the synthesized block is a result of a zero net weight synthesis resulting in the leaf cells being placed independently of pin locations in the original abstract.

In the next step, the synthesized block is compared with the functional abstract of the macro in order to create a pin grid based on the possible legal pin locations required by the abstract. Next, each required input/output pin is located at a legal pin location that is nearest to the receiving/driving leaf cell that it is intended to serve. It will be appreciated that the original abstract contains more information than just the original pin locations. The power grid locations and wiring contract locations are also contained in the abstract. When determining where to place the pins with respect to the leaf cell location, these aspects must be respected. Legal pin locations are locations exclusive of power grid and wire contact locations. For inputs serving multiple leaf cells, the legal grid point closest to the geometric center of the leaf cells is selected. The final step is the elimination of un-needed re-powering circuitry between the pin and the leaf circuit because of the pin's initial remote position from the leaf circuit. This can be accomplished by re-synthesizing the macro with the pins in the locations developed in the previous step, or by other suitable software programs.

As will be apparent from a comparison of FIGS. 2 and 4, the result is a macro with pin locations that are optimally located with respect to minimizing internal path length and internal signal delay.

The capabilities of the present invention can be implemented in software, firmware, hardware or some combination thereof.

As one example, one or more aspects of the present invention can be included in an article of manufacture (e.g., one or more computer program products) having, for instance, computer usable media. The media has embodied therein, for instance, computer readable program code means for providing and facilitating the capabilities of the present invention. The article of manufacture can be included as a part of a computer system or sold separately.

Additionally, at least one program storage device readable by a machine, tangibly embodying at least one program of instructions executable by the machine to perform the capabilities of the present invention can be provided.

The flow diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.

While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7577933 *Nov 17, 2006Aug 18, 2009Sun Microsystems, Inc.Timing driven pin assignment
US7962877 *Aug 5, 2008Jun 14, 2011International Business Machines CorporationPort assignment in hierarchical designs by abstracting macro logic
US8056025 *Feb 21, 2008Nov 8, 2011Altera CorporationIntegration of open space/dummy metal at CAD for physical debug of new silicon
Classifications
U.S. Classification257/773, 716/122
International ClassificationG06F17/50, G06F9/45
Cooperative ClassificationG06F17/5045
European ClassificationG06F17/50D
Legal Events
DateCodeEventDescription
Oct 4, 2012SULPSurcharge for late payment
Oct 4, 2012FPAYFee payment
Year of fee payment: 4
Aug 6, 2012REMIMaintenance fee reminder mailed
Nov 1, 2006ASAssignment
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BERRY, CHRISTOPHER J;CARNEY, CHRISTOPHER M;RUDE, DAVID L;AND OTHERS;REEL/FRAME:018464/0707;SIGNING DATES FROM 20061023 TO 20061101