US 20080093636 A1
A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.
1. A process for constructing the contact structure of a JFET (Junction Field Effect Transistor) comprising the steps:
forming a layer of insulating material on an upper surface of a semiconductor substrate, said substrate having an active area of semiconductor defined by field oxide formed in a semiconductor portion of said substrate;
forming a layer of nitride on a top surface of said layer of insulating material;
etching holes in said layer of insulating material where at least source, drain and gate contacts of said JFET are to be formed;
depositing a layer of polysilicon so as to fill said holes;
polishing off excess polysilicon so as to leave the remaining polysilicon in said holes flush with a top surface of said nitride layer;
doping said polysilicon in holes proximate locations where said source contact and said drain contact are going to be formed a first conductivity type;
doping said polysilicon in a hole proximate a location where said gate contact is going to be formed a second conductivity type; and
driving impurities from said polysilicon into said substrate to form gate, source, and drain regions of said JFET.
2. The process of
3. A process for fabricating a normally-off JFET (Junction Field Effect Transistor) comprising the steps:
A) forming an active area in a substrate at least a portion of which is a semiconductor material using Shallow Trench Isolation insulator, said substrate having a top surface of said semiconductor portion;
B) implanting a channel region in said active area so as to have a predetermined junction depth and predetermined doping concentration for at least one location;
C) forming a layer of insulating material having a predetermined thickness on said top surface of said substrate of said semiconductor portion;
D) etching holes in said layer of insulating material at locations where at least source, drain and gate contacts of said JFET are to be formed;
E) forming a layer of polysilicon over said insulating material layer so as to fill said holes;
F) polishing off excess polysilicon to leave remaining polysilicon filling said holes and flush with the top surface of said insulating layer formed in step C;
G) masking source, drain, and gate contact regions;
H) doping said source, drain, and gate contact regions with impurities so as to form source and drain polysilicon contacts having a first conductivity type and a gate polysilicon contact having a second conductivity type;
I) driving in said doped impurities in the source, drain and gate contacts into the underlying substrate to form source and drain regions and a gate region in said channel region; and
(J) the doping of said gate polysilicon contact and the driving in of said doped impurities are coordinated so that a gate-channel junction is formed which is located in a region disposed down from said top surface of the substrate at a distance which is less than a depth of a channel-substrate junction and is selected given the doping concentration of the gate region so as to have a zero bias voltage depletion region portion disposed below said gate-channel junction in contact with a portion of said zero bias voltage depletion region above said channel-substrate junction so as to form said normally-off JFET.
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forming a nitride layer over said field oxide layer below said layer of insulating material formed in step C, and wherein step C further comprises forming said CVD oxide over said surface of said substrate and over said nitride layer.
16. The process of
17. The process of
18. A process for forming a semiconductor device structure comprising:
forming active islands with a thermal field oxide in a substrate material;
implanting a doped-well in the active islands;
depositing a layer of oxide on the top of the substrate after forming the active islands;
masking the deposited layer of oxide for source and drain regions; and
etching the deposited layer of oxide but stopping etching of the deposited oxide layer at the thermal oxide using the deposited layer of oxide before any notch is created into the substrate.
19. The process of
20. The process of
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forming a layer of nitride on top of the oxide layer; and
polishing the device using the layer of nitride to act as a polish operation stop layer.
24. A JFET (Junction Field Effect Transistor) semiconductor device manufactured according the process of
25. A JFET (Junction Field Effect Transistor) manufactured according the process of
26. A semiconductor device structure manufactured according the process of
This is a divisional patent application and claims the benefit of priority to parent U.S. patent application Ser. No. 11/451,886 filed Jun. 12, 2006.
The invention pertains to a device structure and method for making JFET transistors at very small line widths which can overcome certain process problems caused by the small line widths.
As line widths have shrunk steadily down into the submicron range (today's line widths are 45 nanometers (NM) or 0.045 microns, where a micron is 10−6 meters and one nanometer equals 10 angstroms), all structures on CMOS, NMOS and PMOS circuits have shrunk including the thickness of the gate oxide. As line widths shrink, the voltages must be dropped to avoid punch through. This shrinking line width means the thickness of gate oxide must also be reduced so that sufficient electric field concentration to cause channel inversions in MOS devices can be achieved at the lower voltages. Shrinking gate oxide thickness causes leakage, which increases power consumption in CMOS circuits and all other MOS circuits. The limit of gate oxide thickness that will not cause leakage is about 50 nanometers, which has already been reached by the current state-of-the-art 45 nanometer line widths.
At one micron line widths, power consumption for a one square centimeter integrated circuit was 5 watts. As line widths shrink to 45 nanometers, power consumption for the same size chip could rise to 1000 watts. This can destroy an integrated circuit which is not cooled properly and is clearly unacceptable for portable devices such as laptops, cell phones etc. This power consumption complicates the design process immensely because it requires additional circuitry to put idle transistors to sleep so they do not leak. This power consumption is only one of the problems caused by shrinking line widths.
Junction field effect transistors date back to the 1950's when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field effect transistors have been reported, as follows:
In addition, a report published by R. Zuleeg titled “Complimentary GaAs Logic” dated 4 Aug. 1985 is cited herein as prior art.
A representative structure of a conventional N-channel JFET is shown in
Another problem with the JFET of
Therefore, a need has arisen for a process to fabricate normally off JFETs and a device structure, both of which eliminate the above noted etching problem and which will scale to smaller linewidths.
The teachings of this invention include eliminating the etch step whose control is so imprecise as to cause probable damage to the gate region. The novelty of the technique according to the teachings of this invention is to deposit a layer of oxide on the top of the substrate after forming the active islands with the field oxide and implanting the P-well (or N-well in the case of a P-channel JFET). Typically the oxide layer is 500 angstroms thick CVD oxide, but it could also be a “low-K” (low dielectric constant) oxide. Then the oxide layer is masked and etched to form holes where the poly source, drain, gate and substrate contacts are to be formed. The advantage of using low-K oxide over CVD oxide is that the etching of the low-K oxide for the source and drain holes will stop at the thermal oxide of the field oxide regions and not create a notch. This notch will happen if etch overshoot of CVD oxide happens; such a notch is undesirable. The reason this notch is undesirable is because if etch overshoot occurs, the field oxide outside the active area defined by the field oxide is etched down below the surface of the substrate. This causes the gate poly to dip down and form sidewall PN contacts with the gate region which, if deep enough, can short to the gate-substrate junction. Then a layer of nitride is formed on top of the oxide to act as a polish stopper. Nitride is very hard and it stops any polishing process at the nitride layer. After the holes are etched, a layer of polysilicon is deposited so as to fill the holes. The poly is then polished off until the polishing process stops at the nitride layer. Since the oxide layer is only approximately 500 angstroms (50 NM) thick typically (any reasonable depth for this layer can be picked as oxide is well behaved), the poly contacts are only 500 angstroms thick after the polishing process (or as thick as the oxide layer).
After forming the poly contacts, rough masks can be used to dope the poly of the source and drain contacts N+ and to dope the poly gate contact and P-well contact P+ (for an N-channel JFET where the opposite doping is used for a P-channel JFET and opposite substrate and channel and well doping is used also).
After doping the polysilicon, a thermal drive in step is used to drive impurities from the poly into the substrate to form the gate, source and drain regions.
For an N-channel JFET, the gate contact poly and P-well poly contact is doped P+ and the source and drain poly contacts are doped N+. For a P-channel JFET, the gate contact poly and P-well poly contact is doped N+ and the source and drain poly contacts are doped P+.
The tops of the poly contacts can have a layer of silicide formed thereon to reduce the resistance of the poly lines from about 100 ohms per square to less than 2 ohms per square to greatly increase the switching speed and frequency response of the structure. When an inverter is to be made, a normally off N-channel JFET is coupled to a normally off P-channel JFET by extending the poly gate contacts lines so as to couple the gates of the two devices together, connecting the drain of the P-channel JFET to a voltage source, connecting the source of the P-channel JFET to the drain of the N-channel JFET and connecting the source of the N-channel JFET to ground.
One solution to the increasing power consumption problem of conventional CMOS as line widths shrink is the normally off junction field effect transistor JFET, which structure is shown in
The channel is a narrow region 50 which is doped lightly N-type. The gate is a very shallow (typically 10 nanometers, hereafter NM) P-type region formed in the N-type channel by methods such as diffusion of dopants from the overlying heavily P+ doped polysilicon 75 or ion implantation.
The JFET of
The channel is a narrow region 50 which is doped lightly N-type. The gate is a very shallow (typically 10 nanometers, hereafter NM) P-type region 70 formed in the N-type channel by methods such as diffusion of dopants from the overlying heavily P+ doped polysilicon 75 or ion implantation.
A doping profile of the transistor at varying depths from the surface through the gate 70 and channel 50 is shown in
Curve 81 is a typical gate doping profile and point 85 is typically only about 10 NM from the substrate surface so the gate is very shallow. Curves 82, 83 and 84 represent the doping profile of the channel 50, the P-well 11 and the substrate bulk regions 15 respectively. The depth of the gate-channel junction is at point 85. The depth of the channel-P-well junction is at point 86 and is typically only 50 NM down from the surface of the substrate. The depth of the well-substrate junction is shown at 87. Each junction has a depletion region on either side of the junction even when the junction has zero bias across it.
As alluded to earlier, the normally off JFET device allows JFET inverters to replace MOS inverters at small line widths to get around the leakage problem. The key to this device is to design the device such that the depletion region surrounding the gate-channel junction 85 is large enough to extend down to the boundary of the depletion region surrounding the channel-well junction 86 (or channel-substrate junction 86 in the case of embodiments of
The depth of the gate-channel junction 85 has to be small because the width of the depletion layer, i.e., the distance between boundaries 90 and 92 is fixed. To achieve pinchoff, most of this depletion layer needs to be in the channel region 50 so as to meet the depletion layer surrounding the channel-well junction 86. To make this happen, the concentration of impurities in the gate region 70 must be kept much higher than the concentration of impurities in the channel region. This is done by keeping the gate region very thin thereby keeping the impurity concentration very high. If the thickness of the gate layer 70 increases, the concentration of impurities drops, the depletion region moves further into the gate layer and does not penetrate the channel region as much and the pinchoff does not occur so the device becomes a normally on device again. This design allows 1 square centimeter chips to be made using 45 NM line widths and which consume far less power than is consumed by 45 NM MOS. But the required thinness of the gate region creates a problem in the construction of the device.
The problem with forming the structure of
Etching overshoot is very likely because the poly layer deposited on the surface of the substrate from which poly contacts 71, 72, 75 and 74 will be formed is about 1500 angstroms thick and it is difficult to precisely control the depth of etching of such a poly layer because the error in etch depth is a percentage of the thickness of the layer. Therefore, a 1500 angstrom thick poly layer which has an etch stop error of 10% may go 150 angstroms too far past the surface of the substrate and etch right by the gate region and destroy the transistor. It is therefore desirable to reduce the thickness of the poly layer to reduce the etch stop error, but this is not possible because in creating thin poly layers of 1000 angstroms or less, there is very little control for reasons which are not well understood. Thus an attempt to make a 1000 or 500 angstrom thick poly layer will result in erratic layer thicknesses and eratic etch thickness control.
It is undesirable to increase the thickness of the gate region 70 because to make this region thicker increases the parasitic junction capacitance of the side junctions between the gate and source and drain regions. This parasitic junction capacitance slows the switching speed of the device down unnecessarily.
Much more precise control is required to form the source, gate and drain poly contacts above the substrate surface for reliable device fabrication.
In the non P-well embodiment of
In the P-well embodiment of
The gate region 70 in the preferred embodiments is thermally driven in using the impurities of the overlying poly gate contact 96 in the preferred embodiment. The gate region 70 is doped P+ and the time interval of the drive-in interval is kept short so that the depth of the gate-channel junction 85 is only about 10 NM from the substrate surface.
The channel region 50, in the preferred embodiments, is formed by implantation typically, and the channel-P-well junction 86 is typically only about 50 NM from the surface of the substrate. The doping of the channel and gate regions and their depths are set so that pinchoff (at zero bias across the gate-channel and channel-P-well junction) occurs by the depletion region portion below the gate-channel junction 85 extending to meet the portion of the depletion region above the channel-P-well junction 86. Poly contacts 98 and 100 are doped N+ and the impurities therein are driven into the substrate to form the source region 31 and drain region 40, both of which are doped N+. The drive-in to form the source and drain regions occurs at the same time in the same oven bake as the drive in to form the gate region 70.
In embodiments like
What is different about the embodiments of
After the oxide layer is formed, a layer of nitride is formed on top of the oxide, and then a mask is used to define photoresist which defines the locations of holes to be etched in the oxide layer 104 at the locations of the poly contacts 102, 98, 96 and 100. These holes are then etched. In alternative embodiments like that shown in
After forming the nitride layer and the holes, undoped poly is deposited so as to fill the holes and cover the oxide and nitride layers. The poly is then polished off down to the top of the nitride layer so that the poly is flush with the top of the nitride layer. Thus, the top of the poly contacts will be relatively smooth and flush with the top of the nitride layer.
Next, rough non-precision masks are used to mask off the poly contacts so that the gate poly contact 96 and the P-well poly contact 102 can be doped P+ (or vice versa if a P-channel device is being built) and the source and drain poly contacts 98 and 100 can be doped N+ (or vice versa if a P-channel device is being built).
After doping the poly layers, a drive in step is performed to bake the structure at a sufficiently high temperature to drive the dopant impurities in the poly into the substrate regions right below the poly. The time and temperature of this bake is set so as to form a shallow gate region which is sufficiently shallow (typically 10 NM) so as to remain sufficiently high in dopant concentration to cause most of the depletion region surrounding the gate-channel junction 85 to be in the N-channel region. The depth of the channel region and doping thereof is controlled so that the upper reaches of the depletion region above the channel-P-well junction 86 touches the depletion region extending down from the gate-channel junction 85 thereby causing the desired pinch off effect.
The Process of Construction of an N-Channel JFET
In embodiments where inverters are to be formed so that P-wells are necessary for the N-channel devices and N-wells are necessary for the P-channel devices, the P-well and N-well implants are performed first before forming the field oxide regions 21. These P-wells and N-wells isolate the JFETs constructed therein from surrounding structures. Typical implant energy is 50 KEV with a dose of 5E11. A P-well drive-in at 950 degrees C., N2 60′ is then performed.
The process illustrated is to build stand alone JFET's with no P-well or N-well. If an inverter is to be built, the P-well and N-well is necessary to isolate the N-channel device in the P-well from the P-channel device in the N-well and back gate surface contacts to each of the P-well and the N-well are necessary to be able to apply bias to the back gate. Details illustrating the relationship of the P-well or N-well and the substrate 13 and the P-well or N-well contact 68 and the electrical connection between the first and second conductive regions which are shown in
The N-channel implant is done so as to achieve a concentration of approximately 1018 dopant atoms per cubic centimeter. Implant energy is set to establish the channel-substrate junction 86 at about 50 NM. Other depths and doping concentrations can be selected so long as they are coordinated with the depth and doping concentration of a gate regions to be formed later so as to achieve pinchoff and normally off operation. A typical channel implant is 1E13 dosage at 15 KEV followed by another implant of 4E11 dosage at 37 KEV to achieve optimum doping profile for a normally off N-channel JFET.
In some embodiments, other insulating layers 104 that can be etched to form holes for the polysilicon could be used. Examples are nitride and a whole host of other insulating materials. However, it is necessary that thin layers such as 500 angstroms can be formed and that the insulating layer can be etched to form holes for the contacts, and it is important that the material selected does not interfere with the doping of the active area beneath the layer during its formation or during subsequent processing. The other types of insulating materials have inferior dielectric constant properties and/or inferior etching properties compared to oxide so oxide is preferred. The oxide layer 104 is preferably formed with low dielectric constant oxide (low K oxide), but Chemical Vapor Deposition (CVD) oxide can also be used so as to avoid high temperatures of thermal oxidation which could drive the channel region in further and change the junction depth. Low K oxide for layer 104 in
In an alternative embodiment, a layer of nitride 106 is formed on the top surface of the field oxide layers 21 in
The oxide layer 104 is about 500 angstroms thick in the preferred embodiment, but it can be thicker and it can be thinner in other embodiments. The rationale of choosing 500 angstroms (or any thickness less than 1000 angstroms) is to show that poly contacts of less than 1000 angstroms can indeed be built which was thought to be impossible or at least very difficult in the prior art with any degree of reliability. The difficulty in the prior art arose because of the problem of only being able to control the depth of a poly etch to within plus or minus 10% of the poly layer thickness. The invention claimed removes this difficulty by removing the poly etch step altogether and replacing it with the steps: forming an oxide layer with a nitride layer on top; etching holes for the poly contact; poly fill; and polish back to remove poly to the top of the nitride steps. The only reason the thickness of the poly matters is because of the line width. The line width controls how wide the poly contact windows are. The idea in shrinking geometries is to shrink everything so more devices can be put on the same size die. Larger dies have more faults, so yield goes down, so shrinking the line size has been the game. When 45 NM line widths can be achieved, there is a disadvantage to making the holes for the poly contacts larger than 45 NM as that requires the transistor channel region to be bigger and wastes space. Therefore, since the widths of the poly contact holes is 45 NM, the thickness of the oxide layer and the poly layer needs to be some thickness that is compatible with 45 NM hole width. Narrow holes in thick layers do not have good characteristics when using photoresist technology so 500 NM oxide layer thickness is a good choice for this linewidth but other thinner or thicker layers can be chosen given the above considerations.
The layer of nitride 106 is formed on top of the insulating layer 104 to act as a polish stop so that the step of polishing off excess polysilicon of a layer to be described below does not also remove the oxide.
The final steps to form an operative normally off JFET are carried out by stripping the photresist and annealing the structure at approximately 900 degrees C. for five seconds to drive in the source, gate and drain diffusions simultaneously. A 100 angstrom layer of titanium is then deposited, annealed and etched to form silicide connection lines to form whatever circuit is being built.
The above described process is capable of making a 45 NM or smaller normally-off JFET with no leakage. In order to achieve smaller size devices, scaling of the oxide layer and poly layer thickness downward below 500 angstroms will occur to thicknesses compatible with the smaller line width such as 25 NM.
Although the invention has been disclosed in terms of the preferred and alternative embodiments disclosed herein, those skilled in the art will appreciate that modifications and improvements may be made without departing from the scope of the invention. All such modifications are intended to be included within the scope of the claims appended hereto.