US 20080111177 A1
A non-volatile electrically erasable programmable read only memory (EEPROM) capable of storing two bit of information having a non-conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the two bit EEPROM device. The non-conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. A left and a right bit are stored in physically different areas of the charge trapping layer, near left and right regions of the memory cell, respectively. Each bit of the memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and to either the left or the right region while the other region is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near where the programming voltages were applied to. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and to either the right or the left region while the other region is grounded. Two bits are able to be programmed and read due to a combination of relatively low gate voltages with reading in the reverse direction. This greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region associated with each of the bits. In addition, both bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and either left or right regions so as to cause electrons to be removed from the corresponding charge trapping region of the nitride layer.
1. A non-volatile memory cell comprising:
a dielectric charge trapping layer located substantially above a channel junction of the cell, said charge trapping layer being adapted to be charged and discharged more than 100 cycles before degrading beyond an operable state.
2. The method according to
3. The method according to
4. The method according to
5. The method according to
6. A method of fabricating a non-volatile memory cell comprising:
depositing a dielectric charge trapping layer substantially above a channel junction of the cell, said charge trapping layer being adapted to be charged and discharged more than 100 cycles before degrading beyond an operable state.
7. The method according to
8. The method according to
9. The method according to
10. The method according to
11. A non volatile memory cell comprising:
A charge trapping layer comprised of an impure silicon based dielectric located substantially above a channel of the cell,
wherein said silicon based dielectric contains an impurity selected from the group consisting of oxygen, boron, carbon and polycrystalline silicon,
wherein said silicon based dielectric is selected from the group consisting of silicon dioxide and silicon nitride.
12. The cell according to
13. A non-volatile memory cell comprising:
a charge trapping layer at least partially including silicon nitride, wherein
said silicon nitride includes an annealed nitride portion and at least a portion of which is located substantially above a channel of the cell.
14. A non-volatile memory cell comprising:
a charge trapping layer and at least partially including silicon nitride, wherein said silicon nitride includes an annealed nitride portion and is located substantially below a gate of the cell.
15. A non-volatile memory cell comprising:
two charge trapping regions, wherein each charge trapping region is located in proximity to and above a channel junction of said cell;
wherein a thickness of said two charge trapping regions is approximately 100 angstroms or less.
16. The cell according to
17. The cell according to
18. The cell according to
19. A non-volatile memory cell comprising:
two charge trapping regions, wherein each charge trapping region is located below a gate of said cell;
wherein a thickness of said two charge trapping regions is approximately 100 angstroms or less.
20. The cell according to
21. The cell according to
22. The cell according to
This application is a continuation application of U.S. patent application Ser. No. 11/979,187, filed Oct. 31, 2007 which is a continuation application of U.S. patent application Ser. No. 11/785,285, filed Apr. 17, 2007, which is a continuation of U.S. patent application Ser. No. 11/497,078, filed Aug. 1, 2006, which is a continuation of U.S. patent application Ser. No. 10/863,529, filed Jun. 9, 2004 which is a continuation of U.S. patent application Ser. No. 10/122,078, filed Apr. 15, 2002, which is a continuation of U.S. patent application Ser. No. 09/246,183 filed Feb. 4, 1999, which is a continuation of U.S. patent application Ser. No. 08/905,286, filed Aug. 1, 1997 all of which are hereby incorporated by reference.
The present invention relates generally to semiconductor memory devices and more particularly to multi-bit flash electrically erasable programmable read only memory (EEPROM) cells that trap charge within a trapping dielectric material gate.
Memory devices for non-volatile storage of information are currently in widespread use today, being used in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM. Further description of non-volatile memory (NVM) and related semiconductor and microelectronic device technologies may be found at “Microchip Fabrication”, 1997 by Peter Van Zant (McGraw-Hill), incorporated by reference herein in its entirety.
Semiconductor ROM devices, however, suffer from the disadvantage of not being electrically programmable memory devices. The programming of a ROM occurs during one of the steps of manufacture using special masks containing the data to be stored. Thus, the entire contents of a ROM must be determined before manufacture. In addition, because ROM devices are programmed during manufacture, the time delay before the finished product is available could be six weeks or more. The advantage, however, of using ROM for data storage is the low cost per device. However, the penalty is the inability to change the data once the masks are committed to. If mistakes in the data programming are found they are typically very costly to correct. Any inventory that exists having incorrect data programming is instantly obsolete and probably cannot be used. In addition, extensive time delays are incurred because new masks must first be generated from scratch and the entire manufacturing process repeated. Also, the cost savings in the use of ROM memories only exist if large quantities of the ROM are produced.
Moving to EPROM semiconductor devices eliminates the necessity of mask programming the data but the complexity of the process increases drastically. In addition, the die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices. An advantage of EPROMs is that they are electrically programmed, but for erasing, EPROMs require exposure to ultraviolet (UV) light. These devices are constructed with windows transparent to UV light to allow the die to be exposed for erasing, which must be performed before the device can be programmed. A major drawback to these devices is that they lack the ability to be electrically erased. In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device for erasing and reprogramming.
Semiconductor EEPROM devices also involve more complex processing and testing procedures than ROM, but have the advantage of electrical programming and erasing. Using EEPROM devices in circuitry permits in-circuit erasing and reprogramming of the device, a feat not possible with conventional EPROM memory. Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e., written) and erased electrically but with the additional ability of erasing all memory cells at once, hence the term flash EEPROM. The disadvantage of flash EEPROM is that it is very difficult and expensive to manufacture and produce.
The widespread use of EEPROM semiconductor memory has prompted much research focusing on constructing better memory cells. Active areas of research have focused on developing a memory cell that has improved performance characteristics such as shorter programming times, utilizing lower voltages for programming and reading, longer data retention times, shorter erase times and smaller physical dimensions. One such area of research involves a memory cell that has an insulated gate. The following prior art reference is related to this area.
U.S. Pat. No. 4,173,766, issued to Hayes, incorporated herein by reference in its entirety, teaches a metal nitride oxide semiconductor (MNOS) constructed with an insulated gate having a bottom silicon dioxide layer and a top nitride layer.
U.S. Pat. No. 5,168,334, issued to Mitchell et al., incorporated herein by reference in its entirety, teaches a single transistor EEPROM memory cell.
A single transistor ONO EEPROM device is disclosed in the technical article entitled “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” T. Y. Chan, K. K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987 incorporated herein by reference in its entirety.
Multi-bit transistors are known in the art. Most multi-bit transistors utilize multi-level thresholds to store more than one bit with each threshold level representing a different state. A memory cell having four threshold levels can store two bits.
Achieving multiple thresholds in FLASH and EEPROM requires an initial erase cycle to bring all the memory cells below a certain threshold. Then, utilizing a methodical programming scheme, the threshold of each cell is increased until the desired threshold is reached. A disadvantage with this technique is that the programming process requires constant feedback, which causes multi-level programming to be slow.
In addition, using this technique causes the window of operation to decrease meaning the margins for each state are reduced. This translates to a lower probability of making good dies and a reduction in the level of quality achieved. If it is not desired to sacrifice any margins while increasing the reliability of the cell, then the window of operation must be increased by a factor of two. This means operating at much higher voltages, which is not desirable because it lowers the reliability and increases the disturbances between the cells. Due to the complexity of the multi-threshold technique, it is used mainly in applications where missing bits can be tolerated such as in audio applications.
Another problem with this technique is that the threshold windows for each state may change over time reducing the reliability. It must be guaranteed that using the same word line or bit line to program other cells will not interfere with or disturb the data in cells already programmed. In addition, the programming time itself increases to accommodate the multitude of different programming thresholds. Thus, the shifting of threshold windows for each state over time reduces the window of operation and consequently increases the sensitivity to disturbs.
The reduced margins for the threshold windows for the multiple states results in reduced yield. Further, in order to maintain quality and threshold margins, higher voltages are required. This implies higher electric fields in the channel, which contributes to lower reliability of the memory cell.
In order to construct a multi-bit memory cell, the cell must have four distinct levels that can be programmed. In the case of two levels, i.e., conventional single bit cell, the threshold voltage programmed into a cell for a ‘0’ bit only has to be greater than the maximum gate voltage, thus making sure the cell does not conduct when it is turned on during reading. It is sufficient that the cell conducts at least a certain amount of current to distinguish between the programmed and unprogrammed states. The current through a transistor can be described by the following equation.
The gate voltage also affects the distribution of read currents. For the same set of threshold levels, varying the gate voltage directly results in a variation of the ratio between the read currents. Therefore the gate voltage must be kept very stable. In addition, since there are multiple levels of current, sensing becomes more complex than in the two level, i.e., single bit, cell.
The following art references are related to multi-bit semiconductor memory cells.
U.S. Pat. No. 5,021,999, issued to Kohda et al., incorporated herein by reference in its entirety, teaches a non-volatile memory cell using an MOS transistor having a floating gate with two electrically separated segmented floating gates.
U.S. Pat. No. 5,214,303, issued to Aoki, incorporated herein by reference in its entirety, teaches a two bit transistor which comprises a semiconductor substrate.
U.S. Pat. No. 5,394,355, issued to Uramoto et al., incorporated herein by reference in its entirety, teaches a ROM memory having a plurality of reference potential transmission lines.
U.S. Pat. No. 5,414,693, issued to Ma et al., incorporated herein by reference in its entirety, teaches a two bit split gate flash EEPROM memory cell structure that uses one select gate transistor and two floating gate transistors.
U.S. Pat. No. 5,434,825, issued to Harari, incorporated herein by reference in its entirety, teaches a multi-bit EPROM and EEPROM memory cell which is partitioned into three or more ranges of programming charge.
The present invention discloses an apparatus for and method of programming and erasing a flash electrically erasable programmable read only memory (EEPROM). The flash EEPROM memory cell is constructed having a charge trapping non-conducting dielectric layer. The non-conducting dielectric layer functions as an electrical charge trapping medium.
An aspect of the memory device is that bits are programmed in the conventional manner, using hot electron programming. For example, the bit is programmed conventionally by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into a region of the trapping dielectric layer near the drain.
Utilizing relatively low gate voltages, the potential drop across the portion of the channel beneath the trapped charge region is reduced. A relatively small programming region or charge trapping region is possible due to the lower channel potential drop under the charge trapping region. This permits faster programming times because the effect of the charge trapped in the localized trapping region is amplified. Programming times are reduced while the delta in threshold voltage between the programmed versus un programmed states remains the same.
Another benefit is that the memory cell is enhanced. Bits of the memory cell can be erased by applying suitable erase voltages to the gate and the drain for the bit and to the gate and the source for the bit so as to cause electrons to be removed from the charge trapping region of the nitride layer. Electrons move from the nitride through the bottom oxide layer to the drain or the source for the bits, respectively.
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible.
Utilizing a thinner silicon nitride charge trapping layer helps to confine the charge trapping region to a laterally narrower region near the drain. Further, thinner top and bottom oxide sandwiching the nitride layer helps in retention of the trapped charge.
In addition, bottom and top oxide thickness can be scaled due to the deep trapping levels that function to increase the potential barrier for direct tunneling. Since the electron trapping levels are deep, thinner bottom and top oxides can be used without compromising charge retention.
Another benefit of localized charge trapping is that during erase, the region of the nitride away from the drain does not experience deep depletion since the erase occurs near the drain only. The final threshold of the cell after erasing is self limited by the device structure itself. This is in direct contrast to conventional single transistor floating gate flash memory cells which are plagued with deep depletion problems. To overcome these problems, manufacturers include complex circuitry to control the erase process in order to prevent or recover from deep depletion.
Consideration of the memory cell of the present invention is described hereinbelow. Programming the device to a low VT, by clamping the word line voltage VWL, further enhances the margin for each bit. The margin is defined as the parameters that will program one bit without affecting others.
The memory device also exhibits little or no disturb during programming. This is because during programming the drain voltage is only applied to the junction adjacent to the region where charge trapping is to occur.
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
The two bit flash EEPROM cell of the present invention can best be understood with an understanding of how single bit charge trapping dielectric flash EEPROM memory cells are constructed, programmed and read. Thus, single bit ONO EEPROM memory cells and the method used to program, read and erase them are described in some detail. Illustrated in
Programming Single Bit Memory Devices
The operation of the memory cell 41 will now be described. To program or write the cell, voltages are applied to the drain 34 and the gate 42 and the source 32 is grounded. These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating towards the drain. As they move along the length of the channel, they gain energy. If they gain enough energy they are able to jump over the potential barrier of the oxide layer 36 into the silicon nitride layer 38 and become trapped. The probability of this occurring is a maximum in the region of the gate next to the drain 34 because it is near the drain that the electrons gain the most energy. These accelerated electrons are termed hot electrons and once injected into the nitride layer they become trapped and remain stored there. Thus, the trapped charge remains in a trapping region in the nitride.
In U.S. Pat. No. 4,173,766, issued to Hayes, the nitride layer is described as typically being about 350 Angstroms thick (see column 6, lines 59 to 61). Further, the nitride layer in Hayes has no top oxide layer.
In memory cells constructed using a conductive floating gate, the charge that gets injected into the gate is distributed equally across the entire gate. The threshold voltage of the entire gate increases as more and more charge is injected into the gate. The threshold voltage increases because the electrons that become stored in the gate screen the gate voltage from the channel.
With reference to
The method of reading flash EEPROM memory cells will now be described. The conventional technique of reading both conductive floating gate and non conductive trapping gate EEPROM or flash EEPROM memory is to apply read voltages to the gate and drain and to ground the source. This is similar to the method of programming with the difference being that lower level voltages are applied during reading than during programming. Since the floating gate is conductive, the trapped charge is distributed evenly throughout the entire floating conductor. In a programmed device, the threshold is therefore high for the entire channel and the process of reading becomes symmetrical. It makes no difference whether voltage is applied to the drain and the source is grounded or vice versa. A similar process is also used to read non conductive gate flash EEPROM devices.
The process of programming typically includes writing followed by reading. This is true for all EPROM and EEPROM memory devices. A short programming pulse is applied to the device followed by a read. The read is actually used to effectively measure the gate threshold voltage. By convention, the gate threshold voltage is measured by applying a voltage to the drain and a separate voltage to the gate, with the voltage on the gate being increased from zero while the channel current flowing from drain to source is measured. The gate voltage that provides of channel current is termed the threshold voltage.
Typically, programming pulses (i.e., write pulses) are followed by read cycles wherein the read is performed in the same direction that the programming pulse is applied. This is termed symmetrical programming and reading. Programming stops when the gate threshold voltage has reached a certain predetermined point (i.e., the channel current is reduced to a sufficiently low level). This point is chosen to ensure that a ‘0’ bit can be distinguished from a ‘1’ bit and that a certain data retention time has been achieved.
The Two Bit Memory Device
A sectional view of a two bit flash EEPROM cell constructed in accordance with an embodiment of the present invention utilizing ONO as the gate dielectric is shown in
It is important to note that the two bit memory cell is a symmetrical device. Therefore, the terms source and drain as used with conventional one bit devices may be confusing. In reality, the left junction serves as the source terminal and the right junction serves as the drain terminal for the right bit. Similarly, for the left bit, the right junction serves as the source terminal and the left junction serves as the drain terminal. Thus, to avoid confusion, the terms left or first junction and right or second junction are utilized most of the time rather than source and drain. When the distinction between left and right bits is not crucial to the particular discussion, the terms source and drain are utilized. However, it should be understood that the source and drain terminals for the second bit are reversed compared to the source and drain terminals for the first bit.
Another layer of oxide 22 is formed over the charge trapping layer, (i.e., silicon nitride layer), and is preferably between approximately 60 to 100 Angstroms thick. The oxide layer 22 functions to electrically isolate a conductive gate 24 formed over the oxide layer 22 from charge trapping layer 20.
Charge trapping dielectric materials other than oxynitride/nitride may also be suitable for use as the charge trapping medium. One such material is silicon dioxide with buried islands. The silicon dioxide with polysilicon islands is sandwiched between two layers of oxide in similar fashion to the construction of the ONO memory cell in
Alternatively, the charge trapping dielectric can be constructed by implanting an impurity, such as arsenic, into a middle layer 54 of silicon dioxide deposited on top of the bottom oxide 56.
An aspect of the present invention lies in the manner in which the flash EEPROM memory cell 10 (
It is noted that throughout the discussion of the EEPROM memory cell presented below, the voltage levels discussed in connection therewith are assumed to be independent of the power supply voltage. Thus, the power supply voltages supplied to the chip embodying the EEPROM memory device may vary while the voltages applied to the gate, drain and source thereof will be supplied from regulated voltage sources.
Programming One Bit in the Forward Direction
As previously mentioned, the flash EEPROM memory cell 10 of
It is important to note that in order to be able to subsequently erase memory device 10 effectively, the programming time period must be limited. As the device continues to be programmed, the width of the charge trapping region increases. If programming continues past a certain point the charge trapping region becomes wide whereby erasing is ineffective in removing trapped charge from the nitride layer 20.
If the flash EEPROM memory cell 10 is read using the conventional technique of reading in the same direction as programming, the time needed to program the device increases to achieve the same threshold voltage. Reading in the same direction as programming means the device is programmed and read in the same forward direction. During reading, voltages having levels lower than the voltages applied during programming are applied to the gate and drain and the channel current are sensed. If device 10 is programmed (i.e., a logic ‘0’) the channel current should be very low and if the device is not programmed (i.e., a logic ‘1’) there should be significant channel current generated. Preferably, the difference in the channel current between the ‘0’ and ‘1’ logic states should be maximized in order to better distinguish between the ‘0’ and ‘1’ logic states.
As stated above, the time needed to program the flash EEPROM memory cell increases when reading occurs in the same direction (i.e., the forward direction) as programming. The reason for this will now be explained in more detail with reference to
A description of what occurs during programming is presented first followed by what occurs during reading. Note that the description that follows also may pertain to the memory cell of
When the device is read in the forward direction, a voltage is applied to the drain and the gate, for example 2V and 3V, respectively, and the source is grounded. Inversion occurs in the channel under the area of the nitride 38 that does not have trapped charge. A vertical electric field exists in the channel that spans the length of the channel up to the region of the channel underneath the trapped charge 66. In the inversion region, electrons travel in a linear fashion up to the edge 35 of the inversion region, which is beneath the left edge 33 of the trapped charge region 66. This is indicated by the line shown in the channel region in
The diagonal line under the channel in
However, if the flash EEPROM memory cell 10 (
To read the right bit of the device of
Memory cells utilizing ONO structure have had difficulty retaining the charge in the nitride layer. This is because such memory cells are programmed in a first forward direction and then read in the same direction. The reading of the programmed cell in the forward direction requires a significant amount of charge to be stored on the nitride to provide the desired increase in threshold voltage associated with the programmed cell. However, by reading in the reverse direction, less charge is required to be stored on the nitride to achieve the same increase in threshold voltage in a programmed cell.
In accordance with the present invention, by reading the memory cell in the reverse direction from which the memory cell is programmed, the amount of charge required to achieve a given threshold voltage is reduced in some cases by a factor of two or three times the amount of charge required to obtain the same threshold voltage shift when the memory cell is read in the forward direction. Accordingly, the internal electric fields generated by the charge in the nitride when the memory cell is to be read in the reverse direction are less than the internal electric fields associated with the charge stored on the nitride when the memory cell is to be read in the forward direction. Consequently electron hopping is reduced and the small amount of charge stored in the nitride does not disperse laterally through the nitride due to the internally self generated electric fields even during retention bake. Consequently, the memory cell of the present invention does not suffer the degradation in performance and reliability of prior art ONO memory cells which are programmed and read in the same direction.
Sample Flash EEPROM Device Data
Data obtained from flash EEPROM devices constructed in accordance with the present invention will now be presented to help illustrate the principles of operation thereof. A graph illustrating the difference in threshold voltage in the forward and reverse directions as a function of drain voltage for a flash EEPROM cell of the present invention that has been previously programmed is shown in
While reading in the forward direction, the threshold voltage is approximately the same as the threshold voltage when reading in the reverse direction for low drain voltages. At low drain voltages there is insufficient potential for punch through to occur. However, as the drain voltage increases while reading in the forward direction, the punch through region increases resulting in lower threshold voltage. At a high enough drain voltage, the entire portion of the channel under the trapped charge in region 68 of nitride layer 20 (
However, while reading in the reverse direction, the (VT versus VD) curve appears to follow the V, versus V D curve while reading in the forward direction at low drain voltages. However, the curves rapidly diverge for higher drain voltages and the threshold voltage for reading in the reverse direction levels off at approximately 4V. At a gate voltage VG of approximately 4V and a drain voltage VD of 1.2V, the device has reached saturation (VDSAT). At this gate voltage, any further increase in VD cannot be transferred through the inversion layer thus establishing the maximum potential drop across the portion of the channel beneath the charge trapping region 68. The VT then becomes independent of further increases in VD. For example, at a drain voltage of 1.6V, the difference in VT between reverse and forward read is almost 2V.
A graph illustrating the difference in drain current in the forward and reverse directions as a function of drain voltage for a flash EEPROM cell of the present invention that has been programmed is shown in
The drain current while reading in the reverse direction also increases with increasing drain voltage (measured at the source which functions as the drain when reading in the reverse direction) but the drain current levels off at a lower current than when reading in the forward direction. If the logic threshold for this memory cell is set to 10 μA, the forward curve can represent a logic ‘0’ and the reverse curve a logic ‘1’.
The voltage VX is defined as the voltage in the channel at a distance X from the source. Using the example presented above, the voltage VX that exists in the channel of the memory cell of the present invention (
With reference to
As is shown in the above equations, the threshold voltage in the channel is equal to the threshold voltage with the source at zero potential VT0 plus a delta threshold voltage Δ VT, which is itself a function of the voltage in the channel.
The leakage current through the channel under the region 68 of trapped charge, plotted as a function of the voltage VTC, across the portion of the channel under the charge trapping region 68 while reading in the reverse direction, is shown in
The edge of the region of trapped charge formed in the nitride layer during programming is the portion of the trapped charge that begins to affect the gate voltage required to invert the channel beneath that point.
A graph illustrating the gate voltage required to sustain a given voltage in the channel, VX, spanning the distance from the drain to the edge 27 of the channel under the edge 25 of the charge trapping area for one of the two bits while reading in the reverse direction is shown in
It is important to emphasize that the advantages and benefits of reading in the reverse direction are achieved when combined with the use of relatively low gate voltages. For a particular drain voltage, e.g., 2V, applying a high enough VG such as 5V, for example, causes the differences in threshold voltages between forward and reverse reading to fade. A graph illustrating the effect of the gate voltage VG applied during reading on the difference in drain current ID between reading in the forward direction versus reading in the reverse direction for one of the two bits is shown in
A graph illustrating the effect of the gate voltage on the difference in threshold voltage between the forward and reverse directions is shown in
Programming the Two Bit Cell
With reference to
Similarly, the left bit is programmed by applying programming voltages to the gate 24 and source 14, which now functions as the drain for the left bit. Hot electrons are injected into and trapped in the charge trapping layer 20 in the region defined by the dashed circle 21. The threshold voltage of the portion of the channel under the trapped charge comprising the left bit increases as more and more electrons are injected into the nitride layer.
A graph illustrating the effect programming one of the bits has on the other bit, which has not been previously programmed is shown in
A graph illustrating the effect programming one of the bits has on the other bit, which has been previously programmed is shown in
As shown in
Program through and read through are possible due to the relatively low gate voltages required to turn on each programmed bit when read in the forward direction as occurs when the other bit is read in the reverse direction. Another way to look at this is that a narrow charge trapping region permits punch through to be more effective. Thus the small amount of charge 68 trapped on the right edge of charge trapping layer 20 (
Another reason that the bit not being programmed is not disturbed is that the programming voltage is not being applied to the drain for the bit previously programmed. When programming the other bit, the programming voltage is applied to the drain for the bit on the other side of the device.
As discussed earlier, the programming duration must be limited for each bit in order that the other bit can still be read. For example, in the case when the right bit is programmed, i.e., a logic ‘0’, and the left bit is not programmed, i.e., a logic ‘1’, if the right bit was programmed for too long a time then when the left bit is read, there may be insufficient current for the sense amps to detect a logic ‘1’ because the channel is not sufficiently conductive. In other words, if the right bit is programmed too long, a left logic ‘1’ bit becomes slower, i.e., takes longer to read due to lower channel current, or, in the worst case, may appear to be a logic ‘0’ because the over-programmed right bit prevents the left bit from being read. Thus, a window exists in the programming time within which a logic ‘0’ bit must fall. One of the variable parameters is the voltage that is applied to the functional drain region during read. As the drain voltage is increased, a longer programming time, i.e., longer area of trapped charge, is required in order to avoid punch through. Thus, a longer trapping region is equivalent to increasing the programming time. The upper limit of the programming time for the window is the programming time such that a forward read does not change the read current by more than a predetermined percentage compared to the read current for a reverse read. Preferably, the percentage change to the read current should be limited to 10%. This percentage, although not arbitrary, can be optimized according to the design goals of the chip designer. For example, a designer may wish to have three orders of magnitude margin between the threshold voltage of a forward read and the threshold for a reverse read. To achieve this, the gate voltage, drain voltage and implant level are all adjusted accordingly to determine a maximum programming time.
The effect of programming one of the bits is that both programming and reading for the second bit is slowed somewhat. The second bit can be programmed as long as the gate voltage during programming is higher than the threshold voltage of the channel with the first bit programmed and sufficient voltage is placed on the drain. The channel resistance, however, is raised due to the programming of the fist bit. As long as programming parameters are tuned properly, the higher channel resistance does not prevent the second bit from being programmed and read. The higher channel resistance, however, does cause programming and reading of the second bit to take longer.
In reading the two bit cell, as in programming, each bit is treated as if the device was a single bit device. A sectional view of a two bit EEPROM cell constructed in accordance with a preferred embodiment of the present invention showing the area of charge trapping under the gate for both the right and the left bits is shown in
As described the right bit is read in the reverse direction by applying read voltages to the source 14 and the gate 24 and grounding the drain 16. For example, a gate voltage of 3V and a source voltage of 2V is applied. The resulting voltage in the channel VX will be something less than two volts in accordance with the graph in
A graph illustrating the effect of a low drain voltage on the read through of a programmed bit is shown in
Punch through is sensitive to the length of the trapped charge region, such as regions 68 and 70 of the structure shown in
A read of the two bit memory device of the present invention falls into one of three cases: (1) neither of the two bits are programmed (2) one of the bits is programmed and the other is not or (3) both of the bits are programmed. The first case does not require a read through. The second case requires reading through the programmed bit to read the unprogrammed bit. In this case the margin is the delta between reading a single bit in the forward direction versus the reverse direction. An example of the margin can be seen in
The third case requires read through to read both programmed bits. Programming the second bit, in fact, improves the conditions for reading the first bit. This is so because the voltage in the channel is further reduced over the case of reading a single bit. This increases the read margins between programmed and unprogrammed bits.
It is important to note that the
In the case when one of the bits is unprogrammed, i.e., no charge injected into charge trapping layer for that bit, a read of the other bit will be unaffected by this unprogrammed bit. On the other hand, however, in the case when one bit is programmed, a read of the other bit will be affected by this other programmed bit to some extent. Depending on various process parameters, the programmed bit may cause the channel to be less conductive. However, as long as the channel is sufficiently conductive both bits can still be programmed and read correctly. This is discussed in more detail below.
With reference to
It is important to note that when a semiconductor device is scaled, the channel lengths become shorter and short channel effects take hold. Thus, in the two bit memory cell, because each bit is stored in different areas of the transistor, short channel effects may become prevalent sooner than in the case of the single bit transistor. In order to retain the usable range of drain voltage, the two bit transistor may need to be scaled by a smaller factor.
Criteria Necessary For Two Bit Operation
A key concept associated with the two bit EEPROM memory cell of the present invention is that for the device to operate properly, both bits must be able to be written and read. If one of the bits is programmed, a reverse read on the programmed bit must sense a high VT, i.e., a ‘0’ and a reverse read on the unprogrammed bit must sense a low VT, i.e., a ‘1’. Thus, a reverse read on the unprogrammed bit, which is equivalent to a forward read on the programmed bit, must punch through the region of trapped charge in order to generate a high enough read current. If this does not happen, the unprogrammed bit will not be able to be read as a ‘1’, i.e., a conductive bit.
In order to achieve this goal, a sufficient margin is generated between reading in the forward and reverse directions. With reference to
There are two parameters that can be used to ensure punch through of the charge trapping region. The first is the VG, applied during reading and the second is the width of the charge trapping region. A low VG used during reading combined with a narrow charge trapping region makes punch through more effective. The lower gate voltage produces a weaker vertical electric field which causes the lateral electric field to be stronger.
It is more important to use a low VG during reading in the two bit memory cell than in the single bit memory cell. In the single bit case, it only had to be ensured that the reverse read was better than the forward read, meaning that the VT of a given bit during forward reading was lower than the VT of this bit during reverse reading. In the two bit case, however, it is not enough that the VT drops in the forward case, it must drop sufficiently to be able to punch through when reading the other bit. If the delta VT between the forward and reverse read is not sufficient, one bit cannot be read when the other bit is programmed.
Erasing Memory Devices
A consequence of using an oxide-nitride structure as opposed to an oxide-nitride-oxide structure is that during programming the charge gets distributed across the entire nitride layer, thus providing one form of single bit per cell device. The absence of the top oxide layer lowers the ability to control where the charge is stored in the nitride layer and allows holes from the gate to neutralize charge in the nitride layer, whether enhanced or adulterated with oxygen, or not. A thick nitride layer is required in order to generate sufficient charge retention in the device. However, the relatively thick nitride layer causes the charge trapping region to be very wide thus making erasing the cell difficult. Thus there is a tradeoff between charge retention and sufficiently large threshold voltage deltas on the one hand and the ability to erase the device on the other hand.
Some devices that use hot electron programming utilize an erase mechanism whereby the electrons previously trapped in the nitride are neutralized (i.e., erased) by transferring holes into the nitride. The information is erased by grounding the gate and applying a sufficient potential to the drain to cause avalanche breakdown. Avalanche breakdown involves hot hole injection and requires relatively high voltages on the drain for the phenomenon to occur. The hot holes are generated and caused to jump over the hole potential barrier of the bottom oxide between the channel and the nitride and recombine with the electrons in the nitride. This mechanism, however, is very complex and it is difficult to construct memory devices that work in this manner. Another disadvantage of using hot hole injection for erasing is that since the drain/substrate junction is in breakdown, very large currents are generated that are difficult to control. Further, the number of program/erase cycles that the memory cell can sustain is limited because the breakdown damages the junction area. The damage is caused by very high local temperatures generated in the vicinity of the junction when it is in breakdown.
Erasing the Two Bit Memory Cell
The erase mechanism of the two bit flash EEPROM memory cell 10 (
Using the right bit as an example, one technique of erasing is to simultaneously apply a negative potential to the gate 24 and a positive potential to the drain 16 such that electron tunneling occurs from the charge trapping nitride layer 20 to the drain 16 via the bottom oxide 18. The left bit is erased in a similar fashion except that a positive potential is applied to the source 14 rather than the drain 16. The electron tunneling is substantially confined to a local area near the drain 16. To facilitate the erasing of the memory cell 10 using this technique, the thickness of the bottom oxide layer 18 is suitably constructed (i.e., has a thickness of about seventy (70) Angstroms) to optimize the removal of electrons from the nitride charge trapping layer 20 into the drain 16.
Using the right bit as an example, a second well known technique is to simultaneously apply a positive voltage potential to the gate 24 and zero potential, i.e., ground, to the drain 16 such that electron tunneling occurs from the charge trapping nitride layer 20 through the top oxide 22 to the gate 24. The right bit is erased in a similar fashion with zero potential applied to the source 14. In this case, the top oxide 22 is suitably constructed (again with a thickness of about seventy (70) Angstroms) to optimize the tunneling of electrons from the nitride charge trapping layer 20 into the gate 24 in order to facilitate the erasing of the memory cell 10. In one embodiment, the top oxide 22 has a thickness of 50 Angstroms to 80 Angstroms for a voltage on gate 24 of 10 to 18 volts.
A graph illustrating the effect of programming on erase time for reading in the forward and reverse directions is shown in
As can be seen from
The erase mechanism in the memory cell is self limiting due to the fact that as the memory cell is erased, more and more positive charge is stored in the trapping region 68 (
A graph illustrating the effect of cycling on the program and erase ability of the two bit EEPROM cell is shown in
As explained previously, a result of reading in the reverse direction is that a narrower charge trapping region is required due to the higher efficiency of the reverse read. Since erasing is performed through the effective drain region 16 (for trapped charge 68 and region 14 for trapped charge 70), less charge needs to be moved off the charge trapping layer 20 and directed through the drain 16 (charge 68) or effective drain 14 (charge 70). Thus, reading the memory cell 10 in the reverse direction enables faster erase times. This makes the entire erase process easier. In one bit per cell trapping devices with diffuse charge (
A graph illustrating the effects associated with over programming on the ability to erase in the forward and reverse directions is shown in
In this case, the memory cell, which has been programmed for 100 milliseconds, does not fully erase in a reasonable time (shown in
As is apparent from
Thus, it is important to stress that, especially for the two-bit per cell localized trapping device (e.g.
The graph of
A graph illustrating the programming and erasing curves representing the use of oxide versus TEOS as the dielectric on top of the nitride is shown in
A graph illustrating erase times for a gate voltage of zero with two different values of drain voltage is shown in
A graph illustrating the erase curve for two different values of negative gate voltage is shown in
Reading the graph in
An advantage of reading in the opposite direction from programming is that the effect of the lateral electric field next to the charge trapping region is minimized. In addition, the gate voltage can be reduced to further minimize the potential in the channel. In fact, the gate voltage can be set to achieve the desired voltage in the channel. This was described previously, especially with reference to
The area of charge trapping necessary to program memory cell 41 is illustrated in
The erase mechanism is enhanced when the charge trapping region is made as narrow as possible. This allows for much more rapid and thus more efficient erasing of the memory cell.
Further, utilizing a trapping enhanced or a thinner silicon nitride charge trapping layer than disclosed in the prior art helps to confine the charge trapping region to a region near the drain that is laterally narrower than in the prior art. This improves the retention characteristic of the memory cell. Further, the thinner top and bottom oxide sandwiching the nitride layer helps retain the vertical electric field.
The voltage VX in the channel is a function of the gate voltage and the impurity level in the channel. VX is the voltage in the channel just beneath the edge of the trapped charge region above the channel (
Various thicknesses were tried for the second oxide layer 22 in the ONO structure of
The nitride layer 20 retains the stored localized (
It is also noted that as the thickness of the top oxide layer 22 increased, the lateral fields associated with the charge stored on the 50 Angstrom thick nitride layer 20 decreased slightly. It is also observed that as the thickness of the bottom oxide layer 18 was made thinner, the erase of the charge stored on the nitride layer 20 becomes easier. For a 70 Angstrom thick bottom oxide layer 18, the charge stored on the nitride layer 20 is more easily erased than if the bottom oxide layer 18 is 100 Angstroms thick.
Thus, the conclusion is that the thinner the nitride the better. Nitride layers as thin as 20 Angstroms are believed possible. The thinner nitride reduces the lateral field associated with a given charge stored in the nitride layer and thus reduces the lateral dispersion of the stored charge as a result of the internally generated electric field associated with the stored charge.
In terms of optimization, three parameters can be varied to give the quickest programming time and the widest margins. The first parameter is the channel length. A longer channel length, for a given programming time when reading in the reverse direction, increases the distance between the drain and the trapped charge (effectively, the source and drain designations are flipped). This lowers the level of the lateral electric field even lower.
The second parameter, as described previously, is the gate voltage which can be set to minimize the voltage drop in the channel across the channel region beneath the trapped charge. This further reduces the lateral electric field in the channel beneath the trapped charge. Within limits, the voltage in the channel can be ‘dialed in’ by varying the voltage on the gate. This allows control over the voltage drop in the channel beneath the region of trapped charge. If the gate voltage is made too low then reading a logic ‘1’, i.e., the unprogrammed state, becomes problematic. The gate voltage for reading a logic ‘1’ must be still high enough to generate inversion in order to produce sufficient read current for each sense amplifier. Thus, a lower limit for the gate voltage is approximately 1V above the threshold voltage. The lower limit for the gate voltage is determined by the maximum time required to sense the channel current which represents one state of the memory cell. For example, for fast access time, the maximum time would be in the range of 10 to 30 nanoseconds while for a mass storage device the maximum access time could be as high as 1 microsecond. The actual gate voltage to achieve these maximum times would depend upon the device structure, the dielectric thickness, the bit line capacitance, the doping concentration in the channel and other parameters associated with the device. An upper limit on the gate voltage is the voltage at which the voltage in the channel just beneath the edge of the region of trapped charge is just below the voltage potential applied to the source terminal during reading in the reverse direction. A too high gate voltage will cause inversion in the channel. Thus, it is not recommended to apply a gate voltage that generates such a high voltage in the channel beneath the edge of the charge trapping region because it defeats the benefits of having a lower potential across the portion of the channel beneath this charge trapping region with the accompanying reduction in leakage current and shortened programming time. In a preferred embodiment of the present invention, the gate voltage used for reading is approximately 3V which represents an optimized tradeoff between programming time and leakage current.
The third optimization method, previously described, is to vary the boron doping of the channel region under the gate. An increase in the doping concentration results in a higher threshold voltage VT and a lower voltage generated in the channel. This is due to the reduction in the width of the depletion region formed. Thus, a higher doping concentration permits a higher gate voltage to be applied for the same voltage across the portion of the channel beneath the charge trapping region.
In addition, an increase in the NA doping concentration for the same length trapping region will improve the punch through behavior of the device. By varying the level of boron implanted in the channel region, the width of the depletion region under the gate can be varied. An increase in the doping concentration results in a reduction in the width of the depletion region for the same applied gate voltage. The reduction in the width of the depletion region occurs because there is now more fixed charge in the substrate. Thus, varying the doping concentration can be used to limit the length of the pinchoff region under the gate. In addition, the doping concentration can be used to increase or decrease the initial threshold voltage of the device.
Optimization parameters specific to programming and reading a two bits per gate memory cell will now be described. The optimizations for programming include utilizing a longer minimum effective channel length Leer in order to physically separate the two bits better. In addition, the implant level can be reduced in the channel in order to increase the delta between forward and reverse programming. On the other hand, the implant level can be increased in the channel in order to reduce the impact of the first bit on the programming of the second bit. Thus, the implant level in the channel is a compromise between the forward and reverse delta on the one hand and the programming speed on the other hand.
The optimizations for reading include lowering the gate voltage in order to enhance the punch through during reading. As described previously, punch through is necessary to program and read the second bit. A lower implant level in the channel serves to increase punch through. Also, a higher drain voltage during read functions to increase punch through. These three optimizations relate to reading in the forward direction, which is equivalent to reading the second bit in the reverse.
In addition, a lower gate voltage reduces the number of electrons that need to be injected into the charge trapping region. This improves erasing because it eliminates residual charge remaining trapped after erasure. Any residual charge that remains in the charge trapping layer after erasure degrades cycling.
While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.