US20080116524A1 - Dual stress liner - Google Patents
Dual stress liner Download PDFInfo
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- US20080116524A1 US20080116524A1 US12/018,851 US1885108A US2008116524A1 US 20080116524 A1 US20080116524 A1 US 20080116524A1 US 1885108 A US1885108 A US 1885108A US 2008116524 A1 US2008116524 A1 US 2008116524A1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
Abstract
A semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.
Description
- This is a Divisional of U.S. patent application Ser. No. 11/383,560, filed May 5, 2006.
- The present invention relates to semiconductor devices and their fabrication and more particularly to semiconductor devices in which a stress is applied to the semiconductor device.
- In fabricating integrated circuits in conventional bulk semiconductor wafers, wells of either p-type or n-type conductivity are implanted in a substrate of the opposite conductivity. However, in complementary metal oxide semiconductor (CMOS) technology, both p-type and n-type wells are utilized. Source/drain regions are formed by implanting diffusion regions of the opposite n-type or p-type conductivity as the wells to form metal-oxide-semiconductor field effect transistors (MOSFETs). The carrier mobility in a transistor can be increased when a stress of sufficient magnitude is applied to the conduction channel of a transistor to create a strain therein. An increase in the performance of an n-type field effect transistor (NFET) can be achieved by applying a tensile longitudinal stress to the conduction channel of the NFET. An increase in the performance of a p-type field effect transistor (PFET) can be achieved by applying a compressive longitudinal stress to the conduction channel of the PFET.
- A stress-imparting film, also referred to herein as a “stressed” film, can be deposited to cover a semiconductor device region to impart a stress thereto for enhancing the conductivity of a transistor, for example, an NFET or a PFET device. Silicon nitride is one material, among others, which can be deposited in such way that the resulting material layer imparts either a tensile stress or a compressive stress to a layer of a second material with which it is in contact. To improve the conductivity of both an NFET and a PFET, a tensile stress-imparting nitride can be formed to cover an NFET device region and a compressive stress-imparting nitride can be formed to cover a PFET device region.
- From a fabrication point of view, such a goal can be accomplished by applying two films, each having a different internal stress. In such case, one
stressed film 102 can be patterned with anoverlying oxide layer 103, after which asecond film 104 is deposited and then patterned to produce the overlappedfilms 100 at theboundary 220, as illustrated in the cross-sectional depiction ofFIG. 1 . The overlappedfilms 100, however, can create certain problems. - One such problem concerns the fabrication of a contact via 210 through
dielectric layer 212 for conductively contacting thesilicided polysilicon conductor 225 overlying a shallow trench isolation (STI)region 110 at theboundary 220 between two differently stressedfilms boundary 220 can be difficult to perform while etching other contact holes, such as the contact hole for contact via 230 to thesilicide region 203 that overlies the active device region 202 (FIG. 2 ). The difficulty arises because of the difference between the relatively large thickness of theaggregated films silicided polyconductor 225, as compared to the smaller thickness of thestressed film 102 which overlies thesilicide layer 203 above theactive device region 202. - Because of this difference in the total film thicknesses, the contact hole for the contact via 210 is less likely to be etched to a sufficient depth to properly contact the
silicided polysilicon conductor 225. A contact open failure can result, as best seen at 220 inFIG. 1 . A contact open failure is one in which much higher than normal contact resistance occurs at the interface between the contact via 210 and the polysilicon conductor. A contact open failure can occur when the contact hole fails to be etched sufficiently to contact thesilicide layer 222. On the other hand, extending the etching depth to prevent a contact open failure with respect to the contact via 210 could also cause thesuicide region 203 and/or theactive device region 202 to be excessively over-etched. It is desirable that the contact hole for forming the contact via 230 be etched to a depth that falls just below themajor surface 205 of thesilicide region 203. When the contact hole is over-etched excessively, i.e., to a depth below thesilicide layer 203, thesemiconductor device region 202 can exhibit excessive junction leakage. - Consequently, a need exists for a structure and an associated method of fabricating a semiconductor device in which more than one stressed film can be provided, while permitting contact holes to both the silicided polyconductor and to the active device region to be etched with less difficulty.
- According to an aspect of the invention, a semiconductor device structure is provided which includes a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying the first channel region. A second FET is included which has a second channel region, a second source region, a second drain region and a second gate conductor overlying the second channel region. The first and second gate conductors are portions of a single elongated conductive member extending over both the first and second channel regions. A first stressed film overlies the first FET, the first stressed film applying a stress having a first value to the first channel region. A second stressed film overlies the second FET, the second stressed film applying a stress having a second value to the second channel region. The second value is substantially different from the first value. In addition, the first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at the common boundary.
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FIG. 1 is a sectional view illustrating a semiconductor device structure over which two films, each having a different internal stress are applied and patterned to create an overlapped boundary, at which a first conductive contact via is to be formed. -
FIG. 2 is a sectional view illustrating a different location of the semiconductor device structure shown inFIG. 1 , at which a second conductive contact via is to be formed. -
FIG. 3 is a top-down plan view illustrating a structure including first and second transistors with abutting stressed films, in accordance with one embodiment of the present invention. -
FIG. 4 is a partial sectional view through line A-A′ illustrating the structure shown inFIG. 3 . -
FIG. 5A is a partial sectional view through line X-X′ ofFIG. 3 , illustrating a particular stage of fabricating the structure shown inFIG. 3 . -
FIG. 5B is a corresponding partial sectional view through line Y-Y′ ofFIG. 3 , further illustrating the particular stage of fabricating the structure shown inFIG. 3 . -
FIG. 5C is a corresponding partial sectional view through line A-A′ ofFIG. 3 , further illustrating the particular stage of fabricating the structure shown inFIG. 3 . -
FIGS. 6A, 6B and 6C are respective corresponding views illustrating a stage of fabricating the structure shown inFIG. 3 subsequent to the stage of fabrication illustrated inFIGS. 5A, 5B and 5C. -
FIGS. 7A, 7B and 7C are respective corresponding views illustrating a stage of fabricating the structure shown inFIG. 3 subsequent to the stage of fabrication illustrated inFIGS. 6A, 6B and 6C. -
FIGS. 8A, 8B and 8C are respective corresponding views illustrating a stage of fabricating the structure shown inFIG. 3 subsequent to the stage of fabrication illustrated inFIGS. 7A, 7B and 7C. -
FIGS. 9A, 9B and 9C are respective corresponding views illustrating a stage of fabricating the structure shown inFIG. 3 subsequent to the stage of fabrication illustrated inFIGS. 8A, 8B and 8C. -
FIG. 3 is a top-down illustrating an embodiment of the present invention. As illustrated inFIG. 3 ,semiconductor device regions FIG. 3 , thesemiconductor device regions individual regions source region 303, adrain region 305 and a source-drain conduction path inregion 302 extending between the source region and the drain region, the conduction path extending through achannel region 310 of the PFET. An n-type field effect transistor (“NFET”) has asource region 307, adrain region 309 and a source-drain conduction path inregion 304 extending between the source region and the drain region, the conduction path extending through achannel region 311 of the NFET. - The
semiconductor device regions - A conducting
member 330 includes portions functioning as thegate conductors channel region 310 of the PFET and over the channel region of the NFET. The conducting member also extends over theSTI region 350 provided between the two semiconductor regions. Thus, the conducting member extends over bothsemiconductor regions outer end 306 of thePFET device region 302 to theouter end 308 of theNFET device region 304. The conductingmember 330 also maintains thegate conductors member 330 is a “polyconductor” which includes polysilicon to provide workfunction matching, the polyconductor functioning as the transistor gates for both the PFET and NFET. Further details of such multi-layer current conducting member are described below. -
Dielectric spacers 380, which preferably include an oxide of silicon as at least an outermost layer, are disposed on sidewalls of the conducting member.Stressed films device regions member 330. The dimensions of the stressed films need not be as shown inFIG. 3 , in that the stressed films can occupy smaller or larger areas. The locations of theedges 403, 405 of the stressed films need not be as shown, and need not be aligned with each other. However, in any case, thestressed films common boundary 407 which overlies the STI region between the twosemiconductor regions - As also illustrated in
FIG. 3 , a contact via 342 is provided in conductive communication with the conductingmember 330. A separate contact via to the source region of the PFET is illustrated at 344. For ease of reference, only onesuch contact 344 via to the source of the PFET is illustrated inFIG. 3 . Typically, contacts similar to that shown at 344 are provided to both the source and drain regions of both the PFET and NFET. Such contact vias 342, 344 are made by forming contact holes at the respective locations and subsequently filling them with a conductive material. Preferably, the conductive material includes one or more metals or conductive compounds of metals and may include one or more materials selected for their properties in enhancing adhesion between the conductive via 342 and the conductingmember 330 and/or in forming a barrier against electromigration or other movement of molecules of conductive materials between the conductive via 342 and the conductingmember 330. -
FIG. 4 is a cross-sectional view, through line A-A, of the embodiment shown inFIG. 3 . As illustrated inFIG. 4 , the conductingmember 330 preferably has multiple layers with afirst layer 334 including a material such as doped polysilicon and a low-resistancesecond layer 332 including a low resistance conducting material such as one or more metals or conductive compounds of metals. Preferably, the low-resistancesecond layer 332 includes a conductive silicide of a metal. The conductive silicide can include one or more of tungsten silicide, nickel silicide, cobalt silicide or titanium silicide, among others. - The first stressed
film 402 preferably has an internal compressive stress such that it applies a compressive stress to thesemiconductor region 302 of the PFET with which it is in contact. Preferably, such stressedfilm 302 enhances the performance of the PFET. The second stressedfilm 404 preferably has an internal tensile stress such that it applies a tensile stress to thesemiconductor region 304 of the NFET with which it is in contact. Similarly, such stressedfilm 304 enhances the performance of the NFET. Preferably, the stressed film includes a material such as silicon nitride (Si3N4). By varying the conditions (e.g., vapor pressure and temperature) under which a silicon nitride is deposited, a stressed film can be formed which has a particular type of internal stress (i.e., either compressive or tensile) and a particular magnitude of such stress. These parameters, i.e., stress type and magnitude, can be referred to collectively as the “value” of the stress. - A preferred method of fabricating the structure illustrated in
FIGS. 3 and 4 will now be described. Referring toFIGS. 5A, 5B and 5C, in a particular stage of fabrication, thePFET 300 and NFET 301 have already been formed. A first stressedfilm 402 having an internal stress with a first value is deposited to cover thePFET 300 and theNFET 301. Preferably, the stressed film includes silicon nitride, preferably being stoichiometric silicon nitride (Si3N4). - As particularly shown in
FIG. 5A , the conductingmember 330 functions as a gate conductor of thePFET 300, the conducting member including apolyconductor portion 334 and a low-resistance layer 322 overlying the polyconductor portion. The conductingmember 330 is spaced from thechannel region 310 by agate dielectric 321 and is flanked bydielectric spacers 380. As also shown inFIG. 5A , eachdielectric spacer 380 has a dual structure including afirst spacer 382 having an L-shape and asecond spacer 384 overlying the L-shaped spacer. The first L-shaped spacer preferably includes or consists essentially of an oxide such as an oxide of silicon, e.g., silicon dioxide. The second spacer preferably includes silicon nitride; however, alternatively, the second spacer can include an oxide of silicon such as silicon dioxide. A similar structure is illustrated inFIG. 5B , in which the conductingmember 330 overlies thechannel region 310 of the NFET. - Preferably, the stressed
film 402 is formed in such way that it covers each of thesource region 303,drain region 305, and the conductingmember 330 to a height above thechannel region 310 which exceeds that of the conducting member. To achieve this result, it may be necessary to utilize a process in which the stressed film material is deposited by a combined process of deposition and etching. In one exemplary process, the stressed film material can be initially deposited under a first set of deposition conditions in which deposition predominates over etching. Subsequently, the deposition conditions are altered such that etching becomes predominant. Typically, an additional deposition step raises the height of the stressed film to the desirable level. Alternatively, the initial cycle of one deposition step followed by one etching step can be followed by one or more additional cycles of deposition and etching to form the stressedfilm 402. - After forming the stressed
film 402 to the desired height above the channel region 310 (FIG. 5A ), astop layer 406 is then deposited to overlie the first stressedfilm 402. Thestop layer 406 preferably is formed as a conformal layer, i.e., a layer which conforms to the topography of the stressedfilm 402 which it covers. Alternatively, the stop layer can be of the planarizing type which tends to fill gaps and reduce topography. The stop layer preferably is formed by a low temperature oxide (“LTO”) deposition, which may include deposition using a TEOS (tetraethylorthosilicate) precursor, or alternatively a silane precursor. In a particular embodiment, the stop layer can be formed by deposition of doped or undoped silicate glass. In another embodiment, the stop layer can be formed by deposition and subsequent baking of a spin-on-glass material. -
FIG. 5C illustrates the first stressedfilm 402 and stoplayer 406 overlying the stressed film, as results at a location of the structure where later a conductive via will be formed to contact at least one of the low-resistance layer 332 or thepolyconductor portion 334 of the conductingmember 330, as overlies anSTI region 350 between the first andsecond semiconductor regions - As further illustrated in
FIGS. 6A, 6B and 6C, after the first stressedfilm 402 is formed, thestop layer 406 and first stressed film are selectively removed from the structure where they overlie thesecond semiconductor region 304. Thestop layer 406 andfilm 402 is also removed from the structure where it overlies aportion 412 of the STI region 350 (FIG. 6C ) that separates thefirst semiconductor region 302 from thesecond semiconductor region 304. This step is performed, for example, by depositing and photolithographically patterning a photoresist to provide an opening which exposes a portion of the stop layer and the first stressed film. Thereafter, thestop layer 406 and the first stressedfilm 402 are removed by selective etching, for example. Either wet or dry etching, e.g., reactive ion etching, can be used to remove these layers. At the conclusion of this step, thestop layer 406 and the first stressedfilm 402 remain in place overlying the PFET 300 (FIG. 6A ) but are removed from the NFET 301 (FIG. 6B ). - Thereafter, the second stressed film is formed. The second stressed film preferably has a tensile internal stress rather than a compressive internal stress which is characteristic of the first stressed film. Referring to
FIGS. 7A, 7B and 7C, the second stressedfilm 404 is formed to overlie theNFET 301, thePFET 300, as well as thestop layer 406 and the first stressedfilm 402 which cover thePFET 300. As initially formed, the second stressedfilm 404 typically conforms to topography including the conductingmember 330 which underlies it. However, as in the case of the first stressed film, the second stressed film may have a planarizing property which reduces the topography of the stressed film in relation to the topography which underlies it. As in the case of depositing the first stressedfilm 402, the second stressed film can be formed by successive deposition and etching steps, such as a sequence of a deposition step followed by an etching step followed by another deposition step, for example. As illustrated inFIG. 7C , at the conclusion of this step of processing, aportion 408 of the second stressedfilm 404 overlaps thestop layer 406 and the first stressedfilm 402 above theSTI region 350. - Next, as illustrated in
FIGS. 8A, 8B and 8C, further processing is performed to planarize the structure, in a manner that stops on thestop layer 406. Preferably, a chemical mechanical polishing (“CMP”) process is applied to an exposed surface of the substrate. In such way, the CMP process removes topography of the first stressedfilm 402 and the second stressedfilm 404. In addition, the CMP process effectively removes the portion of the second stressed film that overlies thestop layer 406, such that the structure is as illustrated inFIG. 8A . In such way, the CMP process planarizes the first and second stressedfilms FIGS. 8A, 8B and 8C. - Thereafter, as further illustrated in
FIGS. 9A, 9B and 9C, the stop layer preferably is removed from the structure, such as through wet chemical etching. Subsequently, an interlevel dielectric layer (“ILD”) 410 is deposited to overlie the structure. However, when the stop layer consists essentially of an oxide, especially an oxide of silicon and the subsequently deposited ILD consists essentially of an oxide of silicon, the stop layer preferably is not removed prior to depositing the ILD. Preferably, the ILD is deposited to contact the first stressedfilm 402 overlying the PFET 300 (FIG. 9A ) and such that the ILD contacts the second stressedfilm 404 overlying the NFET 301 (FIG. 9B ). As particularly shown inFIG. 9C , the ILD overlies theboundary 407 where the first stressedfilm 402 abuts the second stressedfilm 404 and neither one of the stressed films overlaps the other stressed film. The ILD preferably includes an oxide. However, alternatively, the ILD can be formed by any suitable process which may include the deposition of an organic material, e.g., silicon low-K (“SILK”) dielectric material. - After the
ILD 410 is formed, a contact hole is etched to coincide with theboundary 407 between the first and second stressed films, after which the contact hole is filled with one or more metals or conductive compounds of metals to form thecontact 342 is illustrated inFIGS. 3 and 4 . Simultaneously, one or more contact holes are etched to contact at least one of the source and drain regions of each of the NFET and PFET transistors, and these one or more contact holes are filled with one or more metals or conductive compounds of metals to form one or more contact vias such as the contact hole shown at 344 inFIG. 3 . - In a variation of the above-described method, the places of the NFET and the PFET are switched. In addition, the first stressed film preferably has a tensile stress while the second stressed film preferably has a compressive stress. In such case, the first stressed film remains as a stressor film overlying the NFET while the later formed second stressed film is formed to overlie the PFET.
- From the foregoing described structure and method, the following advantages are apparent. The process of etching contact holes is improved because the first and second stressed films do not overlap and have uniform thickness both where they overlie the polyconductor and where they overlie the source region or drain region of each FET. Another advantage is that the first and second stressed films can be made thicker than was possible heretofore. Thicker stressed films can impart greater stress than heretofore because of their greater thickness covering the source and drain regions of each FET. A third advantage is that only one photomask is used to define the locations of the first and second stressed films and only one masking step is needed to define the common boundary between the first and second stressed films.
- While the invention has been described in accordance with certain preferred embodiments thereof, many modifications and enhancements can be made thereto without departing from the true scope and spirit of the invention, which is limited only by the claims appended below.
Claims (10)
1. A semiconductor device structure, comprising:
a first field effect transistor (“FET”) having a first channel region, a first source region, a first drain region and a first gate conductor overlying said first channel region;
a second FET having a second channel region, a second source region, a second drain region and a second gate conductor overlying said second channel region, said first and second gate conductors being portions of a single elongated conductive member extending over both said first and second channel regions;
a first stressed film overlying said first FET, said first stressed film applying a stress having a first value to said first channel region; and
a second stressed film overlying said second FET, said second stressed film applying a stress having a second value to said second channel region, said second value being substantially different from said first value,
wherein said first and second stressed films abut each other at a common boundary and present a substantially co-planar major surface at said common boundary.
2. The semiconductor device structure as claimed in claim 1 , wherein neither one of said first and second stressed films overlaps the other one of said first and second stressed films at said common boundary.
3. The semiconductor device structure as claimed in claim 2 , further comprising an interlevel dielectric layer (“ILD”) overlying said first and second stressed films, said conductive via extending through said ILD and said first and second stressed films at said common boundary to contact said conducting member.
4. The semiconductor device structure as claimed in claim 2 , wherein said first value is compressive and said second value is tensile.
5. The semiconductor device structure as claimed in claim 4 , wherein said first FET includes a PFET and said second FET includes an NFET.
6. The semiconductor device structure as claimed in claim 2 , wherein said first source region, first channel region and first drain region of said first FET are provided in a first semiconductor region, said second source region, second channel region and second drain region are provided in a second semiconductor region, said semiconductor device structure further comprising at least one isolation region separating and electrically isolating said first and second semiconductor regions.
7. The semiconductor device structure as claimed in claim 2 , wherein major surfaces of said first and second stressed films are at least substantially planar.
8. The semiconductor device structure as claimed in claim 2 , wherein said first and second gate conductors include top surfaces remote from said first and second channel regions, respectively, and said first and second stressed films overlie said top surfaces of said first and second gate conductors.
9. The semiconductor device structure as claimed in claim 2 , wherein said first stressed film and said second stressed film each consist of nitride.
10. The semiconductor device structure as claimed in claim 9 , wherein said first and said second semiconductor regions consist essentially of silicon and said nitride includes silicon nitride.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/018,851 US20080116524A1 (en) | 2006-05-16 | 2008-01-24 | Dual stress liner |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/383,560 US7361539B2 (en) | 2006-05-16 | 2006-05-16 | Dual stress liner |
US12/018,851 US20080116524A1 (en) | 2006-05-16 | 2008-01-24 | Dual stress liner |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/383,560 Division US7361539B2 (en) | 2006-05-16 | 2006-05-16 | Dual stress liner |
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US12/080,016 Expired - Fee Related US7943454B2 (en) | 2006-05-16 | 2008-03-31 | Method for dual stress liner |
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US7521307B2 (en) * | 2006-04-28 | 2009-04-21 | International Business Machines Corporation | CMOS structures and methods using self-aligned dual stressed layers |
US7361539B2 (en) * | 2006-05-16 | 2008-04-22 | International Business Machines Corporation | Dual stress liner |
US7585720B2 (en) * | 2006-07-05 | 2009-09-08 | Toshiba America Electronic Components, Inc. | Dual stress liner device and method |
US8288218B2 (en) * | 2010-01-19 | 2012-10-16 | International Business Machines Corporation | Device structure, layout and fabrication method for uniaxially strained transistors |
US8169025B2 (en) * | 2010-01-19 | 2012-05-01 | International Business Machines Corporation | Strained CMOS device, circuit and method of fabrication |
US8466513B2 (en) | 2011-06-13 | 2013-06-18 | Semiconductor Components Industries, Llc | Semiconductor device with enhanced mobility and method |
US8492218B1 (en) | 2012-04-03 | 2013-07-23 | International Business Machines Corporation | Removal of an overlap of dual stress liners |
US8778764B2 (en) | 2012-07-16 | 2014-07-15 | Semiconductor Components Industries, Llc | Method of making an insulated gate semiconductor device having a shield electrode structure and structure therefor |
US9105559B2 (en) | 2013-09-16 | 2015-08-11 | International Business Machines Corporation | Conformal doping for FinFET devices |
US9269779B2 (en) | 2014-07-21 | 2016-02-23 | Semiconductor Components Industries, Llc | Insulated gate semiconductor device having a shield electrode structure |
DE102015106689A1 (en) * | 2015-04-29 | 2016-11-03 | Infineon Technologies Ag | A method of manufacturing a semiconductor device with tilted ion implantation processes, semiconductor device and integrated circuit |
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US7361539B2 (en) * | 2006-05-16 | 2008-04-22 | International Business Machines Corporation | Dual stress liner |
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TW400561B (en) * | 1998-06-08 | 2000-08-01 | United Microelectronics Corp | The manufacturing method of the self-aligned salicide |
KR100784603B1 (en) * | 2000-11-22 | 2007-12-11 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and method for fabricating the same |
US6709935B1 (en) * | 2001-03-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Method of locally forming a silicon/geranium channel layer |
KR100441682B1 (en) * | 2001-06-14 | 2004-07-27 | 삼성전자주식회사 | Semiconductor device having LDD-type source/drain regions and fabrication method thereof |
JP4173672B2 (en) * | 2002-03-19 | 2008-10-29 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
US6890808B2 (en) * | 2003-09-10 | 2005-05-10 | International Business Machines Corporation | Method and structure for improved MOSFETs using poly/silicide gate height control |
US7064027B2 (en) * | 2003-11-13 | 2006-06-20 | International Business Machines Corporation | Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance |
US7118999B2 (en) * | 2004-01-16 | 2006-10-10 | International Business Machines Corporation | Method and apparatus to increase strain effect in a transistor channel |
US7381609B2 (en) * | 2004-01-16 | 2008-06-03 | International Business Machines Corporation | Method and structure for controlling stress in a transistor channel |
US6881635B1 (en) * | 2004-03-23 | 2005-04-19 | International Business Machines Corporation | Strained silicon NMOS devices with embedded source/drain |
US20050214998A1 (en) | 2004-03-26 | 2005-09-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Local stress control for CMOS performance enhancement |
US7002209B2 (en) * | 2004-05-21 | 2006-02-21 | International Business Machines Corporation | MOSFET structure with high mechanical stress in the channel |
US6984564B1 (en) * | 2004-06-24 | 2006-01-10 | International Business Machines Corporation | Structure and method to improve SRAM stability without increasing cell area or off current |
US7098536B2 (en) * | 2004-10-21 | 2006-08-29 | International Business Machines Corporation | Structure for strained channel field effect transistor pair having a member and a contact via |
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US7361539B2 (en) * | 2006-05-16 | 2008-04-22 | International Business Machines Corporation | Dual stress liner |
US20080185657A1 (en) * | 2006-05-16 | 2008-08-07 | Xiangdong Chen | Dual stress liner |
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US7943454B2 (en) | 2011-05-17 |
US20070269942A1 (en) | 2007-11-22 |
TW200802855A (en) | 2008-01-01 |
US7361539B2 (en) | 2008-04-22 |
US20080185657A1 (en) | 2008-08-07 |
CN100533739C (en) | 2009-08-26 |
CN101075617A (en) | 2007-11-21 |
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